---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: xilinx-bufg.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Model of Xilinx BUFG component to allow design to simulate
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity BUFG is
  port (I   : in    std_ulogic;
        O   : out   std_ulogic);
end entity BUFG;

architecture Behave of BUFG is
begin

  O <= I;

end Behave;

