Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.3: Invalid unit type: 1139238728
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.4: Invalid unit type: DT/root/rapidaq/fw/SharedComps/src/BlockRam.vhd
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.6: Invalid unit type: 1139238729
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.7: Invalid unit type: oot/rapidaq/fw/SharedComps/src/BlockRam.vhd
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.10: Invalid unit type: 1139238732
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.11: Invalid unit type: DT/root/rapidaq/fw/SystemFpga/src/FpgaProg.vhd
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.12: Invalid unit type: 9
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/FpgaProg.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.15: Invalid unit type: 1139238732
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.16: Invalid unit type: daq/fw/SystemFpga/src/SystemFpgaTop.vhd
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/SystemFpgaTop.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.19: Invalid unit type: 1135025687
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.20: Invalid unit type: ONENTS
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/SystemFpgaTop.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.23: Invalid unit type: 1139238736
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.26: Invalid unit type: 1139238730
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.27: Invalid unit type: DT/root/rapidaq/fw/SystemFpga/src/LbusCont.vhd
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.28: Invalid unit type: 9
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/LbusCont.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.31: Invalid unit type: 1139238730
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.32: Invalid unit type: daq/fw/SystemFpga/src/EepromCtrl.vhd
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/EepromCtrl.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.35: Invalid unit type: 1135025687
WARNING:HDLParsers:3300 - Invalid date.time ("\") scanned for file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/src/EepromCtrl.vhd in dependency database.
WARNING:HDLParsers:11 - xst/work/hdpdeps.ref.38: Invalid unit type: 1139238734
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <blockram> (Architecture <syn>).
Entity <blockram> analyzed. Unit <blockram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <blockram>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <blockram> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <blockram> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.2.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block blockram, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of bonded IOBs:                 71  out of    180    39%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pClk                               | BUFGP                  | 2     |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: No path found
   Minimum input arrival time before clock: 5.010ns
   Maximum output required time after clock: 10.481ns
   Maximum combinational path delay: No path found

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -i -p xc2s50-fg256-5
blockram.ngc blockram.ngd 

Reading NGO file
"d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/blockram.ngc" ...
Reading component libraries for design expansion...

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 37056 kilobytes

Writing NGD file "blockram.ngd" ...

Writing NGDBUILD log file "blockram.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
Logic Distribution:
    Number of Slices containing only related logic:      0 out of      0    0%
    Number of Slices containing unrelated logic:         0 out of      0    0%
        *See NOTES below for an explanation of the effects of unrelated logic
   Number of bonded IOBs:            71 out of    176   40%
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%

Total equivalent gate count for design:  32,768
Additional JTAG gate count for IOBs:  3,456
Peak Memory Usage:  55 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "blockram_map.mrp" for details.
Completed process "Map".

Mapping Module blockram . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o blockram_map.ncd blockram.ngd blockram.pcf
Mapping Module blockram: DONE



Started process "Place & Route".





Constraints file: blockram.pcf

Loading device database for application Par from file "blockram_map.ncd".
   "blockram" is an NCD, version 2.38, device xc2s50, package fg256, speed -5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.2.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs            71 out of 176    40%
      Number of LOCed External IOBs    0 out of 71      0%

   Number of BLOCKRAMs                 2 out of 8      25%




Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)


Phase 1.1
Phase 1.1 (Checksum:9897ab) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.
Phase 5.8 (Checksum:99d5d5) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 0 secs 

Writing design to file blockram.ncd.

Total REAL time to Placer completion: 0 secs 
Total CPU time to Placer completion: 0 secs 


Phase 1: 85 unrouted;       REAL time: 0 secs 

Phase 2: 79 unrouted;       REAL time: 0 secs 

Phase 3: 8 unrouted;       REAL time: 0 secs 

Phase 4: 0 unrouted;       REAL time: 0 secs 

Total REAL time to Router completion: 0 secs 
Total CPU time to Router completion: 1 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|        pClk_BUFGP          |  Global  |    2   |  0.001     |  0.175      |
+----------------------------+----------+--------+------------+-------------+

Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 secs 
Total CPU time to PAR completion: 1 secs 

Peak Memory Usage:  50 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Writing design to file blockram.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Feb 09 11:55:53 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module blockram . . .
PAR command line: par -w -intstyle ise -ol std -t 1 blockram_map.ncd blockram.ncd blockram.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/LbusCont.vhd in Library work.
Architecture behavioral of Entity lbuscont is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Entity <systemfpgatop> (Architecture <rtl>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<8>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:8>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 7                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 162.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 4-bit register for signal <sys_command_reg<7:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 293 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# Adders/Subtractors               : 5
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 197
 1-bit register                    : 177
 32-bit register                   : 7
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.2.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 59.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     500  out of    768    65%  
 Number of Slice Flip Flops:           574  out of   1536    37%  
 Number of 4 input LUTs:               841  out of   1536    54%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 576   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.650ns (Maximum Frequency: 73.260MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
ERROR:NgdBuild:755 - Line 83 in '../constraints/SystemFpga.ucf': Could not find
   net(s) 'pFpgaBusy' in the design.  To suppress this error specify the correct
   net name or remove the constraint.  The 'Ignore I\O constraints on Invalid
   Object Names' property can also be set ( -aul switch for command line users).
ERROR:Parsers:11 - Encountered unrecognized constraint while parsing.
ERROR:NgdBuild:19 - Errors found while parsing constraint file
   "../constraints/SystemFpga.ucf".

Writing NGDBUILD log file "systemfpgatop.bld"...
ERROR: NGDBUILD failed
Process "Translate" did not complete.


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/LbusCont.vhd in Library work.
Architecture behavioral of Entity lbuscont is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<8>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:8>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 7                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 162.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 4-bit register for signal <sys_command_reg<7:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 293 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# Adders/Subtractors               : 5
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 197
 1-bit register                    : 177
 32-bit register                   : 7
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.2.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 59.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     500  out of    768    65%  
 Number of Slice Flip Flops:           574  out of   1536    37%  
 Number of 4 input LUTs:               841  out of   1536    54%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 576   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.650ns (Maximum Frequency: 73.260MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"d:/jgelectronics/ndt/root/rapidaq/fw/systemfpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 43200 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       482 out of  1,536   31%
  Number of 4 input LUTs:           703 out of  1,536   45%
Logic Distribution:
    Number of occupied Slices:                         524 out of    768   68%
    Number of Slices containing only related logic:    524 out of    524  100%
    Number of Slices containing unrelated logic:         0 out of    524    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          775 out of  1,536   50%
      Number used as logic:                       703
      Number used as a route-thru:                 72
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  49,610
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  64 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.2.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  524 out of 768    68%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b8c9) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......................
......
Phase 5.8 (Checksum:af13dc) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 4118 unrouted;       REAL time: 3 secs 

Phase 2: 3689 unrouted;       REAL time: 5 secs 

Phase 3: 1004 unrouted;       REAL time: 5 secs 

Phase 4: 1004 unrouted; (5157)      REAL time: 5 secs 

Phase 5: 1022 unrouted; (2163)      REAL time: 6 secs 

Phase 6: 1022 unrouted; (2163)      REAL time: 6 secs 

Phase 7: 0 unrouted; (2164)      REAL time: 6 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (0)      REAL time: 8 secs 

Phase 9: 0 unrouted; (0)      REAL time: 8 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  407   |  0.471     |  0.637      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.233ns   | 2    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.399ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 5.192ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.313ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 4.954ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.157ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.493ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.299ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 12.383ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 7.459ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.666ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.455ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.701ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.124ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 9.121ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 9 secs 
Total CPU time to PAR completion: 8 secs 

Peak Memory Usage:  66 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Thu Feb 09 11:58:08 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Architecture behavioral of Entity lbuscont is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<8>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:8>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 7                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 162.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 4-bit register for signal <sys_command_reg<7:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 293 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# Adders/Subtractors               : 5
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 197
 1-bit register                    : 177
 32-bit register                   : 7
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.2.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 59.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     500  out of    768    65%  
 Number of Slice Flip Flops:           574  out of   1536    37%  
 Number of 4 input LUTs:               841  out of   1536    54%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 576   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.650ns (Maximum Frequency: 73.260MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 43200 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       482 out of  1,536   31%
  Number of 4 input LUTs:           703 out of  1,536   45%
Logic Distribution:
    Number of occupied Slices:                         524 out of    768   68%
    Number of Slices containing only related logic:    524 out of    524  100%
    Number of Slices containing unrelated logic:         0 out of    524    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          775 out of  1,536   50%
      Number used as logic:                       703
      Number used as a route-thru:                 72
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  49,610
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  64 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.2.
Device speed data version:  PRODUCTION 1.27 2003-12-13.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  524 out of 768    68%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b8c9) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.......................
......
Phase 5.8 (Checksum:af13dc) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 4 secs 
Total CPU time to Placer completion: 3 secs 


Phase 1: 4118 unrouted;       REAL time: 4 secs 

Phase 2: 3689 unrouted;       REAL time: 5 secs 

Phase 3: 1004 unrouted;       REAL time: 6 secs 

Phase 4: 1004 unrouted; (5157)      REAL time: 6 secs 

Phase 5: 1022 unrouted; (2163)      REAL time: 6 secs 

Phase 6: 1022 unrouted; (2163)      REAL time: 6 secs 

Phase 7: 0 unrouted; (2164)      REAL time: 7 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (0)      REAL time: 8 secs 

Phase 9: 0 unrouted; (0)      REAL time: 8 secs 

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 7 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  407   |  0.471     |  0.637      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.233ns   | 2    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.399ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 5.192ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.313ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 4.954ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.157ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.493ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.299ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 12.383ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 7.459ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.666ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.455ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.701ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.124ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 9.121ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 8 secs 

Peak Memory Usage:  66 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Fri Mar 03 17:56:37 2006
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".


Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Entity <BlockRam> (Architecture <syn>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Entity <LbusCont> (Architecture <Behavioral>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Entity <FpgaProg> (Architecture <Rtl>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Entity <EepromCtrl> (Architecture <Rtl>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Entity <SystemFpgaTop> (Architecture <Rtl>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <Rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<8>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:8>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 7                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 162.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 4-bit register for signal <sys_command_reg<7:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   2 Counter(s).
	inferred 293 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# Adders/Subtractors               : 5
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 197
 1-bit register                    : 177
 32-bit register                   : 7
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 59.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 1 time(s)
FlipFlop LbusCont0_IntAddr_4 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     493  out of    768    64%  
 Number of Slice Flip Flops:           574  out of   1536    37%  
 Number of 4 input LUTs:               819  out of   1536    53%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 576   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 12.407ns (Maximum Frequency: 80.600MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       482 out of  1,536   31%
  Number of 4 input LUTs:           687 out of  1,536   44%
Logic Distribution:
    Number of occupied Slices:                         513 out of    768   66%
    Number of Slices containing only related logic:    513 out of    513  100%
    Number of Slices containing unrelated logic:         0 out of    513    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          753 out of  1,536   49%
      Number used as logic:                       687
      Number used as a route-thru:                 66
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  49,457
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  67 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  513 out of 768    66%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b38f) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
..........................
.....
Phase 5.8 (Checksum:b133a6) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4041 unrouted;       REAL time: 3 secs 

Phase 2: 3614 unrouted;       REAL time: 4 secs 

Phase 3: 1014 unrouted;       REAL time: 4 secs 

Phase 4: 1014 unrouted; (5893)      REAL time: 4 secs 

Phase 5: 1019 unrouted; (9093)      REAL time: 5 secs 

Phase 6: 1024 unrouted; (1492)      REAL time: 5 secs 

Phase 7: 0 unrouted; (1492)      REAL time: 6 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (0)      REAL time: 7 secs 

Phase 9: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  403   |  0.486     |  0.652      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.566ns   | 2    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.431ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 5.246ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.578ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 4.985ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.031ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.425ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 8.323ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 12.178ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 7.459ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.932ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.666ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.956ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.504ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 8.672ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 10:51:31 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Entity <lbuscont> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:646 - Signal <sys_enable<8>> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 6                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x9-bit ROM for signal <$n0144>.
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 164.
    Found 32-bit adder for signal <$n0174> created at line 755.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <OorReset>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 5-bit register for signal <sys_command_reg<8:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 32-bit register for signal <sys_oor_count>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 327 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# ROMs                             : 1
 16x9-bit ROM                      : 1
# Adders/Subtractors               : 6
 32-bit adder                      : 1
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 200
 1-bit register                    : 179
 32-bit register                   : 8
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 70.
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_CtrlState_FFd1 has been replicated 1 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     528  out of    768    68%  
 Number of Slice Flip Flops:           600  out of   1536    39%  
 Number of 4 input LUTs:               959  out of   1536    62%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 602   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 16.303ns (Maximum Frequency: 61.338MHz)
   Minimum input arrival time before clock: 13.962ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       508 out of  1,536   33%
  Number of 4 input LUTs:           796 out of  1,536   51%
Logic Distribution:
    Number of occupied Slices:                         572 out of    768   74%
    Number of Slices containing only related logic:    572 out of    572  100%
    Number of Slices containing unrelated logic:         0 out of    572    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          893 out of  1,536   58%
      Number used as logic:                       796
      Number used as a route-thru:                 97
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  50,511
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  572 out of 768    74%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b837) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.....................................
........
Phase 5.8 (Checksum:b30776) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4471 unrouted;       REAL time: 3 secs 

Phase 2: 4023 unrouted;       REAL time: 4 secs 

Phase 3: 1181 unrouted;       REAL time: 5 secs 

Phase 4: 1181 unrouted; (174932)      REAL time: 5 secs 

Phase 5: 1249 unrouted; (131320)      REAL time: 5 secs 

Phase 6: 1263 unrouted; (126096)      REAL time: 5 secs 

Phase 7: 0 unrouted; (129532)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  422   |  0.414     |  0.588      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 129532

WARNING:Par:62 - Timing constraints have not been met.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.056ns   | 5    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.470ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 4.314ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.984ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
* TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 10.293ns   | 5    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 3.821ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
* TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.621ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.252ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 11.101ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
* TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 9.050ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.766ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
* TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 9.119ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.956ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.399ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 7.121ns    | 3    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


4 constraints not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 7 secs 

Peak Memory Usage:  68 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 47 errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 13:19:11 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Entity <lbuscont> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:646 - Signal <sys_enable<8>> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 6                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x9-bit ROM for signal <$n0142>.
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 164.
    Found 32-bit adder for signal <$n0172> created at line 754.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <OorReset>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 5-bit register for signal <sys_command_reg<8:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 32-bit register for signal <sys_oor_count>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <vValidAccess>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 328 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# ROMs                             : 1
 16x9-bit ROM                      : 1
# Adders/Subtractors               : 6
 32-bit adder                      : 1
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 201
 1-bit register                    : 180
 32-bit register                   : 8
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 68.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_CtrlState_FFd1 has been replicated 2 time(s)
FlipFlop LbusCont0_vValidAccess has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     518  out of    768    67%  
 Number of Slice Flip Flops:           610  out of   1536    39%  
 Number of 4 input LUTs:               911  out of   1536    59%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 612   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.507ns (Maximum Frequency: 74.036MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       518 out of  1,536   33%
  Number of 4 input LUTs:           748 out of  1,536   48%
Logic Distribution:
    Number of occupied Slices:                         562 out of    768   73%
    Number of Slices containing only related logic:    562 out of    562  100%
    Number of Slices containing unrelated logic:         0 out of    562    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          845 out of  1,536   55%
      Number used as logic:                       748
      Number used as a route-thru:                 97
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  50,267
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  562 out of 768    73%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b7b5) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
................................
.......
Phase 5.8 (Checksum:b3abbd) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4411 unrouted;       REAL time: 3 secs 

Phase 2: 3950 unrouted;       REAL time: 4 secs 

Phase 3: 1140 unrouted;       REAL time: 4 secs 

Phase 4: 1140 unrouted; (7980)      REAL time: 4 secs 

Phase 5: 1195 unrouted; (15580)      REAL time: 4 secs 

Phase 6: 1211 unrouted; (1822)      REAL time: 5 secs 

Phase 7: 0 unrouted; (1822)      REAL time: 5 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (157)      REAL time: 6 secs 

Phase 9: 0 unrouted; (649)      REAL time: 7 secs 

Phase 10: 0 unrouted; (157)      REAL time: 7 secs 

Writing design to file systemfpgatop.ncd.

Phase 11: 0 unrouted; (157)      REAL time: 8 secs 

Phase 12: 0 unrouted; (157)      REAL time: 9 secs 

Total REAL time to Router completion: 9 secs 
Total CPU time to Router completion: 8 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  435   |  0.475     |  0.649      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 157

WARNING:Par:62 - Timing constraints have not been met.

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.343ns   | 4    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.919ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 4.967ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 4.003ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 5.339ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.062ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.459ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.137ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 11.604ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
* TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 8.157ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.406ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.408ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.723ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.582ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 8.211ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 10 secs 
Total CPU time to PAR completion: 9 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - 1 errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 13:28:55 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Architecture behavioral of Entity lbuscont is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:646 - Signal <sys_enable<8>> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 6                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x9-bit ROM for signal <$n0142>.
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 164.
    Found 32-bit adder for signal <$n0172> created at line 754.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <OorReset>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 5-bit register for signal <sys_command_reg<8:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 32-bit register for signal <sys_oor_count>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <vValidAccess>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 328 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# ROMs                             : 1
 16x9-bit ROM                      : 1
# Adders/Subtractors               : 6
 32-bit adder                      : 1
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 201
 1-bit register                    : 180
 32-bit register                   : 8
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 68.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_CtrlState_FFd1 has been replicated 2 time(s)
FlipFlop LbusCont0_vValidAccess has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     518  out of    768    67%  
 Number of Slice Flip Flops:           610  out of   1536    39%  
 Number of 4 input LUTs:               911  out of   1536    59%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 612   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.507ns (Maximum Frequency: 74.036MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       518 out of  1,536   33%
  Number of 4 input LUTs:           748 out of  1,536   48%
Logic Distribution:
    Number of occupied Slices:                         562 out of    768   73%
    Number of Slices containing only related logic:    562 out of    562  100%
    Number of Slices containing unrelated logic:         0 out of    562    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          845 out of  1,536   55%
      Number used as logic:                       748
      Number used as a route-thru:                 97
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  50,267
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  562 out of 768    73%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b7b5) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
................................
.......
Phase 5.8 (Checksum:b3d471) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4411 unrouted;       REAL time: 2 secs 

Phase 2: 3950 unrouted;       REAL time: 3 secs 

Phase 3: 1204 unrouted;       REAL time: 4 secs 

Phase 4: 1204 unrouted; (15043)      REAL time: 4 secs 

Phase 5: 1209 unrouted; (21842)      REAL time: 4 secs 

Phase 6: 1216 unrouted; (0)      REAL time: 4 secs 

Phase 7: 0 unrouted; (0)      REAL time: 5 secs 

Total REAL time to Router completion: 5 secs 
Total CPU time to Router completion: 5 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  435   |  0.474     |  0.648      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.711ns   | 6    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 7.769ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 4.903ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.539ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 5.760ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 4.062ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.468ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 8.249ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 11.705ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 7.256ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.822ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.707ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.701ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.192ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 7.898ns    | 3    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 6 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 13:34:41 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Entity <lbuscont> (Architecture <behavioral>) compiled.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:646 - Signal <sys_enable<8>> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 6                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x9-bit ROM for signal <$n0142>.
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 164.
    Found 32-bit adder for signal <$n0172> created at line 753.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <OorReset>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 5-bit register for signal <sys_command_reg<8:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 32-bit register for signal <sys_oor_count>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <vValidAccess>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 328 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# ROMs                             : 1
 16x9-bit ROM                      : 1
# Adders/Subtractors               : 6
 32-bit adder                      : 1
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 201
 1-bit register                    : 180
 32-bit register                   : 8
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 68.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_CtrlState_FFd1 has been replicated 2 time(s)
FlipFlop LbusCont0_vValidAccess has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     518  out of    768    67%  
 Number of Slice Flip Flops:           610  out of   1536    39%  
 Number of 4 input LUTs:               912  out of   1536    59%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 612   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.507ns (Maximum Frequency: 74.036MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       518 out of  1,536   33%
  Number of 4 input LUTs:           749 out of  1,536   48%
Logic Distribution:
    Number of occupied Slices:                         564 out of    768   73%
    Number of Slices containing only related logic:    564 out of    564  100%
    Number of Slices containing unrelated logic:         0 out of    564    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          846 out of  1,536   55%
      Number used as logic:                       749
      Number used as a route-thru:                 97
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  50,273
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  564 out of 768    73%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b7cf) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.................................
.....
Phase 5.8 (Checksum:b1f692) REAL time: 2 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 2 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 3 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 3 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4412 unrouted;       REAL time: 3 secs 

Phase 2: 3951 unrouted;       REAL time: 4 secs 

Phase 3: 1112 unrouted;       REAL time: 4 secs 

Phase 4: 1112 unrouted; (17078)      REAL time: 4 secs 

Phase 5: 1136 unrouted; (7065)      REAL time: 5 secs 

Phase 6: 1148 unrouted; (371)      REAL time: 5 secs 

Phase 7: 0 unrouted; (373)      REAL time: 6 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (0)      REAL time: 7 secs 

Phase 9: 0 unrouted; (0)      REAL time: 7 secs 

Total REAL time to Router completion: 7 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  435   |  0.460     |  0.634      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.023ns   | 2    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.125ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 5.211ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.160ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 4.936ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 3.959ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.409ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 7.599ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 11.414ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 6.818ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.784ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.617ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.723ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.782ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 7.721ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 14:08:36 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".



Project Navigator Auto-Make Log File
-------------------------------------




Started process "Synthesize".


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd in Library work.
Architecture syn of Entity blockram is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd in Library work.
Architecture behavioral of Entity lbuscont is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd in Library work.
Architecture rtl of Entity fpgaprog is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd in Library work.
Architecture rtl of Entity eepromctrl is up to date.
Compiling vhdl file D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd in Library work.
Architecture rtl of Entity systemfpgatop is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <systemfpgatop> (Architecture <rtl>).
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 260: Generating a Black Box for component <IBUFG>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK90' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK180' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK270' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLK2X' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'CLKDV' of component 'CLKDLL'.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Unconnected output port 'LOCKED' of component 'CLKDLL'.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 264: Generating a Black Box for component <CLKDLL>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 276: Generating a Black Box for component <BUFG>.
WARNING:Xst:766 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 284: Generating a Black Box for component <IFD>.
WARNING:Xst:753 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd line 317: Unconnected output port 'pTest' of component 'LbusCont'.
Entity <systemfpgatop> analyzed. Unit <systemfpgatop> generated.

Analyzing generic Entity <BlockRam> (Architecture <syn>).
	gAddressWidth = 6
	gDataWidth = 32
Entity <BlockRam> analyzed. Unit <BlockRam> generated.

Analyzing Entity <LbusCont> (Architecture <behavioral>).
INFO:Xst:1304 - Contents of register <sys_command_reg<31>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<30>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<29>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<28>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<27>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<26>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<25>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<24>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<23>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<22>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<21>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<20>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<19>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<18>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<17>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<16>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<15>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<14>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<13>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<12>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<11>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<10>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<9>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<2>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <sys_command_reg<1>> in unit <LbusCont> never changes during circuit operation. The register is replaced by logic.
Entity <LbusCont> analyzed. Unit <LbusCont> generated.

Analyzing Entity <FpgaProg> (Architecture <rtl>).
WARNING:Xst:1639 - D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd line 96: Size of operands are different, smallest operand is adjusted.
INFO:Xst:1304 - Contents of register <pLAout<31>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<30>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<29>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<28>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<27>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<26>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<25>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<24>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<23>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
INFO:Xst:1304 - Contents of register <pLAout<22>> in unit <FpgaProg> never changes during circuit operation. The register is replaced by logic.
Entity <FpgaProg> analyzed. Unit <FpgaProg> generated.

Analyzing Entity <EepromCtrl> (Architecture <rtl>).
Entity <EepromCtrl> analyzed. Unit <EepromCtrl> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <EepromCtrl>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/EepromCtrl.vhd.
    Found finite state machine <FSM_0> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 13                                             |
    | Transitions        | 29                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | pLCLKA (rising_edge)                           |
    | Clock enable       | ClkEN_Fe (positive)                            |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Using one-hot encoding for signal <InstrSel>.
    Found 1-bit register for signal <pEeprom_nS>.
    Found 1-bit register for signal <pBRamWriteEn>.
    Found 1-bit register for signal <pEeprom_C>.
    Found 4-bit adder carry out for signal <$n0172> created at line 340.
    Found 3-bit adder carry out for signal <$n0173> created at line 559.
    Found 6-bit up counter for signal <AddrCount>.
    Found 1-bit register for signal <AddrDone>.
    Found 1-bit register for signal <AddrInc>.
    Found 1-bit register for signal <AddrInc2>.
    Found 1-bit register for signal <AddrLoad>.
    Found 8-bit register for signal <AddrReg>.
    Found 1-bit register for signal <AddrReset>.
    Found 1-bit register for signal <AddrShift>.
    Found 1-bit register for signal <ClkEN_Fe>.
    Found 1-bit register for signal <ClkEN_Re>.
    Found 3-bit up counter for signal <DelayCount>.
    Found 1-bit register for signal <DelayDone>.
    Found 1-bit register for signal <DoDelay>.
    Found 1-bit register for signal <EepromBusy>.
    Found 1-bit register for signal <InstrDone>.
    Found 1-bit register for signal <InstrLoad>.
    Found 8-bit register for signal <InstrReg>.
    Found 4-bit register for signal <InstrSel>.
    Found 1-bit register for signal <InstrShift>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 1-bit register for signal <RxDataDone>.
    Found 1-bit register for signal <RxDataShift>.
    Found 32-bit register for signal <RxDataWord>.
    Found 1-bit register for signal <StallClock>.
    Found 8-bit register for signal <StatusData>.
    Found 3-bit up counter for signal <vBitCount>.
    Found 3-bit register for signal <vBitCount0>.
    Found 4-bit register for signal <vBlockCount>.
    Found 2-bit up counter for signal <vByteCount>.
    Found 6-bit up counter for signal <vCount>.
    Found 3-bit up counter for signal <vShiftCount>.
    Found 3-bit up counter for signal <vShiftCount0>.
    Found 6-bit up counter for signal <vWordCount>.
    Found 1-bit register for signal <WaitWriteDone>.
    Found 3-bit up counter for signal <WrBitCount>.
    Found 2-bit up counter for signal <WrByteCount>.
    Found 1-bit register for signal <WrDataDone>.
    Found 1-bit register for signal <WrDataEn>.
    Found 1-bit register for signal <WrDataLoad>.
    Found 32-bit register for signal <WrDataWord>.
    Found 1-bit register for signal <WriteDone>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 2-bit up counter for signal <WrWordCOunt>.
    Found 8 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  11 Counter(s).
	inferred 114 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   8 Multiplexer(s).
Unit <EepromCtrl> synthesized.


Synthesizing Unit <FpgaProg>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/FpgaProg.vhd.
WARNING:Xst:647 - Input <pBusy> is never used.
    Found finite state machine <FSM_1> for signal <state_var>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | 10000000                                       |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit register for signal <pProgram>.
    Found 20-bit register for signal <pLAout<21:2>>.
    Found 1-bit register for signal <pCClk>.
    Found 1-bit register for signal <pFpgaWrite>.
    Found 1-bit register for signal <pSramOeReq>.
    Found 1-bit register for signal <pTest>.
    Found 9-bit comparator greatequal for signal <$n0034> created at line 96.
    Found 20-bit comparator greater for signal <$n0035> created at line 141.
    Found 9-bit comparator less for signal <$n0036> created at line 96.
    Found 20-bit adder for signal <$n0037> created at line 236.
    Found 9-bit adder for signal <$n0042> created at line 97.
    Found 20-bit register for signal <address_counter>.
    Found 1-bit register for signal <Done>.
    Found 1-bit register for signal <done_toggle>.
    Found 1-bit register for signal <Donei>.
    Found 4-bit register for signal <DSPFpgaCS>.
    Found 1-bit register for signal <FpgaDone>.
    Found 1-bit register for signal <init_toggle>.
    Found 1-bit register for signal <load_toggle>.
    Found 4-bit register for signal <PerFpgaCS>.
    Found 9-bit register for signal <program_counter>.
    Found 1-bit register for signal <program_toggle>.
    Found 1-bit register for signal <vLastLoadToggle>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  73 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
Unit <FpgaProg> synthesized.


Synthesizing Unit <LbusCont>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/LbusCont.vhd.
WARNING:Xst:647 - Input <pnPerFpgaProg<3:1>> is never used.
WARNING:Xst:647 - Input <pnDspFpgaProg<3:1>> is never used.
WARNING:Xst:646 - Signal <sys_command_reg<31:9>> is assigned but never used.
WARNING:Xst:646 - Signal <sys_command_reg<3:1>> is assigned but never used.
WARNING:Xst:646 - Signal <IntAddr<1:0>> is assigned but never used.
WARNING:Xst:646 - Signal <SampleRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <SysRamAccess> is assigned but never used.
WARNING:Xst:646 - Signal <nADS_delayed> is assigned but never used.
WARNING:Xst:1780 - Signal <next_ram_nWR> is never used or assigned.
WARNING:Xst:646 - Signal <sys_enable_any> is assigned but never used.
WARNING:Xst:646 - Signal <sys_enable<8>> is assigned but never used.
WARNING:Xst:1780 - Signal <SysRamWr_a> is never used or assigned.
WARNING:Xst:1780 - Signal <SysRamWr_b> is never used or assigned.
WARNING:Xst:1780 - Signal <next_ram_nCS> is never used or assigned.
WARNING:Xst:1780 - Signal <nExtndReady> is never used or assigned.
WARNING:Xst:1780 - Signal <FirstAccess> is never used or assigned.
    Found finite state machine <FSM_2> for signal <CtrlState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 10                                             |
    | Inputs             | 4                                              |
    | Outputs            | 6                                              |
    | Clock              | pLCLKA (rising_edge)                           |
    | Reset              | pnReset (negative)                             |
    | Reset type         | asynchronous                                   |
    | Reset State        | sidle                                          |
    | Power Up State     | sidle                                          |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16x9-bit ROM for signal <$n0142>.
    Found 1-bit register for signal <pLDoutEn>.
    Found 1-bit register for signal <pFpgaLoad>.
    Found 1-bit register for signal <pTest>.
    Found 30-bit adder for signal <$n0000> created at line 164.
    Found 32-bit adder for signal <$n0172> created at line 753.
    Found 32-bit register for signal <BlkRamData>.
    Found 1-bit register for signal <BlockRamAccess>.
    Found 1-bit register for signal <BlockRamAccessQ>.
    Found 6-bit up counter for signal <BurstAddr>.
    Found 16-bit up counter for signal <BurstCount>.
    Found 1-bit register for signal <BurstInc>.
    Found 1-bit register for signal <BurstReset>.
    Found 1-bit register for signal <BurstWrite>.
    Found 1-bit register for signal <BurstZero>.
    Found 32-bit register for signal <check_register>.
    Found 1-bit register for signal <IncAddress>.
    Found 30-bit register for signal <IntAddr<31:2>>.
    Found 1-bit register for signal <Intlholda>.
    Found 1-bit register for signal <IntLW_R>.
    Found 1-bit register for signal <local_bus_control>.
    Found 1-bit register for signal <nDspFpgaCs>.
    Found 1-bit register for signal <nPerFpgaCs>.
    Found 1-bit register for signal <nReady>.
    Found 1-bit register for signal <nSysRamCS>.
    Found 1-bit register for signal <nSysRamOE>.
    Found 1-bit register for signal <nSysRamWE>.
    Found 1-bit register for signal <OorReset>.
    Found 1-bit register for signal <ReadEeprom>.
    Found 32-bit register for signal <RegReadData>.
    Found 5-bit register for signal <sys_command_reg<8:4>>.
    Found 1-bit register for signal <sys_command_reg<0>>.
    Found 1-bit register for signal <sys_debug_reg<0>>.
    Found 32-bit register for signal <sys_io_bank0>.
    Found 32-bit register for signal <sys_io_bank0_ddr>.
    Found 21-bit register for signal <sys_io_bank1>.
    Found 21-bit register for signal <sys_io_bank1_ddr>.
    Found 32-bit register for signal <sys_oor_count>.
    Found 1-bit register for signal <sys_reg_enable>.
    Found 1-bit register for signal <sys_status_reg<0>>.
    Found 32-bit register for signal <sys_test_reg>.
    Found 1-bit register for signal <vValidAccess>.
    Found 1-bit register for signal <WriteEeprom>.
    Found 101 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred   1 ROM(s).
	inferred   2 Counter(s).
	inferred 328 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred 101 Multiplexer(s).
Unit <LbusCont> synthesized.


Synthesizing Unit <BlockRam>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../../SharedComps/src/BlockRam.vhd.
    Found 64x32-bit single-port block RAM for signal <Ram>.
    -----------------------------------------------------------------------
    | mode               | write-first                         |          |
    | aspect ratio       | 64-word x 32-bit                    |          |
    | clock              | connected to signal <pClk>          | rise     |
    | write enable       | connected to signal <pWriteEn>      | high     |
    | address            | connected to signal <pAddr>         |          |
    | data in            | connected to signal <pDataIn>       |          |
    | data out           | connected to signal <pDataOut>      |          |
    | ram_style          | Auto                                |          |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 RAM(s).
Unit <BlockRam> synthesized.


Synthesizing Unit <systemfpgatop>.
    Related source file is D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/../src/SystemFpgaTop.vhd.
WARNING:Xst:646 - Signal <Debug> is assigned but never used.
    Found 30-bit tristate buffer for signal <pLA>.
    Found 32-bit tristate buffer for signal <pLD>.
    Found 53-bit tristate buffer for signal <pIO>.
    Found 39 1-bit 2-to-1 multiplexers.
    Summary:
	inferred  39 Multiplexer(s).
	inferred 115 Tristate(s).
Unit <systemfpgatop> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Selecting encoding for FSM_2 ...
Optimizing FSM <FSM_2> on signal <CtrlState> with one-hot encoding.
Selecting encoding for FSM_1 ...
Optimizing FSM <FSM_1> on signal <state_var> with one-hot encoding.
Selecting encoding for FSM_0 ...
Optimizing FSM <FSM_0> on signal <CtrlState> with one-hot encoding.
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# FSMs                             : 3
# Block RAMs                       : 1
 64x32-bit single-port block RAM   : 1
# ROMs                             : 1
 16x9-bit ROM                      : 1
# Adders/Subtractors               : 6
 32-bit adder                      : 1
 30-bit adder                      : 1
 9-bit adder                       : 1
 20-bit adder                      : 1
 4-bit adder carry out             : 1
 3-bit adder carry out             : 1
# Counters                         : 13
 16-bit up counter                 : 1
 6-bit up counter                  : 4
 3-bit up counter                  : 5
 2-bit up counter                  : 3
# Registers                        : 201
 1-bit register                    : 180
 32-bit register                   : 8
 21-bit register                   : 2
 20-bit register                   : 1
 9-bit register                    : 1
 4-bit register                    : 5
 3-bit register                    : 1
 8-bit register                    : 3
# Comparators                      : 3
 9-bit comparator less             : 1
 20-bit comparator greater         : 1
 9-bit comparator greatequal       : 1
# Multiplexers                     : 38
 32-bit 2-to-1 multiplexer         : 3
 6-bit 2-to-1 multiplexer          : 2
 1-bit 2-to-1 multiplexer          : 32
 8-bit 2-to-1 multiplexer          : 1
# Tristates                        : 55
 30-bit tristate buffer            : 1
 32-bit tristate buffer            : 1
 1-bit tristate buffer             : 53

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1291 - FF/Latch <pTest> is unconnected in block <LbusCont0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <PerFpgaCS_3> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_1> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <DSPFpgaCS_2> is unconnected in block <FpgaProg0>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <InstrSel>.
WARNING:Xst:1291 - FF/Latch <7> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <6> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <1> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <2> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <3> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <4> is unconnected in block <StatusData>.
WARNING:Xst:1291 - FF/Latch <5> is unconnected in block <StatusData>.
WARNING:Xst:1988 - Unit <FpgaProg>: instances <Mcompar__n0036>, <Mcompar__n0034> of unit <LPM_COMPARE_3> and unit <LPM_COMPARE_1> are dual, second instance is removed
WARNING:Xst:1710 - FF/Latch  <AddrReg_0> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <AddrReg_1> (without init value) is constant in block <EepromCtrl>.
WARNING:Xst:1291 - FF/Latch <InstrSel_3> is unconnected in block <EepromCtrl>.

Optimizing unit <systemfpgatop> ...

Optimizing unit <LbusCont> ...

Optimizing unit <FpgaProg> ...
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1710 - FF/Latch  <DSPFpgaCS_3> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_1> (without init value) is constant in block <FpgaProg>.
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch  <DSPFpgaCS_2> (without init value) is constant in block <FpgaProg>.

Optimizing unit <EepromCtrl> ...
Loading device for application Xst from file 'v50.nph' in environment C:/Xilinx_6.3.

Mapping all equations...
WARNING:Xst:1291 - FF/Latch <LbusCont0_pTest> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <FpgaProg0_PerFpgaCS_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_7> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_6> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_1> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_2> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_3> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_4> is unconnected in block <systemfpgatop>.
WARNING:Xst:1291 - FF/Latch <EepromCtrl0_StatusData_5> is unconnected in block <systemfpgatop>.
Building and optimizing final netlist ...
Register FpgaProg0_Donei equivalent to LbusCont0_sys_status_reg_0 has been removed
Found area constraint ratio of 100 (+ 5) on block systemfpgatop, actual ratio is 68.
FlipFlop LbusCont0_IntAddr_2 has been replicated 2 time(s)
FlipFlop LbusCont0_IntAddr_3 has been replicated 2 time(s)
FlipFlop LbusCont0_CtrlState_FFd1 has been replicated 2 time(s)
FlipFlop LbusCont0_vValidAccess has been replicated 1 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop EepromCtrl0_ClkEN_Fe has been replicated 2 time(s)
FlipFlop LbusCont0_sys_debug_reg_0 has been replicated 1 time(s)
FlipFlop LbusCont0_Intlholda has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s50fg256-5 

 Number of Slices:                     518  out of    768    67%  
 Number of Slice Flip Flops:           610  out of   1536    39%  
 Number of 4 input LUTs:               912  out of   1536    59%  
 Number of bonded IOBs:                151  out of    180    83%  
 Number of BRAMs:                        2  out of      8    25%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT


Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
pLCLKA                             | CLKDLL0:CLK0           | 612   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -5

   Minimum period: 13.507ns (Maximum Frequency: 74.036MHz)
   Minimum input arrival time before clock: 6.756ns
   Maximum output required time after clock: 12.618ns
   Maximum combinational path delay: 7.631ns

=========================================================================
Completed process "Synthesize".



Started process "Translate".


Command Line: ngdbuild -intstyle ise -dd
d:\jgelectronics\ndt\root\rapidaq\fw\systemfpga\xilinx/_ngo -uc
../constraints/SystemFpga.ucf -aul -p xc2s50-fg256-5 systemfpgatop.ngc
systemfpgatop.ngd 

Reading NGO file
"D:/JGElectronics/NDT/root/rapidaq/fw/SystemFpga/xilinx/systemfpgatop.ngc" ...
Reading component libraries for design expansion...

Annotating constraints to design from file "../constraints/SystemFpga.ucf" ...
Attached a PULLUP primitive to pad net pnADS 
Attached a PULLUP primitive to pad net pIRQ<0> 

Checking timing specifications ...
Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Total memory usage is 45224 kilobytes

Writing NGD file "systemfpgatop.ngd" ...

Writing NGDBUILD log file "systemfpgatop.bld"...

NGDBUILD done.
Completed process "Translate".



Started process "Map".

Using target part "2s50fg256-5".
Removing unused or disabled logic...
Running cover...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary:
Number of errors:      0
Number of warnings:   11
Logic Utilization:
  Number of Slice Flip Flops:       518 out of  1,536   33%
  Number of 4 input LUTs:           749 out of  1,536   48%
Logic Distribution:
    Number of occupied Slices:                         564 out of    768   73%
    Number of Slices containing only related logic:    564 out of    564  100%
    Number of Slices containing unrelated logic:         0 out of    564    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          846 out of  1,536   55%
      Number used as logic:                       749
      Number used as a route-thru:                 97
   Number of bonded IOBs:           151 out of    176   85%
      IOB Flip Flops:                              92
   Number of Block RAMs:              2 out of      8   25%
   Number of GCLKs:                   1 out of      4   25%
   Number of GCLKIOBs:                1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

Total equivalent gate count for design:  50,273
Additional JTAG gate count for IOBs:  7,296
Peak Memory Usage:  68 MB

NOTES:

   Related logic is defined as being logic that shares connectivity -
   e.g. two LUTs are "related" if they share common inputs.
   When assembling slices, Map gives priority to combine logic that
   is related.  Doing so results in the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin
   packing unrelated logic into a slice once 99% of the slices are
   occupied through related logic packing.

   Note that once logic distribution reaches the 99% level through
   related logic packing, this does not mean the device is completely
   utilized.  Unrelated logic packing will then begin, continuing until
   all usable LUTs and FFs are occupied.  Depending on your timing
   budget, increased levels of unrelated logic packing may adversely
   affect the overall timing performance of your design.


Mapping completed.
See MAP report file "systemfpgatop_map.mrp" for details.
Completed process "Map".

Mapping Module systemfpgatop . . .
MAP command line:
map -intstyle ise -p xc2s50-fg256-5 -cm area -pr b -k 4 -c 100 -tx off -o systemfpgatop_map.ncd systemfpgatop.ngd systemfpgatop.pcf
Mapping Module systemfpgatop: DONE



Started process "Place & Route".





Constraints file: systemfpgatop.pcf

Loading device database for application Par from file "systemfpgatop_map.ncd".
   "systemfpgatop" is an NCD, version 2.38, device xc2s50, package fg256, speed
-5
Loading device for application Par from file 'v50.nph' in environment
C:/Xilinx_6.3.
Device speed data version:  PRODUCTION 1.27 2004-06-25.


Resolving physical constraints.
Finished resolving physical constraints.

Device utilization summary:

   Number of External GCLKIOBs         1 out of 4      25%
   Number of External IOBs           151 out of 176    85%
      Number of LOCed External IOBs  151 out of 151   100%

   Number of BLOCKRAMs                 2 out of 8      25%
   Number of SLICEs                  564 out of 768    73%

   Number of DLLs                      1 out of 4      25%
   Number of GCLKs                     1 out of 4      25%



Overall effort level (-ol):   Standard (set by user)
Placer effort level (-pl):    Standard (set by user)
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard (set by user)

Starting initial Timing Analysis.  REAL time: 0 secs 
WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
Finished initial Timing Analysis.  REAL time: 0 secs 


Phase 1.1
Phase 1.1 (Checksum:98b7cf) REAL time: 0 secs 

Phase 2.23
Phase 2.23 (Checksum:1312cfe) REAL time: 0 secs 

Phase 3.3
Phase 3.3 (Checksum:1c9c37d) REAL time: 0 secs 

Phase 4.5
Phase 4.5 (Checksum:26259fc) REAL time: 0 secs 

Phase 5.8
.................................
.....
Phase 5.8 (Checksum:b1f692) REAL time: 0 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 0 secs 

Phase 7.18
Phase 7.18 (Checksum:42c1d79) REAL time: 2 secs 

Writing design to file systemfpgatop.ncd.

Total REAL time to Placer completion: 2 secs 
Total CPU time to Placer completion: 2 secs 


Phase 1: 4412 unrouted;       REAL time: 2 secs 

Phase 2: 3951 unrouted;       REAL time: 3 secs 

Phase 3: 1112 unrouted;       REAL time: 3 secs 

Phase 4: 1112 unrouted; (17078)      REAL time: 4 secs 

Phase 5: 1136 unrouted; (7065)      REAL time: 4 secs 

Phase 6: 1148 unrouted; (371)      REAL time: 4 secs 

Phase 7: 0 unrouted; (373)      REAL time: 5 secs 

Writing design to file systemfpgatop.ncd.

Phase 8: 0 unrouted; (0)      REAL time: 6 secs 

Phase 9: 0 unrouted; (0)      REAL time: 6 secs 

Total REAL time to Router completion: 6 secs 
Total CPU time to Router completion: 6 secs 

Generating "par" statistics.

**************************
Generating Clock Report
**************************

+----------------------------+----------+--------+------------+-------------+
|         Clock Net          | Resource | Fanout |Net Skew(ns)|Max Delay(ns)|
+----------------------------+----------+--------+------------+-------------+
|             LCLKA          |  Global  |  435   |  0.460     |  0.634      |
+----------------------------+----------+--------+------------+-------------+

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
  NET "LCLKA" PERIOD =  15 nS   HIGH 50.000 | 15.000ns   | 14.023ns   | 2    
  000 %                                     |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 12.000ns   | 8.125ns    | 1    
  S" TO TIMEGRP "LCLK_RE" 12 nS             |            |            |      
--------------------------------------------------------------------------------
  TS_InToFFsFe = MAXDELAY FROM TIMEGRP "PAD | N/A        | N/A        | N/A  
  S" TO TIMEGRP "LCLK_FE" 5 nS              |            |            |      
--------------------------------------------------------------------------------
  TS_LAToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 6.000ns    | 5.211ns    | 2    
  S(pLA*)" TO TIMEGRP "LCLK_RE" 6 nS        |            |            |      
--------------------------------------------------------------------------------
  TS_EEPROM_QTOFFsRE = MAXDELAY FROM TIMEGR | 12.000ns   | 3.160ns    | 1    
  P "PADS(pEeprom_Q)" TO TIMEGRP  "LCLK_RE" |            |            |      
   12 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_nADSTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pnADS)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_nBLASTTOFFsRE = MAXDELAY FROM TIMEGRP  | 6.000ns    | 4.936ns    | 3    
  "PADS(pnBLAST)" TO TIMEGRP "LCLK_RE" 6  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_LHOLDTOFFsRE = MAXDELAY FROM TIMEGRP " | 6.000ns    | 3.959ns    | 1    
  PADS(pLHOLD)" TO TIMEGRP "LCLK_RE" 6  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_LWnRTOFFsRE = MAXDELAY FROM TIMEGRP "P | 6.000ns    | 1.835ns    | 1    
  ADS(pLWnR)" TO TIMEGRP "LCLK_RE" 6 nS     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamCS = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamCS) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamOe = MAXDELAY FROM TIMEGR | 6.000ns    | 3.368ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamOE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToSysRamWe = MAXDELAY FROM TIMEGR | 6.000ns    | 5.553ns    | 0    
  P "LCLK_RE" TO TIMEGRP  "PADS(pnSysRamWE) |            |            |      
  " 6 nS                                    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLD = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 9.409ns    | 2    
  K_RE" TO TIMEGRP "PADS(pLD*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLA = MAXDELAY FROM TIMEGRP "LCL | 9.500ns    | 7.599ns    | 1    
  K_RE" TO TIMEGRP "PADS(pLA*)" 9.500 nS    |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToEEPROM = MAXDELAY FROM TIMEGRP  | 13.000ns   | 11.414ns   | 2    
  "LCLK_RE" TO TIMEGRP "PADS(pEeprom_*)"  1 |            |            |      
  3 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToLHOLDA = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pLHOLDA)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonREADY = MAXDELAY FROM TIMEGRP  | 5.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pnREADY)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReTonBTERM = MAXDELAY FROM TIMEGRP  | N/A        | N/A        | N/A  
  "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5  n |            |            |      
  S                                         |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToBREQi = MAXDELAY FROM TIMEGRP " | 8.000ns    | 6.818ns    | 1    
  LCLK_RE" TO TIMEGRP "PADS(pBREQi)" 8  nS  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCCLK = MAXDELAY FROM TIMEGR | 9.000ns    | 8.784ns    | 1    
  P "LCLK_RE" TO TIMEGRP  "PADS(pFpgaCClk)" |            |            |      
   9 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaWrite = MAXDELAY FROM TIMEG | 9.000ns    | 8.617ns    | 1    
  RP "LCLK_RE" TO TIMEGRP  "PADS(pFpgaWrite |            |            |      
  )" 9 nS                                   |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToFpgaCS = MAXDELAY FROM TIMEGRP  | 8.000ns    | 3.368ns    | 0    
  "LCLK_RE" TO TIMEGRP "PADS(pFpgaCS*)"  8  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToPFpgaCS = MAXDELAY FROM TIMEGRP | 8.000ns    | 3.368ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pPFpgaCS*)"   |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToProgram = MAXDELAY FROM TIMEGRP | 10.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pProgram*)"   |            |            |      
  10 nS                                     |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToTestLed = MAXDELAY FROM TIMEGRP | 18.000ns   | 5.553ns    | 0    
   "LCLK_RE" TO TIMEGRP "PADS(pTestLed)"  1 |            |            |      
  8 nS                                      |            |            |      
--------------------------------------------------------------------------------
  TS_InToOut = MAXDELAY FROM TIMEGRP "PADS" | 10.000ns   | 9.723ns    | 2    
   TO TIMEGRP "PADS" 10 nS                  |            |            |      
--------------------------------------------------------------------------------
  TS_FFsReToIo = MAXDELAY FROM TIMEGRP "LCL | 15.000ns   | 11.782ns   | 1    
  K_RE" TO TIMEGRP "PADS(pIO*)" 15 nS       |            |            |      
--------------------------------------------------------------------------------
  TS_IoToFFsRe = MAXDELAY FROM TIMEGRP "PAD | 15.000ns   | 7.721ns    | 4    
  S(pIO*)" TO TIMEGRP "LCLK_RE" 15 nS       |            |            |      
--------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
   constraint does not cover any paths or that it has no requested value.
Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 7 secs 
Total CPU time to PAR completion: 6 secs 

Peak Memory Usage:  69 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Writing design to file systemfpgatop.ncd.


PAR done.
Completed process "Place & Route".


Started process "Generate Post-Place & Route Static Timing".

WARNING:Timing:2666 - Constraint ignored: TS_InToFFsFe = MAXDELAY FROM TIMEGRP
   "PADS" TO TIMEGRP "LCLK_FE" 5 nS  ; 
WARNING:Timing:2666 - Constraint ignored: TS_FFsReTonBTERM = MAXDELAY FROM
   TIMEGRP "LCLK_RE" TO TIMEGRP "PADS(pnBTERM)" 5 
   nS ;
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.
WARNING:SpeedCalc:42 - Cannot find referenced model "bel_d_min_period".  This
   generally indicates that there is an inconsistency between versions of the
   speed and device data files.  Please check to ensure that the XILINX
   environment variable is set correctly, if the MYXILINX variable is set, make
   sure that it is pointing to patch files that are compatable with the version
   of software that the XILINX variable points to.

Analysis completed Tue Jul 03 14:34:49 2007
--------------------------------------------------------------------------------

Generating Report ...

Completed process "Generate Post-Place & Route Static Timing".

Place & Route Module systemfpgatop . . .
PAR command line: par -w -intstyle ise -ol std -t 1 systemfpgatop_map.ncd systemfpgatop.ncd systemfpgatop.pcf
PAR completed successfully




Started process "Generate Programming File".

Completed process "Generate Programming File".


