# UCF file for DSPCORE in XC2S200-5FG456

#
# AtoD Connections
#
NET "pADC_DataA<0>" LOC = "B3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<1>" LOC = "A3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<2>" LOC = "B4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<3>" LOC = "A4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<4>" LOC = "B5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<5>" LOC = "A5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<6>" LOC = "C5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<7>" LOC = "D5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<8>" LOC = "B6" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<9>" LOC = "C6" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<10>" LOC = "D6" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataA<11>" LOC = "B7" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<0>" LOC = "G1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<1>" LOC = "G3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<2>" LOC = "F4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<3>" LOC = "F3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<4>" LOC = "F1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<5>" LOC = "F2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<6>" LOC = "E4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<7>" LOC = "E3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<8>" LOC = "E1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<9>" LOC = "E2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<10>" LOC = "D2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_DataB<11>" LOC = "C1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pADC_Clk" LOC = "A11" | IOBDELAY = NONE | SLEW = FAST;
NET "pADC_En"	LOC = L1;
#NET "OR_B"				LOC = B1
#NET "OR_A"				LOC = A7
## dds stuff
NET "pDDS_nWR" LOC = "G4";
#NET "DDSRDB"	LOC = "F5"
NET "pDDS_IO" LOC = "G5" | IOBDELAY = NONE;
NET "pDDSRESET" LOC = "K5";
NET "pDDSA<0>" LOC = "H2";
NET "pDDSA<1>" LOC = "H1";
NET "pDDSA<2>" LOC = "H5";
NET "pDDSA<3>" LOC = "H4";
NET "pDDSA<4>" LOC = "H3";
NET "pDDSA<5>" LOC = "J2";
NET "pDDSD<0>" LOC = "J1";
NET "pDDSD<1>" LOC = "J5";
NET "pDDSD<2>" LOC = "J4";
NET "pDDSD<3>" LOC = "J3";
NET "pDDSD<4>" LOC = "K2";
NET "pDDSD<5>" LOC = "K1";
NET "pDDSD<6>" LOC = "K4";
NET "pDDSD<7>" LOC = "K3";
#NET "pTrigIn"  LOC = "L3" | PULLDOWN | IOBDELAY = NONE;
NET "pSYNC"	LOC = "L4" | PULLDOWN;

#
# SRAM bank A Connections
#
# Address
NET "pSramA_Addr<0>"  LOC = "A9" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<1>"  LOC = "E10" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<2>"  LOC = "C10" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<3>"  LOC = "A10" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<4>"  LOC = "E11" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<5>"  LOC = "D16" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<6>"  LOC = "A16" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<7>"  LOC = "C17" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<8>"  LOC = "A17" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<9>"  LOC = "B18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<10>"  LOC = "A18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<11>"  LOC = "C18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<12>"  LOC = "B17" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<13>"  LOC = "D17" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<14>"  LOC = "C16" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<15>"  LOC = "B10" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<16>"  LOC = "D10" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_Addr<17>"  LOC = "B9" | IOBDELAY = NONE  | SLEW = FAST;
# Data
NET "pSramA_Data<0>"  LOC = "C12" | IOBDELAY = NONE;
NET "pSramA_Data<1>"  LOC = "E13" | IOBDELAY = NONE;
NET "pSramA_Data<2>"  LOC = "C13" | IOBDELAY = NONE;
NET "pSramA_Data<3>"  LOC = "A13" | IOBDELAY = NONE;
NET "pSramA_Data<4>"  LOC = "D14" | IOBDELAY = NONE;
NET "pSramA_Data<5>"  LOC = "B14" | IOBDELAY = NONE;
NET "pSramA_Data<6>"  LOC = "E15" | IOBDELAY = NONE;
NET "pSramA_Data<7>"  LOC = "C15" | IOBDELAY = NONE;
NET "pSramA_Data<8>"  LOC = "B15" | IOBDELAY = NONE;
NET "pSramA_Data<9>"  LOC = "D15" | IOBDELAY = NONE;
NET "pSramA_Data<10>"  LOC = "A14" | IOBDELAY = NONE;
NET "pSramA_Data<11>"  LOC = "C14" | IOBDELAY = NONE;
NET "pSramA_Data<12>"  LOC = "E14" | IOBDELAY = NONE;
NET "pSramA_Data<13>"  LOC = "B13" | IOBDELAY = NONE;
NET "pSramA_Data<14>"  LOC = "D13" | IOBDELAY = NONE;
NET "pSramA_Data<15>"  LOC = "B12" | IOBDELAY = NONE;
NET "pSramA_Data<16>"  LOC = "L18" | IOBDELAY = NONE;
NET "pSramA_Data<17>"  LOC = "M17" | IOBDELAY = NONE;
NET "pSramA_Data<18>"  LOC = "M22" | IOBDELAY = NONE;
NET "pSramA_Data<19>"  LOC = "N21" | IOBDELAY = NONE;
NET "pSramA_Data<20>"  LOC = "P21" | IOBDELAY = NONE;
NET "pSramA_Data<21>"  LOC = "R22" | IOBDELAY = NONE;
NET "pSramA_Data<22>"  LOC = "T21" | IOBDELAY = NONE;
NET "pSramA_Data<23>"  LOC = "U22" | IOBDELAY = NONE;
NET "pSramA_Data<24>"  LOC = "V21" | IOBDELAY = NONE;
NET "pSramA_Data<25>"  LOC = "U20" | IOBDELAY = NONE;
NET "pSramA_Data<26>"  LOC = "T19" | IOBDELAY = NONE;
NET "pSramA_Data<27>"  LOC = "R18" | IOBDELAY = NONE;
NET "pSramA_Data<28>"  LOC = "P19" | IOBDELAY = NONE;
NET "pSramA_Data<29>"  LOC = "N19" | IOBDELAY = NONE;
NET "pSramA_Data<30>"  LOC = "M19" | IOBDELAY = NONE;
NET "pSramA_Data<31>"  LOC = "L21" | IOBDELAY = NONE;
 #Write Strobe
NET "pSramA_nWE"  LOC = "A15" | IOBDELAY = NONE  | SLEW = FAST;
# Read Strobe
NET "pSramA_nRD"  LOC = "F11" | IOBDELAY = NONE  | SLEW = FAST;
# Chip Select
NET "pSramA_nCS<0>"  LOC = "E12" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_nCS<1>"  LOC = "F12" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_nCS<2>"  LOC = "D11" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramA_nCS<3>"  LOC = "D12" | IOBDELAY = NONE  | SLEW = FAST;

#
# SRAM bank B Connections
#
# Address
NET "pSramB_Addr<0>"		LOC = "H18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<1>"		LOC = "H21" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<2>"		LOC = "J19" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<3>"		LOC = "J21" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<4>"		LOC = "K22" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<5>"		LOC = "AA22" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<6>"		LOC = "AB20" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<7>"		LOC = "AB19" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<8>"		LOC = "Y18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<9>"		LOC = "AB18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<10>"		LOC = "AA18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<11>"		LOC = "W18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<12>"		LOC = "AA19" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<13>"		LOC = "AA20" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<14>"		LOC = "W22" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<15>"		LOC = "J18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<16>"		LOC = "H19" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_Addr<17>"		LOC = "G21" | IOBDELAY = NONE  | SLEW = FAST;
# Data
NET "pSramB_Data<0>"		LOC = "B19" | IOBDELAY = NONE;
NET "pSramB_Data<1>"		LOC = "A19" | IOBDELAY = NONE;
NET "pSramB_Data<2>"		LOC = "C22" | IOBDELAY = NONE;
NET "pSramB_Data<3>"		LOC = "D21" | IOBDELAY = NONE;
NET "pSramB_Data<4>"		LOC = "D22" | IOBDELAY = NONE;
NET "pSramB_Data<5>"		LOC = "E20" | IOBDELAY = NONE;
NET "pSramB_Data<6>"		LOC = "E21" | IOBDELAY = NONE;
NET "pSramB_Data<7>"		LOC = "E22" | IOBDELAY = NONE;
NET "pSramB_Data<8>"		LOC = "F18" | IOBDELAY = NONE;
NET "pSramB_Data<9>"		LOC = "F19" | IOBDELAY = NONE;
NET "pSramB_Data<10>"		LOC = "F20" | IOBDELAY = NONE;
NET "pSramB_Data<11>"		LOC = "F21" | IOBDELAY = NONE;
NET "pSramB_Data<12>"		LOC = "F22" | IOBDELAY = NONE;
NET "pSramB_Data<13>"		LOC = "G18" | IOBDELAY = NONE;
NET "pSramB_Data<14>"		LOC = "G19" | IOBDELAY = NONE;
NET "pSramB_Data<15>"		LOC = "G20" | IOBDELAY = NONE;
NET "pSramB_Data<16>"		LOC = "U21" | IOBDELAY = NONE;
NET "pSramB_Data<17>"		LOC = "T20" | IOBDELAY = NONE;
NET "pSramB_Data<18>"		LOC = "R19" | IOBDELAY = NONE;
NET "pSramB_Data<19>"		LOC = "P20" | IOBDELAY = NONE;
NET "pSramB_Data<20>"		LOC = "N20" | IOBDELAY = NONE;
NET "pSramB_Data<21>"		LOC = "M20" | IOBDELAY = NONE;
NET "pSramB_Data<22>"		LOC = "L22" | IOBDELAY = NONE;
NET "pSramB_Data<23>"		LOC = "L17" | IOBDELAY = NONE;
NET "pSramB_Data<24>"		LOC = "L20" | IOBDELAY = NONE;
NET "pSramB_Data<25>"		LOC = "M18" | IOBDELAY = NONE;
NET "pSramB_Data<26>"		LOC = "N18" | IOBDELAY = NONE;
NET "pSramB_Data<27>"		LOC = "P18" | IOBDELAY = NONE;
NET "pSramB_Data<28>"		LOC = "P22" | IOBDELAY = NONE;
NET "pSramB_Data<29>"		LOC = "T18" | IOBDELAY = NONE;
NET "pSramB_Data<30>"		LOC = "U19" | IOBDELAY = NONE;
NET "pSramB_Data<31>"		LOC = "V20" | IOBDELAY = NONE;
# Write Strobe
NET "pSramB_nWE"		LOC = "W21" | IOBDELAY = NONE  | SLEW = FAST;
# Read Strobe
NET "pSramB_nRD"		LOC = "J20" | IOBDELAY = NONE  | SLEW = FAST;
# Chip Select
NET "pSramB_nCS<0>" 		LOC = "J22" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_nCS<1>" 		LOC = "K18" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_nCS<2>" 		LOC = "K19" | IOBDELAY = NONE  | SLEW = FAST;
NET "pSramB_nCS<3>" 		LOC = "K21" | IOBDELAY = NONE  | SLEW = FAST;


#
#NET NOT_FPGAWRITE	LOC = A20;
#NET AANC				LOC = E16;
#NET BANC				LOC = V22;
#NET NOT_FPGAINIT		LOC = V19;

# DAC Signals
NET "pDACSLEEP" LOC = "W5";
NET "pDAC1WRT" LOC = "AB3";
NET "pDAC2WRT" LOC = "AA4";
NET "pDACCLK" LOC = "AB4";

# DAC SRAM Signals
NET "pDACnRD"  LOC = N1 | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACnWR"  LOC = T5 | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<0>" LOC = "M4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<1>" LOC = "M5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<2>" LOC = "M6" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<3>" LOC = "N4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<4>" LOC = "N3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<5>" LOC = "U4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<6>" LOC = "V4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<7>" LOC = "V3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<8>" LOC = "W3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<9>" LOC = "Y2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<10>" LOC = "Y1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<11>" LOC = "W1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<12>" LOC = "W2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<13>" LOC = "V1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<14>" LOC = "V2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<15>" LOC = "N2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<16>" LOC = "M1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACA<17>" LOC = "M3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<0>" LOC = "N5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<1>" LOC = "P4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<2>" LOC = "P3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<3>" LOC = "P5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<4>" LOC = "R5" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<5>" LOC = "R4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<6>" LOC = "T4" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<7>" LOC = "T3" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<8>" LOC = "U1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<9>" LOC = "U2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<10>" LOC = "T1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<11>" LOC = "T2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<12>" LOC = "R1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<13>" LOC = "R2" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<14>" LOC = "P1" | IOBDELAY = NONE  | SLEW = FAST;
NET "pDACD<15>" LOC = "P2" | IOBDELAY = NONE  | SLEW = FAST;

# Connections between DSP FPGA and Peripheral FPGA
NET "pZ0"   LOC = E6;
NET "pZ1"   LOC = D7 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ2"   LOC = C7 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ3"   LOC = E7 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ4"   LOC = E8 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ5"   LOC = D8 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ6"   LOC = C8 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ7"   LOC = E9 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ8"   LOC = D9 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ9"   LOC = C9 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ10"  LOC = B8 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ11"  LOC = A8 | IOBDELAY = NONE  | SLEW = FAST;
NET "pZ12"  LOC = C21 | IOBDELAY = NONE  | SLEW = FAST; # "FPGABUSY" on schematic
##NET "pSampleClk"		LOC = "W12" | IOBDELAY = NONE | SLEW = FAST;
NET "pnLReset"			LOC = AB17;
NET "pnIRQ0"			LOC = AA17;

#NET "SampleCLK" TNM_NET = "SampleCLK"
#TIMESPEC "TS_SampleCLK" = PERIOD "SampleCLK" 20 ns HIGH 50 %
TIMESPEC "TS_P2P" = FROM "PADS" TO "PADS" 20 ns;
#PACE: Start of Constraints generated by PACE
#PACE: Start of PACE I/O Pin Assignments



NET "pnFpgaCs"  LOC = "C19"	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<2>"  LOC = "U11" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<3>"  LOC = "V11" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<4>"  LOC = "W11"  	| IOBDELAY = NONE | SLEW = FAST;
NET "pLA<5>"  LOC = "AB11" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<6>"  LOC = "U12" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<7>"  LOC = "V12" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<8>"  LOC = "Y12" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<9>"  LOC = "AA12" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<10>"  LOC = "V13"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<11>"  LOC = "W13"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<12>"  LOC = "Y13"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<13>"  LOC = "AA13" | IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<14>"  LOC = "AB13" | IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<15>"  LOC = "V14"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<16>"  LOC = "W14"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<17>"  LOC = "Y14"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<18>" LOC = "AA14"	| IOBDELAY = NONE | SLEW = FAST;
NET "pLA<19>" LOC = "AB14"	| IOBDELAY = NONE | SLEW = FAST;
NET "pLA<20>"  LOC = "V15" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<21>"  LOC = "W15" 	| IOBDELAY = NONE | SLEW = FAST ;
NET "pLA<22>"  LOC = "Y15"  | IOBDELAY = NONE | SLEW = FAST;
NET "pLA<23>"  LOC = "AA15" | IOBDELAY = NONE | SLEW = FAST ;
##NET "pLA<24>" LOC = "AB15"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<25>" LOC = "V16"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<26>" LOC = "W16"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<27>" LOC = "Y16"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<28>" LOC = "AB16"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<29>" LOC = "V17"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<30>" LOC = "W17"	| IOBDELAY = NONE | SLEW = FAST;
##NET "pLA<31>" LOC = "Y17"	| IOBDELAY = NONE | SLEW = FAST;
NET "pLCLK"  LOC = "C11"  | IOBDELAY = NONE | SLEW = FAST ;
NET "pLD<0>"  LOC = "D20" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<10>"  LOC = "Y6" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<11>"  LOC = "AA6" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<12>"  LOC = "AB6" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<13>"  LOC = "V7" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<14>"  LOC = "W7" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<15>"  LOC = "Y7" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<16>"  LOC = "AA7" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<17>"  LOC = "V8" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<18>"  LOC = "W8" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<19>"  LOC = "Y8" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<1>"  LOC = "H22" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<20>"  LOC = "AA8" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<21>"  LOC = "AB8" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<22>"  LOC = "V9" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<23>"  LOC = "W9" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<24>"  LOC = "Y9" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<25>"  LOC = "AA9" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<26>"  LOC = "AB9" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<27>"  LOC = "V10" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<28>"  LOC = "W10" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<29>"  LOC = "Y10" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<2>"  LOC = "H20" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<30>"  LOC = "AA10" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<31>"  LOC = "AB10" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<3>"  LOC = "K20" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<4>"  LOC = "N22" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<5>"  LOC = "R21" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<6>"  LOC = "T22" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<7>"  LOC = "Y21" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<8>"  LOC = "AB5" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLD<9>"  LOC = "W6" | IOBDELAY = NONE  | SLEW = FAST ;
NET "pLED0" LOC = "L5";
NET "pLED1" LOC = "L6";
NET "pLWnR"  LOC = "AA5" | IOBDELAY = NONE | SLEW = FAST ;

######## clock constraints ######## 
NET "pADC_Clk" PERIOD = 20 ns HIGH 50 %;
NET "ADC_2xClk" PERIOD = 10 ns HIGH 50 %;
NET "pLCLK" PERIOD = 15 ns HIGH 50 %;
######## clock constraints end ######## 

######## Create time groups for rising and falling edge FFs ########
NET "ADC_2xClk" TNM_NET=ADC_2xClk_BE;
# Timegroup containing all FFs clocked by the rising edge of ADC_2xClk
TIMEGRP ADC_2xClk_RE = RISING ADC_2xClk_BE;
# Timegroup containing all FFs clocked by the falling edge of ADC_2xClk
TIMEGRP ADC_2xClk_FE = FALLING ADC_2xClk_BE;
##
NET "pLCLK" TNM_NET=LCLK_BE;
# Timegroup containing all FFs clocked by the rising edge of pLCLK
TIMEGRP LCLK_RE = RISING LCLK_BE;
# Timegroup containing all FFs clocked by the falling edge of pLCLK
TIMEGRP LCLK_FE = FALLING LCLK_BE;
######## Create time groups for rising and falling edge FFs end ########



######## Input Constraints ########
TIMESPEC TS_SramAReadData=FROM:PADS(pSramA_Data*):TO:LCLK_RE:11;
TIMESPEC TS_SramBReadData=FROM:PADS(pSramB_Data*):TO:LCLK_RE:11;
TIMESPEC TS_LD2ReLCLK=FROM:PADS(pLD*):TO:LCLK_RE:13;
TIMESPEC TS_La2ReLCLK=FROM:PADS(pLA*):TO:LCLK_RE:13;
TIMESPEC TS_FpgaCs2ReLCLK=FROM:PADS(pnFpgaCs):TO:LCLK_RE:13;
TIMESPEC TS_LWnR2ReLCLK=FROM:PADS(pLWnR):TO:LCLK_RE:13;
######## Input Constraints End ########


######## Output Constraints ########

#
# SRAM address bus Output Constraints (from FFs)
#
TIMESPEC TS_Re2xClk2SramAAdd=FROM:ADC_2xClk_RE:TO:PADS(pSramA_Addr*):11;
TIMESPEC TS_Re2xClk2SramBAdd=FROM:ADC_2xClk_RE:TO:PADS(pSramB_Addr*):11;
#
TIMESPEC TS_ReLCLK2SramAAdd=FROM:LCLK_RE:TO:PADS(pSramA_Addr*):11;
TIMESPEC TS_ReLCLK2SramBAdd=FROM:LCLK_RE:TO:PADS(pSramB_Addr*):11;

#
# SRAM data bus Output Constraints (from FFs)
#
TIMESPEC TS_Re2xClk2SramADat=FROM:ADC_2xClk_RE:TO:PADS(pSramA_Data*):11;
TIMESPEC TS_Re2xClk2SramBDat=FROM:ADC_2xClk_RE:TO:PADS(pSramB_Data*):11;

#
# SRAM CS Output Constraints (from FFs)
#
TIMESPEC TS_Re2xClk2SramACs=FROM:ADC_2xClk_RE:TO:PADS(pSramA_nCS*):11;
TIMESPEC TS_Re2xClk2SramBCs=FROM:ADC_2xClk_RE:TO:PADS(pSramB_nCS*):11;
#
TIMESPEC TS_ReLClk2SramACs=FROM:LCLK_RE:TO:PADS(pSramA_nCS*):11;
TIMESPEC TS_ReLClk2SramBCs=FROM:LCLK_RE:TO:PADS(pSramB_nCS*):11;

#
# SRAM OE Output Constraints (from FFs)
#
TIMESPEC TS_ReLClk2SramARD=FROM:LCLK_RE:TO:PADS(pSramA_nRD):11;
TIMESPEC TS_ReLClk2SramBRD=FROM:LCLK_RE:TO:PADS(pSramB_nRD):11;


#
# SRAM WE Output Constraints (from FFs)
#
TIMESPEC TS_Fe2xClk2SramAWe=FROM:ADC_2xClk_FE:TO:PADS(pSramA_nWE):11;
TIMESPEC TS_Fe2xClk2SramBWe=FROM:ADC_2xClk_FE:TO:PADS(pSramB_nWE):11;

#
# LBUS data bus Output Constraints (from FFs)
#
TIMESPEC TS_ReLClk2LBusDat=FROM:LCLK_RE:TO:PADS(pLD*):14;

#
# LBUS data bus Output Constraints from pads
#
TIMESPEC TS_FpgaCs2LD=FROM:PADS(pnFpgaCs):TO:PADS(pLD*):13;
#TIMESPEC TS_pLWnR2LD=FROM:PADS(pLWnR):TO:PADS(pLD*):13;

#
# TCG SRAM Signals
#
TIMESPEC TS_ReLCLK2TcgA=FROM:LCLK_RE:TO:PADS(pDACA*):12;
TIMESPEC TS_ReLCLK2TcgD=FROM:LCLK_RE:TO:PADS(pDACD*):8;
TIMESPEC TS_FeLCLK2TcgWR=FROM:LCLK_FE:TO:PADS(pDACnWR):8;
TIMESPEC TS_ReLCLK2TcgRD=FROM:LCLK_RE:TO:PADS(pDACnRD):8;
TIMESPEC TS_Re2xClk2TcgA=FROM:ADC_2xClk_RE:TO:PADS(pDACA*):12;

#
# DDS Connections
#
TIMESPEC TS_ReLCLK2DDSout=FROM:LCLK_RE:TO:PADS(pDDS*):10;
TIMESPEC TS_DDSin2ReLCLK=FROM:PADS(pDDS_IO):TO:LCLK_RE:8;

#
# Peripheral FPGA interconnections
#
TIMESPEC TS_Z12ReLCLK=FROM:PADS(pZ1):TO:LCLK_RE:5;  # These should use IOB FFs
TIMESPEC TS_Z22ReLCLK=FROM:PADS(pZ2):TO:LCLK_RE:5;
TIMESPEC TS_Z32ReLCLK=FROM:PADS(pZ3):TO:LCLK_RE:5;
TIMESPEC TS_Z42ReLCLK=FROM:PADS(pZ4):TO:LCLK_RE:5;
TIMESPEC TS_Z52ReLCLK=FROM:PADS(pZ5):TO:LCLK_RE:5;
TIMESPEC TS_Z62ReLCLK=FROM:PADS(pZ6):TO:LCLK_RE:5;
TIMESPEC TS_Z72ReLCLK=FROM:PADS(pZ7):TO:LCLK_RE:5;
TIMESPEC TS_Z112ReLCLK=FROM:PADS(pZ11):TO:LCLK_RE:5;

#
# Multi-cycle paths
#
#INST "LBusInterface0_TcgLoadCount_*"   TNM = "MultiCycle1_Paths";
#TIMESPEC TS_MultiPath1=FROM:MultiCycle1_Paths:TO:MultiCycle1_Paths:30;
#
#INST "LBusInterface0_CurveLoadCount_*"   TNM = "MultiCycle2_Paths";
#TIMESPEC TS_MultiPath2=FROM:MultiCycle2_Paths:TO:MultiCycle2_Paths:30;
#

TIMEGRP "MultiCycle5_Paths" = FFS(Gate?_TimeCount<*>);
TIMEGRP "MultiCycle6_Paths" = FFS(Gate?_TimeCount<0>);
TIMEGRP "MultiCycle7_Paths" = "MultiCycle5_Paths" EXCEPT "MultiCycle6_Paths";

TIMEGRP "MultiCycle8_Paths" = FFS("Gate?_TimeDone");
TIMESPEC TS_MultiPath4=FROM:MultiCycle7_Paths:TO:MultiCycle8_Paths:20;

INST "LBusInterface0_SramCtrlSampleCtrlTable_Mram_Ram_inst_ramb_12" INIT_00="0200020002000200020002000200020002000200020002000200020002000200";
INST "LBusInterface0_SramCtrlSampleCtrlTable_Mram_Ram_inst_ramb_12" INIT_01="0200020002000200020002000200020002000200020002000200020002000200";
