---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: DspFpgaPkg.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- VHDL package for DSP FPGA
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

-- Bring in the constant cFpgaVersion to define the FPGA version
library work;
use work.DspFpgaVerPkg.all;


package DspFpgaPkg is

  -- cFpgaRevision should be updated with the current revision number
  constant cFpgaRevision: std_logic_vector(11 downto 0) := X"123";  -- From 1.00 to F.FF

  -----------------------------------------------------------------------------
  --
  -- Nothing beyond this point should need to be changed for a standard build
  --
  -----------------------------------------------------------------------------

  constant cNoOfRegs :  integer := 64; -- (Unused regs will be optimised out)
  constant cDecodeBits: integer := 8;
  constant cRegBase  : std_logic_vector(31 downto 0) := X"00500200";

  -- Register Names and offset (/4) from cRegBase
  constant cCurvedGateData      : integer := 16#00# / 4;
  constant cRawAdcData          : integer := 16#04# / 4;
  constant cTrailingHoldoff     : integer := 16#08# / 4;
  --
  constant cBScansInSram        : integer := 16#4C# / 4;
  constant cRectifierMode       : integer := 16#50# / 4;
  constant cSramCtrlSampleCtrl  : integer := 16#58# / 4;
  constant cDdsCtrl             : integer := 16#5C# / 4;
  constant cTcgConfig           : integer := 16#60# / 4;
  constant cDataSamplingStatus  : integer := 16#64# / 4;
  constant cCScanDataSramBase   : integer := 16#68# / 4;
  constant cSramCtrlNoScans     : integer := 16#6C# / 4;
  constant cTcgLoad             : integer := 16#70# / 4;
  --
  constant cDspFpgaVer          : integer := 16#FC# / 4;

  -- Type to hold array of registers
  type tRegSet is array(0 to cNoOfRegs-1) of std_logic_vector(31 downto 0);

  -- Constant holding initial register values
  -- (Only writable bits have initial values)
  constant cRegSetInitVals: tRegSet := (cCurvedGateData      => X"00000000",
                                        cRawAdcData          => X"00000000",
                                        cTrailingHoldoff     => X"00000000",
                                        --
                                        cBScansInSram        => X"00000000",
                                        cRectifierMode       => X"00000000",
                                        cSramCtrlSampleCtrl  => X"00000200",
                                        cDdsCtrl             => X"00000000",
                                        cTcgConfig           => X"00000000",
                                        cDataSamplingStatus  => X"00000000",
                                        cCScanDataSramBase   => X"00300000",
                                        cSramCtrlNoScans     => X"00000000",
                                        cTcgLoad             => X"00000000",
                                        --
                                        cDspFpgaVer          => (X"0000" & cFpgaVersion & cFpgaRevision),
                                        others               => X"00000000");

  -- Constant holding writable bit positions
  -- A '1' specifies that a bit is writable at a given address
  constant cRegSetWriteMask: tRegSet:= (cCurvedGateData      => X"000007FF",
                                        cRawAdcData          => X"00000000",
                                        cTrailingHoldoff     => X"0000007F",
                                        --
                                        cBScansInSram        => X"00000000",
                                        cRectifierMode       => X"00000007",
                                        cSramCtrlSampleCtrl  => X"000F7FFF",
                                        cDdsCtrl             => X"00007FFF",
                                        cTcgConfig           => X"000000FF",
                                        cDataSamplingStatus  => X"00000000",
                                        cCScanDataSramBase   => X"003FFFFC",
                                        cSramCtrlNoScans     => X"F807FF7F",
                                        cTcgLoad             => X"0000FFFF",
                                        --
                                        cDspFpgaVer          => X"00000000",
                                        others               => X"00000000");

  -- Constant holding readable bit positions
  -- A '1' specifies that a bit is readable at a given address
  constant cRegSetReadMask: tRegSet:= (cCurvedGateData       => X"00000000",
                                       cRawAdcData           => X"00000FFF",
                                       cTrailingHoldoff      => X"0000007F",
                                       --
                                       cBScansInSram         => X"00007FFF",
                                       cRectifierMode        => X"00000007",
                                       cSramCtrlSampleCtrl   => X"000F7FFF",
                                       cDdsCtrl              => X"80007FFF",
                                       cTcgConfig            => X"000000FF",
                                       cDataSamplingStatus   => X"0000011F",
                                       cCScanDataSramBase    => X"003FFFFC",
                                       cSramCtrlNoScans      => X"F807FF7F",
                                       cTcgLoad              => X"00000000",
                                       --
                                       cDspFpgaVer           => X"0000FFFF",
                                       others                => X"00000000");

  type tGateData is array(0 to 7) of std_logic_vector(13 downto 0);

end package DspFpgaPkg;
