---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: SimCtrl001.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card FPGAs
--
-- Design Description:
--Simulation Control file (003) for Digitiser card testbench
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


entity SimCtrl is
  port(ToBusModel   : out tToBusModel;
       FromBusModel : in tFromBusModel;
       ToAdcModel   : out tToAdcModel;
       FromAdcModel : in tFromAdcModel;
       Trigger      : in std_ulogic;
       Ack          : out std_ulogic);
end entity SimCtrl;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00500000#;
  constant cSysCommandReg: integer := 16#00500014#;
  constant cSysStatusReg:  integer := 16#00500014#;

  -- Define the base of the system SRAM
  constant cSysSramBase:   integer := 16#00400000#;

  -- Define the base of the sample SRAM
  constant cSampleSramBase:   integer := 16#00000000#;


begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing PIO"));
    writeline (OUTPUT, vLine);

    -- Test register accesses to Peripheral FPGA
    LBusRead(16#00500400#, vRData, ToBusModel, FromBusModel);
--    LBusRead(16#00500404#, vRData, ToBusModel, FromBusModel);
    LBusWrite(16#00500400#, 16#FFFFFFFF#, ToBusModel, FromBusModel);
    LBusRead(16#00500400#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#7FFCFFFF# then
      write (vLine, string'("Testbench: Error - Expected 0x7FFCFFFF from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
--    LBusRead(16#00500404#, vRData, ToBusModel, FromBusModel);
--    if vRData /= 16#00010000# then
--      write (vLine, string'("Testbench: Error - Expected 0x00010000 from Peripheral FPGA register"));
--      writeline (OUTPUT, vLine);
--      vTestFail := true;
--    end if;

    -- Test Peripheral FPGA gpio
    LBusRead(16#00500448#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Expected 0x00000000 from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500448#, 16#FFFFFFFF#, ToBusModel, FromBusModel);
    LBusRead(16#00500448#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FFFFFFFC# then
      write (vLine, string'("Testbench: Error - Expected 0xFFFFFFFC from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500444#, 16#AAAAAAAA#, ToBusModel, FromBusModel);
    LBusRead(16#00500444#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AAAAAAA8# then
      write (vLine, string'("Testbench: Error - Expected 0xAAAAAAA8 from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500444#, 16#55555555#, ToBusModel, FromBusModel);
    LBusRead(16#00500444#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#55555554# then
      write (vLine, string'("Testbench: Error - Expected 0x55555554 from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00500468#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Expected 0x00000000 from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500468#, 16#FFFFFFFF#, ToBusModel, FromBusModel);
    LBusRead(16#00500468#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#7FFFFFFF# then
      write (vLine, string'("Testbench: Error - Expected 0x7FFFFFFF from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500464#, 16#AAAAAAAA#, ToBusModel, FromBusModel);
    LBusRead(16#00500464#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#2AAAAAAA# then
      write (vLine, string'("Testbench: Error - Expected 0x2AAAAAAA from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    LBusWrite(16#00500464#, 16#55555555#, ToBusModel, FromBusModel);
    LBusRead(16#00500464#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#55555555# then
      write (vLine, string'("Testbench: Error - Expected 0x55555555 from Peripheral FPGA register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;