---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: xilinx-clkdll.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Model of Xilinx CLKDLL component to allow design to simulate
--
-- Note: This a VERY simple model to simulate 2X clock multiplication
-- operation and CLK0 operation.
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity CLKDLL is
  port (CLKIN  : in  std_ulogic;
        CLKFB  : in  std_ulogic;
        RST    : in  std_ulogic;
        CLK0   : out std_ulogic;
        CLK90  : out std_ulogic;
        CLK180 : out std_ulogic;
        CLK270 : out std_ulogic;
        CLK2X  : out std_ulogic;
        CLKDV  : out std_ulogic;
        LOCKED : out std_ulogic);
end entity CLKDLL;


architecture Behave of CLKDLL is

begin

  CLK0 <= CLKIN;

  GenCLK2X: process
    variable vClkPeriod: time;
  begin
    CLK2X <= '0';
    LOCKED <= '0';

    for Delay in 0 to 10 loop
      wait on CLKIN until falling_edge(CLKIN);
      CLK2X <= '0';
      wait on CLKIN until rising_edge(CLKIN);
      CLK2X <= '1';
      vClkPeriod := now;
      wait on CLKIN until falling_edge(CLKIN);
      CLK2X <= '0';
      wait on CLKIN until rising_edge(CLKIN);
      CLK2X <= '1';
      vClkPeriod := now - vClkPeriod;
    end loop;

    LOCKED <= '1';
    while true loop
      CLK2X <= '1';
      wait for vClkPeriod/4;
      CLK2X <= '0';
      wait for vClkPeriod/4;
    end loop;
  end process GenCLK2X;

end Behave;