* Generic IO.
Each bit of IO is programmable as input/output and then can be controlled or
read.


System FPGA
-----------

Add Interrupt support register.



DSP FPGA
--------

* Gating.
Implemented, needs testing.

* TCG DAC Support.
Implemented, needs testing.

* Reverse gate referencing


##########################
Completed:
----------
Misc
----
Add functionality to write Encoder values to Sampling RAM (DSP and Peripheral FPGAs)
## Think about multile elements firing during initial Trigger Delay Time

Peripheral FPGA
---------------

* Rotary encoder inputs (6) 2 bits each.
For each input store current position in signed 32-bit register.
Plus 1 error bit for overrun error.
Requires reset bit from software to define zero position.

* Programable trigger width: 5ns to 20.475us at 100MHz sampling rate.

* Transducer ping-pong support.
Ping-pong table stored in BLOCK-RAM. 0:127 of 0:255 (32768 bits).
No of elements array register - 0 to 127.
Time between element firing register: resolution.

* B-Scan Trigger generation.
Register specifies which input encoder is active.
Register specifies amount encoder changes before a new B-Scan is initiated.

* Encoder Position Logging.
For each B-Scan trigger, log the value of all the encoders (6 x 32-bit words)
in the sample SRAM. Need to pass the data to the DSP FPGA for this.
Does this need to be stored in both A-Scan and C-Scan areas of SRAM.

* Calibration DAC support

* Interleaving support. - Not happening

* Input filter..... - Not happening



System FPGA
-----------

EEPROM access via BLOCK ROM buffer - 256 bytes.
** Done **



DSP FPGA
--------
* Sample Dropping.


