---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: RippleCounter.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card (Shared component)
--
-- Design Description:
-- Module to implement a ripple counter
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity RippleCounter is
  generic(gCountWidth: integer range 2 to 32 := 16);
  port(pReset : in  std_ulogic;
       pInc   : in  std_ulogic;
       pCount : out std_logic_vector(gCountWidth-1 downto 0));
end entity RippleCounter;


architecture rtl of RippleCounter is

  signal Count: std_logic_vector(gCountWidth-1 downto 0);

begin

  -- First stage of counter
  process(pReset, pInc)
  begin
    if pReset = '1' then
      Count(0) <= '0';
    elsif rising_edge(pInc) then
      Count(0) <= not Count(0);
    end if;
  end process;


  -- Remaining stages of counter
  RippleCounter: for LoopCount in 1 to gCountWidth-1 generate
    process(pReset, Count)
    begin
      if pReset = '1' then
        Count(LoopCount) <= '0';
      elsif falling_edge(Count(LoopCount-1)) then
        Count(LoopCount) <= not Count(LoopCount);
      end if;
    end process;
  end generate RippleCounter;

  -- Connect up output
  pCount <= Count;

end rtl;
