-------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: SramSwitching.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Module to switch access between the two banks of SRAM
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity SramSwitching is
  port (pBankAnB_Active : in  std_ulogic;  -- Which bank is active for the datastream storage
        pBankBnA_Active : in  std_ulogic;
        -- Inputs to/from datastream storing logic
        pDStreamAddr    : in  std_logic_vector(17 downto 0);
        pDStreamDataOut : in  std_logic_vector(31 downto 0);
        pDStream_nWE    : in  std_logic_vector(1 downto 0);
        pDStream_nCS    : in  std_logic_vector(3 downto 0);
        -- Inputs to/from local bus
        pLBusSramAddr   : in  std_logic_vector(17 downto 0);
        pLBusSramDataOE : in  std_ulogic;
        pLBusSramDataIn : out std_logic_vector(31 downto 0);
        pLBusSram_nRD   : in  std_ulogic;
        pLBusSram_nCS   : in  std_logic_vector(3 downto 0);
        -- Outputs to/for SRAM bank A
        pSramA_Addr    : out std_logic_vector(17 downto 0);  -- SRAM Bank A Address bus
        pSramA_DataOut : out std_logic_vector(31 downto 0);  -- SRAM Bank A Data bus
        pSramA_DataOE  : out std_ulogic;                     -- SRAM Bank A Data output enable
        pSramA_DataIn  : in  std_logic_vector(31 downto 0);  -- SRAM Bank A Data bus
        pSramA_nWE     : out std_ulogic;                     -- SRAM Bank A Read strobe
        pSramA_nRD     : out std_ulogic;                     -- SRAM Bank A Write strobe
        pSramA_nCS     : out std_logic_vector(3 downto 0);   -- SRAM Bank A chip selects
        -- Outputs to/for SRAM bank B
        pSramB_Addr    : out std_logic_vector(17 downto 0);  -- SRAM Bank B Address bus
        pSramB_DataOut : out std_logic_vector(31 downto 0);  -- SRAM Bank B Data bus
        pSramB_DataOE  : out std_ulogic;                     -- SRAM Bank B Data output enable
        pSramB_DataIn  : in  std_logic_vector(31 downto 0);  -- SRAM Bank B Data bus
        pSramB_nWE     : out std_ulogic;                     -- SRAM Bank B Read strobe
        pSramB_nRD     : out std_ulogic;                     -- SRAM Bank B Write strobe
        pSramB_nCS     : out std_logic_vector(3 downto 0));  -- SRAM Bank B chip selects
end entity SramSwitching;


architecture Rtl of SramSwitching is

begin

  SramSignalMuxA: process(pBankAnB_Active, pDStreamAddr,
                          pSramA_DataIn, pDStream_nWE, pDStream_nCS, pLBusSramAddr,
                          pLBusSramDataOE, pSramB_DataIn,
                          pLBusSram_nRD, pLBusSram_nCS)
  begin
    case pBankAnB_Active is
      when '0' =>
        -- Signals from Datastream to SRAM
        pSramA_Addr     <= pDStreamAddr;
        pSramA_DataOE   <= '1';
        pSramA_nRD      <= '1';
        pSramA_nCS      <= pDStream_nCS;
      when others =>  -- '1'
        -- Signals from Local bus to SRAM
        pSramA_Addr     <= pLBusSramAddr;
        pSramA_DataOE   <= pLBusSramDataOE;
        pSramA_nRD      <= pLBusSram_nRD;
        pSramA_nCS      <= pLBusSram_nCS;
    end case;
  end process SramSignalMuxA;

  -- As only data stream is writing to SRAM assign it all the time
  pSramA_DataOut  <= pDStreamDataOut;
  pSramA_nWE      <= pDStream_nWE(0);

  SramSignalMuxB: process(pBankBnA_Active, pDStreamAddr,
                          pSramA_DataIn, pDStream_nWE, pDStream_nCS, pLBusSramAddr,
                          pLBusSramDataOE, pSramB_DataIn,
                          pLBusSram_nRD, pLBusSram_nCS)
  begin
    case pBankBnA_Active is
      when '0' =>
        -- Signals from Datastream to SRAM
        pSramB_Addr     <= pDStreamAddr;
        pSramB_DataOE   <= '1';
        pLBusSramDataIn <= pSramA_DataIn;
        pSramB_nRD      <= '1';
        pSramB_nCS      <= pDStream_nCS;
      when others =>  -- '1'
        -- Signals from Local bus to SRAM
        pSramB_Addr     <= pLBusSramAddr;
        pSramB_DataOE   <= pLBusSramDataOE;
        pLBusSramDataIn <= pSramB_DataIn;
        pSramB_nRD      <= pLBusSram_nRD;
        pSramB_nCS      <= pLBusSram_nCS;
    end case;
  end process SramSignalMuxB;

  -- As only data stream is writing to SRAM assign it all the time
  pSramB_DataOut  <= pDStreamDataOut;
  pSramB_nWE      <= pDStream_nWE(1);

end Rtl;

