---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: DataInterleave.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Module to combine the two data streams from the ADC
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity DataInterleave is
  port (pnReset         : in  std_ulogic;
        pADC_2xClk      : in  std_ulogic;  -- Frequency doubled version of clock
        pADC_2xClkValid : in  std_ulogic;  -- x2 Clock is valid
        pADC_DataA      : in  std_logic_vector(11 downto 0);  -- Data stream A from AtoD convertor
        pADC_DataB      : in  std_logic_vector(11 downto 0);  -- Data stream B from AtoD convertor
        pADC_DataOut    : out std_logic_vector(11 downto 0)); -- Combined data stream
end entity DataInterleave;


architecture Rtl of DataInterleave is

  -- Signals for latched data streams from ADC
  signal ADC_DataA:        std_logic_vector(11 downto 0);
  signal ADC_DataB:        std_logic_vector(11 downto 0);
  signal InputToggle:      std_ulogic;

  constant cGnd:         std_ulogic := '0';

begin

  -- Process to latch data streams before processing
  LatchDataStreams:  process(pnReset, pADC_2xClk)
  begin
    if pnReset = '0' then
        ADC_DataA <= X"000";
        ADC_DataB <= X"000";
    elsif rising_edge(pADC_2xClk) then
      if InputToggle = '0' then
        ADC_DataA <= pADC_DataA;
        ADC_DataB <= pADC_DataB;
      end if;
    end if;
  end process LatchDataStreams;


  -- Process to combine data streams
  CombineDataStreams: process(pnReset, pADC_2xClk)
  begin
    if pnReset = '0' then
      InputToggle  <= '0';
      pADC_DataOut <= (others => '0');

    elsif rising_edge(pADC_2xClk) then
      if pADC_2xClkValid = '1' then
        if InputToggle = '1' then
          pADC_DataOut <= ADC_DataA;
        else
          pADC_DataOut <= ADC_DataB;
        end if;

        InputToggle <= not InputToggle;
      else
        -- Zero data output stream until pADC_2xClk is valid
        pADC_DataOut <= (others => '0');
      end if;
    end if;
  end process CombineDataStreams;


end Rtl;

