JDF G
// Created by Project Navigator ver 1.0
PROJECT PerFPGA
DESIGN peripheralfpgav1
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 1070462424
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 1097762843
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Modelsim
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\src\PeripheralFpgaPkg.vhd
SOURCE ..\src\LBusInterface.vhd
SOURCE ..\src\TriggerPulseGen.vhd
SOURCE ..\src\BScanCtrl.vhd
SOURCE ..\src\EncoderMonitor.vhd
SOURCE ..\src\PeripheralFpgaTop.vhd
SOURCE ..\src\TriggerDelay.vhd
SOURCE ..\..\SharedComps\src\DualPortRam.vhd
SOURCE ..\CoreGen\Synthesis\delay_value_ram.edn
SOURCE ..\src\DelayValueRam.vhd
SOURCE ..\src\FocusUnitCtrl.vhd
SOURCE ..\src\PeripheralVerPkgV1.vhd
SOURCE ..\..\SharedComps\src\StrobeExtender.vhd
DEPASSOC peripheralfpgatop ..\constraints\PeripheralFpgaV1.ucf
[Normal]
p_ngdbuildUseLOCConstraints=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479117, True
p_xstGenerateRTLNetlist=xstvhd, spartan2, VHDL.t_synthesize, 1082556067, No
p_xstOptimizeInsPrimtives=xstvhd, spartan2, VHDL.t_synthesize, 1086365223, True
p_xstReadCores=xstvhd, spartan2, VHDL.t_synthesize, 1073477820, False
xilxBitgCfg_GenOpt_ASCIIFile=xstvhd, spartan2, Implementation.t_bitFile, 1070463261, True
xilxBitgCfg_GenOpt_BinaryFile=xstvhd, spartan2, Implementation.t_bitFile, 1070463261, True
xilxBitgReadBk_Sec=xstvhd, spartan2, Implementation.t_bitFile, 1074699378, Disable Readback
xilxBitgStart_Clk=xstvhd, spartan2, Implementation.t_bitFile, 1075472481, CCLK
xilxBitgStart_Clk_DriveDone=xstvhd, spartan2, Implementation.t_bitFile, 1070463261, True
xilxBitgStart_IntDone=xstvhd, spartan2, Implementation.t_bitFile, 1083069877, False
xilxMapReportDetail=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073478857, True
xilxNgdbldIOPads=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479410, True
xilxNgdbldMacro=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1088418203, ..\CoreGen\Synthesis
xilxNgdbldPresHierarchy=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479410, True
xilxNgdbldUnexpBlks=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479410, True
xilxNgdbld_AUL=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479410, True
xilxPAReffortLevel=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1073479643, High
xilxPARplacerCostTable=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1097763639, 1
xilxPostTrceRpt=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1085478089, Verbose Report
xilxPostTrceRptLimit=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1085478089, 5
xilxPostTrceRptTiming=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1085478089, 5
xilxSynthAddIObuf=xstvhd, spartan2, VHDL.t_synthesize, 1082556067, True
xilxSynthRegBalancing=xstvhd, spartan2, VHDL.t_synthesize, 1097763791, No
_SynthCaseImplStyle=xstvhd, spartan2, VHDL.t_synthesize, 1086362259, None
_SynthFsmEncode=xstvhd, spartan2, VHDL.t_synthesize, 1086362259, Auto
_SynthOpt=xstvhd, spartan2, VHDL.t_synthesize, 1086365223, Speed
_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1082556067, High
_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1085680863, True
[STRATEGY-LIST]
Normal=True
