#ifndef RQMEMORYSPACEINTERNAL_H
#define RQMEMORYSPACEINTERNAL_H

#ifdef __cplusplus
extern "C" {
#endif

#define RQ_SAMPLE_RAM_OFFSET						0x00000000
#define RQ_SYSTEM_RAM_OFFSET						0x00400000
#define RQ_REGISTERS_START_OFFSET					0x00500000
#define RQ_REGISTERS_END_OFFSET						0x00500444
#define RQ_SYSTEM_FPGA_REGISTERS_START_OFFSET		0x00000000
#define RQ_SYSTEM_FPGA_REGISTERS_END_OFFSET			0x00000100
#define RQ_SAMPLING_FPGA_REGISTERS_START_OFFSET		0x00000200
#define RQ_SAMPLING_FPGA_REGISTERS_END_OFFSET		0x00000300
#define RQ_PERIPHERAL_FPGA_REGISTERS_START_OFFSET	0x00000400
#define RQ_PERIPHERAL_FPGA_REGISTERS_END_OFFSET		0x00000500

#define RQ_EEPROM_START_OFFSET						0x00600000
#define RQ_EE_ZERO_OFFSET							2
#define RQ_EE_GAIN_OFFSET							8
#define RQ_EE_MAGIC_OFFSET							14
#define RQ_EE_SERIAL_OFFSET							15
#define RQ_EE_CFLAG_OFFSET							16
#define RQ_EE_MAGIC_NUMBER_OLD						0x123455aa // used by older InitCard
#define RQ_EE_MAGIC_NUMBER_NEW						0x1234aa55 // new value (calibration flags interpreted differently)
#define RQ_REGISTERS_TOTAL_LENGTH					(RQ_REGISTERS_END_OFFSET - RQ_REGISTERS_START_OFFSET)

// System FPGA registers

#define RQ_CHECK_REGISTER							0x00000000
#define RQ_SYSTEM_IO_BANK_0							0x00000004
#define RQ_SYSTEM_DDR_0								0x00000008
#define RQ_SYSTEM_IO_BANK_1							0x0000000c
#define RQ_SYSTEM_DDR_1								0x00000010
#define RQ_SYSTEM_COMMAND_REGISTER					0x00000014
#define RQ_SYSTEM_STATUS_REGISTER					0x00000014
#define RQ_OUT_OF_RANGE_ACCESS_COUNT_REGISTER		0x00000020
#define RQ_SYSTEM_FPGA_VERSION_NUMBER				0x000000fc

// Sampling FPGA registers

#define RQ_CURVED_GATE_DATA							0x00000000
#define RQ_RAW_ADC_DATA								0x00000004
#define RQ_TRAILING_FLANK_HOLDOFF					0x00000008
#define RQ_BSCANS_IN_SRAM							0x0000004c
#define RQ_RECTIFIER_MODE							0x00000050
#define RQ_SRAM_CONTROL_SAMPLE_CONTROL				0x00000058
#define RQ_DDS_CONTROL								0x0000005c
#define RQ_TCG_CONFIGURE							0x00000060
#define RQ_SAMPLE_DATA_STATUS						0x00000064
#define RQ_CSCAN_DATA_SRAM_BASE						0x00000068
#define RQ_NUMBER_OF_SCANS							0x0000006c
#define RQ_TCG_LOAD									0x00000070
#define RQ_SAMPLING_SEQUENCE_STEP_NUMBER			0x00000074
#define RQ_SAMPLING_SEQUENCE_CONTROL				0x00000078
#define RQ_SAMPLING_FPGA_VERSION_NUMBER				0x000000fc

// Peripheral FPGA registers

#define RQ_PERIPHERAL_HARDWARE_CONTROL				0x00000000
#define RQ_TRIGGER_CONTROL							0x00000004
#define RQ_PULSE_GENERATOR							0x00000008
#define RQ_CALIBRATION_DATA							0x0000000c
#define RQ_ASCAN_CONTROL							0x00000010
#define RQ_SENSOR_ARRAY_SETUP						0x00000014
#define RQ_PINGPONG_SEQUENCE_DATA					0x00000018
#define RQ_BSCAN_TRIGGER_CONTROL					0x0000001c
#define RQ_ENCODER_0_OUTPUT							0x00000020
#define RQ_GATE_START_STOP							0x00000038
#define RQ_GATE_ATTRIBUTES							0x0000003c
#define RQ_GATE_SETUP								0x00000040
#define RQ_PERIPHERAL_IO_BANK_0						0x00000044
#define RQ_PERIPHERAL_DDR_0							0x00000048
#define RQ_FOCUSING_UNIT_CONTROL					0x0000004c
#define RQ_PERIPHERAL_SEQUENCE_STEP_NUMBER			0x0000005c
#define RQ_PERIPHERAL_SEQUENCE_CONTROL				0x00000060
#define RQ_PERIPHERAL_IO_BANK_1						0x00000064
#define RQ_PERIPHERAL_DDR_1							0x00000068
#define RQ_PERIPHERAL_FPGA_VERSION_NUMBER			0x000000fc

#ifdef __cplusplus
}
#endif

#endif