---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: xilinx-ifd.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Model of Xilinx IFD component to allow design to simulate
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity IFD is
  port (D   : in    std_ulogic;
        C   : in    std_ulogic;
        Q   : out   std_ulogic);
end entity IFD;

architecture Behave of IFD is
begin

  ff: process(C)
  begin
    if rising_edge(C) then
      Q <= D;
    end if;
  end process ff;

end Behave;

