JDF G
// Created by Project Navigator ver 1.0
PROJECT SystemFPGA
DESIGN systemfpga
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\src\SystemFpgaTop.vhd
SOURCE ..\src\EepromCtrl.vhd
SOURCE ..\src\FpgaProg.vhd
SOURCE ..\src\LbusCont.vhd
SOURCE ..\..\SharedComps\src\BlockRam.vhd
DEPASSOC systemfpgatop ..\constraints\SystemFpga.ucf
[Normal]
xilxNgdbld_AUL=xstvhd, spartan2, VHDL.t_placeAndRouteDes, 1139486253, True
[STATUS-ALL]
systemfpgatop.ncdFile=WARNINGS,1183469680
systemfpgatop.ngcFile=WARNINGS,1183469666
[STRATEGY-LIST]
Normal=True
