---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: LBusInterface.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Module to interface the local bus with the rest of the system
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

library work;
use work.DspFpgaVerPkg.all;
use work.DspFpgaPkg.all;


entity LBusInterface is
  Port (-- Local bus signals
        pnReset            : in  std_ulogic;
        pLClk              : in  std_ulogic;
        pnFPGACS           : in  std_ulogic;
        pLAin              : in  std_logic_vector(31 downto 2);
        pLDin              : in  std_logic_vector(31 downto 0);
        pLDout             : out std_logic_vector(31 downto 0);
        pLDoutput_enable   : out std_ulogic;
        pLWnR              : in  std_ulogic;
        pnIRQ0             : out std_ulogic;
        -- ClkDll reset signal
        pResetClkDll       : out std_ulogic;
        --SRAM Signals
        pSram_nCS          : out std_logic_vector(3 downto 0);  -- Chip selects for SRAM
        pSram_nRD          : out std_ulogic;  -- Write Enable for SRAM
        pSramData          : in  std_logic_vector(31 downto 0);  -- Data bus from SRAM
        pSramAddr          : out std_logic_vector(17 downto 0); -- Address bus for SRAM
        -- Signals for DDS chip
        pDDS_addr          : out std_logic_vector(5 downto 0);
        pDDS_data          : out std_logic_vector(7 downto 0);
        pDDS_wr            : out std_logic;
        pDDS_reset         : out std_ulogic;
        pDDS_IO            : in  std_ulogic;
        -- Signals for DAC RAM
        pDACA              : out std_logic_vector(17 downto 0);
        pDACD              : out std_logic_vector(15 downto 0);
        pDACnWR            : out std_ulogic;
        pDAC_Sel           : out std_ulogic;
        -- Signals to Curved Gate Dual Port RAM
        pCurveWr           : out std_ulogic;
        pCurveAddr         : out std_logic_vector(11 downto 0);
        pCurveData         : out std_logic_vector(10 downto 0);
        -- Signals from Trigger Generation module
        pBScansInSram      : in  std_logic_vector(14 downto 0);
        pSetDataReady      : in  std_ulogic;
        pSetNewTrigger     : in  std_ulogic;
        pSetEarlyTrigError : in  std_ulogic;
        pSetDataFullError  : in  std_ulogic;
        pSomeDataReady     : in  std_ulogic;
        -- Sample raw ADC signals
        pSampleAdcData     : out std_ulogic;
        pRawAdcData        : in  std_logic_vector(11 downto 0);
        -- Data ready indicator to S/W
        pDataReady         : out std_ulogic;
        -- Early data delivery request
        pEarlyDataReq      : out std_ulogic;
        -- Reset sampling circuitry
        pResetSampling     : out std_ulogic;
        -- Force trigger event
        pForceTrigger      : out std_ulogic;
        -- Readable register contents
        pAdc2xClkValid     : in  std_ulogic;
        pDebug             : in  std_logic_vector(31 downto 0);
        -- Register Outputs
        pRegData           : out tRegSet);
end entity LBusInterface;


architecture Rtl of LBusInterface is


  component StrobeExtender is
    generic(gLfsrBits: integer range 3 to 32 := 3);
    port(pnReset    : in  std_ulogic;
         pClk       : in  std_ulogic;
         pStrobeIn  : in  std_ulogic;
         pStrobeOut : out std_ulogic);
  end component StrobeExtender;


  signal LClkEn:          std_ulogic;

  -- Signals for acessing DDS chip
  signal DdsResetCount:  integer range 0 to 127;
  signal DdsFlag:       std_ulogic;
  signal DdsWrActive:   std_ulogic;
  signal DDS_reset:     std_ulogic;
  signal ResetDds:      std_ulogic;
  signal ForceTrigger:  std_ulogic;

  signal IntAddr:       std_logic_vector(23 downto 0);
  signal LWnR:          std_ulogic;

  -- Signals to create internal registers
  signal nFpgaCs:          std_ulogic;
  signal RegWriteEn:       std_logic_vector(cNoOfRegs-1 downto 0);  -- Write strobes for registers
  signal RegWriteEn2:      std_logic_vector(cNoOfRegs-1 downto 0);
  signal RegBank:          tRegSet;
  signal RegReadData:      tRegSet;
  signal ReadRegData:      std_logic_vector(31 downto 0);
  signal ReadRegMask:      std_logic_vector(31 downto 0);
  signal ReadRegDataMux:   std_logic_vector(31 downto 0);
  signal WriteRegData:     std_logic_vector(31 downto 0);

  signal Sram_nCS: std_logic_vector(3 downto 0);
  signal Sram_nRD: std_ulogic;

  signal SetDataReady:      std_ulogic;
  signal ClearDataReady:    std_ulogic;
  signal DataReady:         std_ulogic;
  signal SetEarlyTrigError: std_logic_vector(2 downto 0);
  signal SetDataFullError:  std_logic_vector(2 downto 0);
  signal NewTrigger:        std_ulogic;
  signal ReadingStatus:     std_ulogic;
  signal SampleStatusRead:  std_ulogic;
  signal SetNewTrigger:     std_logic_vector(1 downto 0);
  signal SampleAdcData:     std_ulogic;

  signal Adc2xClkValid:     std_ulogic;
  signal EarlyTrigError:    std_ulogic;
  signal DataFullError:     std_ulogic;

  -- TCG loading signals
  signal TcgLoad:           std_ulogic;
  signal TcgReset:          std_ulogic;
  signal TcgLoadCount:      std_logic_vector(17 downto 0) := (others => '1');
  signal DACnWR:            std_ulogic := '1';
  signal DACnWRi:           std_ulogic;

  -- Curved Gate loading signals
  signal CurveLoad:         std_ulogic;
  signal CurveReset:        std_ulogic;
  signal CurveLoadCount:    std_logic_vector(11 downto 0);

  signal SomeDataReady:     std_ulogic;
  signal EarlyDataReq:     std_ulogic;

begin


  -- Process to latch value on address bus and increment it as required
  GenIntAddr: process(pnReset, pLCLK)
  begin
    if pnReset = '0' then
      IntAddr  <= (others => '0');
      LClkEn   <= '0';
      LWnR     <= '1';
    elsif rising_edge(pLCLK) then
      if pnFPGACS = '1' then
        -- Load address
        IntAddr(23 downto 2) <= pLAin(23 downto 2);
        LWnR <= pLWnR;
        if pLAin(23 downto 22) = "00" then
          -- Sample RAM access, begin toggle of clock enable
          LClkEn <= '0';
        else
          -- Access to DSP FPGA registers - keep clock enable enabled
          LClkEn <= '1';
        end if;

      else
        if LClkEn = '1' then
          -- Increment address
          IntAddr(23 downto 2) <= unsigned(IntAddr(23 downto 2)) + 1;
        end if;

        if pLAin(23 downto 22) = "00" then
          -- Sample RAM access, toggle clock enable
          LClkEn <= not LClkEn;
        else
          -- Access to DSP FPGA registers - keep clock enable enabled
          LClkEn <= '1';
        end if;
      end if;
    end if;
  end process GenIntAddr;

  IntAddr(1 downto 0) <= "00";


  -- Generate signal containing all read register data
  GenReadRegData: process(RegBank, DdsWrActive, DDS_reset, Adc2xClkValid,
                          DataFullError, EarlyTrigError, NewTrigger,
                          SomeDataReady, DataReady, pBScansInSram, pRawAdcData)
  begin
    -- By default each register actually reads is writeable bits
    for N in 0 to cNoOfRegs-1 loop
      RegReadData(N) <= RegBank(N);
    end loop;

    -- These are the exceptions to this and will override the defaults above
    RegReadData(cRawAdcData)(11 downto 0) <= pRawAdcData;

    RegReadData(cDdsCtrl)(31)  <= (DdsWrActive or DDS_reset);

    RegReadData(cBScansInSram)(14 downto 0) <= pBScansInSram;

    RegReadData(cDataSamplingStatus)(8) <= not Adc2xClkValid;
    RegReadData(cDataSamplingStatus)(4) <= DataFullError;
    RegReadData(cDataSamplingStatus)(3) <= EarlyTrigError;
    RegReadData(cDataSamplingStatus)(2) <= NewTrigger;
    RegReadData(cDataSamplingStatus)(1) <= SomeDataReady;
    RegReadData(cDataSamplingStatus)(0) <= DataReady;

  end process GenReadRegData;


  GenTristateReadDataMux1: for N in 0 to cNoOfRegs-1 generate
    process(IntAddr, RegReadData)
    begin
      for M in 0 to 31 loop
        ReadRegDataMux(M) <= 'Z';
        if conv_integer(unsigned(IntAddr(cDecodeBits-1 downto 2))) = N then
          if cRegSetReadMask(N)(M) = '1' then
            ReadRegDataMux(M) <= RegReadData(N)(M);
          end if;
        end if;
      end loop;
    end process;
  end generate GenTristateReadDataMux1;


  -- Process to register pnFPGACS and pLDin
  GenWriteRegData: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      WriteRegData <= (others => '0');
      nFPGACS      <= '1';
    elsif rising_edge(pLClk) then
      WriteRegData <= pLDin;
      nFPGACS      <= pnFPGACS;
    end if;
  end process GenWriteRegData;


  -- Process to generate register write strobes
  GenRegAccess: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      ReadRegData <= (others => '0');
      ReadRegMask <= (others => '0');
      RegWriteEn  <= (others => '0');
      RegWriteEn2 <= (others => '0');

    elsif rising_edge(pLClk) then
      -- Generate read data for register and SRAM reads
      --if pnFPGACS = '0' then
        if IntAddr(23 downto 22) = "00" then
          -- Read of Sample RAM
          if LClkEn = '0' then
            ReadRegData <= pSramData;
            ReadRegMask <= X"FFFFFFFF";
          end if;
        else
          -- Read of DSP FPGA register
          ReadRegData <= ReadRegDataMux;
          ReadRegMask <= cRegSetReadMask(conv_integer(unsigned(IntAddr(cDecodeBits-1 downto 2))));
        end if;
      --end if;

      -- Generate register write strobes
      RegWriteEn <= (others => '0');
      if LWnR = '1' and pnFPGACS = '0' then
        if IntAddr(23 downto 20) = X"5" and IntAddr(11 downto 8) =X"2" then
          -- Generate the register write strobes
          RegWriteEn(conv_integer(unsigned(IntAddr(7 downto 2)))) <= '1';
        end if;
      end if;

      RegWriteEn2 <= RegWriteEn;
    end if;
  end process GenRegAccess;


  GenpResetSampling: process(pnReset, pLClk)
    variable vResetCount: integer range 0 to 3;
  begin
    if pnReset = '0' then
      pResetSampling <= '0';
      vResetCount    := 0;
    elsif rising_edge(pLClk) then
      if RegWriteEn(cSramCtrlNoScans) = '1' then
        pResetSampling <= '1';
        vResetCount    := 1;
      elsif vResetCount /= 0 then
        vResetCount := (vResetCount + 1) mod 4;
        pResetSampling <= '1';
      else
        pResetSampling <= '0';
      end if;
    end if;
  end process GenpResetSampling;


  -- Drive local bus data output
  pLDout <= ReadRegData and ReadRegMask;  -- This helps with timing problems seen from IntAddr to ReadRegData


  -- Clock 2xADC clock signals (thru 2 d-types) into the LClk clock domain
  ClockIntoLClkDomain: process(pnReset, pLClk)
    variable vSetDataReady:      std_ulogic;
    variable vSetEarlyTrigError: std_logic_vector(2 downto 0);
    variable vSetDataFullError:  std_logic_vector(2 downto 0);
    variable vAdc2xClkValid:     std_ulogic;
    variable vSomeDataReady:     std_ulogic;
  begin
    if pnReset = '0' then
      SetDataReady  <= '0';
      vSetDataReady := '0';

      SetEarlyTrigError  <= "000";
      vSetEarlyTrigError := "000";

      SetDataFullError  <= "000";
      vSetDataFullError := "000";

      Adc2xClkValid      <= '0';
      vAdc2xClkValid     := '0';

      SomeDataReady      <= '0';
      vSomeDataReady     := '0';

    elsif rising_edge(pLClk) then
      if RegWriteEn2(cSramCtrlNoScans) = '1' then
        SetDataReady  <= '0';
        vSetDataReady := '0';

        SetEarlyTrigError <= "000";
        vSetEarlyTrigError := "000";

        SetDataFullError  <= "000";
        vSetDataFullError := "000";
      else
        SetDataReady  <= vSetDataReady;
        vSetDataReady := pSetDataReady;

        if vSetEarlyTrigError(2 downto 1) = "01" then
          SetEarlyTrigError  <= "111";
        else
          SetEarlyTrigError <= SetEarlyTrigError(1 downto 0) & '0';
        end if;
        vSetEarlyTrigError := vSetEarlyTrigError(1 downto 0) & pSetEarlyTrigError;


        if vSetDataFullError(2 downto 1) = "01" then
          SetDataFullError <= "111";
        else
          SetDataFullError <= SetDataFullError(1 downto 0) & '0';
        end if;
        vSetDataFullError := vSetDataFullError(1 downto 0) & pSetDataFullError;
      end if;

      Adc2xClkValid      <= vAdc2xClkValid;
      vAdc2xClkValid     := pAdc2xClkValid;

      SomeDataReady      <= vSomeDataReady;
      vSomeDataReady     := pSomeDataReady;
    end if;
  end process ClockIntoLClkDomain;


  --
  --  Actual register write logic
  --
  process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      -- Initial values for registers
      for RegLoop in 0 to cNoOfRegs-1 loop
        RegBank(RegLoop) <= cRegSetInitVals(RegLoop);
      end loop;

      NewTrigger         <= '0';
      EarlyTrigError     <= '0';
      DataFullError      <= '0';
      ReadingStatus      <= '0';
      SampleStatusRead   <= '0';

      DdsFlag            <= '0';
      ResetDds           <= '1';  -- Always do a DDS reset after powerup
      TcgLoad            <= '0';
      TcgReset           <= '0';
      ForceTrigger       <= '0';
      EarlyDataReq       <= '0';
      ClearDataReady     <= '0';
      DataReady          <= '0';
      SampleAdcData      <= '0';

      CurveLoad          <= '0';
      CurveReset         <= '0';

      SetNewTrigger      <= "00";

    elsif rising_edge(pLClk) then
      DdsFlag          <= '0';
      ResetDds         <= '0';
      TcgLoad          <= '0';
      TcgReset         <= '0';
      CurveLoad        <= '0';
      CurveReset       <= '0';
      ForceTrigger     <= '0';
      EarlyDataReq     <= '0';
      ClearDataReady   <= '0';
      SampleAdcData    <= '0';
      SetNewTrigger    <= SetNewTrigger(0) & pSetNewTrigger;

      if nFpgaCs = '0' then

        if RegWriteEn2(cRawAdcData) = '1' then
          SampleAdcData <= '1';
        end if;

        if RegWriteEn2(cDataSamplingStatus) = '1' and WriteRegData(0) = '1' then
          ClearDataReady  <= '1';
        end if;

        if RegWriteEn2(cDataSamplingStatus) = '1' and WriteRegData(1) = '1' then
          EarlyDataReq <= '1';
        end if;

        if RegWriteEn2(cDdsCtrl) = '1' then
          DdsFlag <= '1';
        end if;

        if RegWriteEn2(cDdsCtrl) = '1' and WriteRegData(14) = '1' then
          ResetDds <= '1';
        end if;

        if RegWriteEn2(cTcgConfig) = '1' and WriteRegData(31) = '1' then
          TcgReset <= '1';
        end if;

        if RegWriteEn2(cTcgLoad) = '1' then
          TcgLoad  <= '1';
        end if;

        if RegWriteEn2(cCurvedGateData) = '1' then
          if WriteRegData(31) = '1' then
            CurveReset <= '1';
          else
            CurveLoad  <= '1';
          end if;
        end if;

        if RegWriteEn2(cSramCtrlSampleCtrl) = '1' and WriteRegData(31) = '1' then
          ForceTrigger <= '1';
        end if;

        for RegLoop in 0 to cNoOfRegs-1 loop
          if RegWriteEn2(RegLoop) = '1' then
            RegBank(RegLoop) <= WriteRegData and cRegSetWriteMask(RegLoop);
          end if;
        end loop;

      end if;

      -- Add register set logic for cDataAvailable register
      if SetDataReady = '1' then
        DataReady <= '1';
      elsif RegWriteEn(cSramCtrlNoScans) = '1' or ClearDataReady = '1' then
        DataReady <= '0';
      end if;

      if SetEarlyTrigError(2) = '1' then
        EarlyTrigError <= '1';
      elsif SampleStatusRead = '1' then
        -- Register is being read, clear the bit
        EarlyTrigError <= '0';
      elsif RegWriteEn(cSramCtrlNoScans) = '1' then
        -- Write to cSramCtrlNoScans, clear the bit
        EarlyTrigError <= '0';
      end if;

      if pSetNewTrigger = '1' or SetNewTrigger(1) = '1' or SetNewTrigger(0) = '1' then
        -- New trigger has been seen, clear the bit
        NewTrigger <= '1';
      elsif SampleStatusRead = '1' then
        -- Register has been read, clear the bit
        NewTrigger <= '0';
      elsif RegWriteEn(cSramCtrlNoScans) = '1' then
        -- Write to cSramCtrlNoScans, clear the bit
        NewTrigger <= '0';
      end if;

      if SetDataFullError(2) = '1' then
        DataFullError <= '1';
      elsif SampleStatusRead = '1' then
        -- Register has been read, clear the bit
        DataFullError <= '0';
      elsif RegWriteEn(cSramCtrlNoScans) = '1' then
        -- Write to cSramCtrlNoScans, clear the bit
        DataFullError <= '0';
      end if;

      ReadingStatus  <= '0';
      if IntAddr(23 downto 20) = X"5" and conv_integer(unsigned(IntAddr(cDecodeBits-1 downto 2))) = cDataSamplingStatus
         and pnFpgaCS = '0' then
        ReadingStatus  <= '1';
      end if;


      SampleStatusRead <= '0';
      if ReadingStatus = '1' and pnFpgaCs = '0' and LWnR = '0' then
        SampleStatusRead <= '1';
      end if;


    end if;
  end process;

  pDataReady <= DataReady;


  GenDacSramSignals: process(pLClk)
  begin
    if rising_edge(pLClk) then
      DACnWR       <= '1';

      if TcgReset = '1' then
        TcgLoadCount <= (others => '1');
      elsif TcgLoad = '1' then
        TcgLoadCount <= (unsigned(TcgLoadCount) + 1);
      end if;

      if TcgLoad = '1' then
        DACnWR  <= '0';
      end if;

    end if;
  end process GenDacSramSignals;


  DelayDACSignals: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      pDACD    <= (others => '0');
      pDACA    <= (others => '0');
      DACnWRi  <= '1';
    elsif rising_edge(pLClk) then
      pDACD    <= RegBank(cTcgLoad)(15 downto 0);
      pDACA    <= TcgLoadCount;
      DACnWRi  <= DACnWR;
    end if;
  end process DelayDACSignals;

  pDAC_Sel <= not RegBank(cTcgConfig)(1);


  -- Generate -ve edge clocked DACnWR signal
  GenpDACnWR: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      pDACnWR <= '1';
    elsif falling_edge(pLClk) then
      pDACnWR <= DACnWRi;
    end if;
  end process GenpDACnWR;


  GenCurveLoadSignals: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      CurveLoadCount <= (others => '1');
      pCurveWr        <= '0';
    elsif rising_edge(pLClk) then
      pCurveWr <= '0';

      if CurveReset = '1' then
        CurveLoadCount <= (others => '1');
      elsif CurveLoad = '1' then
        CurveLoadCount <= (unsigned(CurveLoadCount) + 1) and X"FFF";
      end if;

      if CurveLoad = '1' then
        pCurveWr <= '1';
      end if;

    end if;
  end process GenCurveLoadSignals;

  pCurveData <= RegBank(cCurvedGateData)(10 downto 0);
  pCurveAddr <= CurveLoadCount;


  -- Lengthen ForceTrigger strobe to produce the pForceTrigger output.
  StrobeExtender0: StrobeExtender
    generic map(gLfsrBits => 3)
    port map(pnReset    => pnReset,
             pClk       => pLClk,
             pStrobeIn  => ForceTrigger,
             pStrobeOut => pForceTrigger);

  -- Lengthen EarlyDataReq strobe to produce pEarlyDataReq output
  StrobeExtender1: StrobeExtender
    generic map(gLfsrBits => 3)
    port map(pnReset    => pnReset,
             pClk       => pLClk,
             pStrobeIn  => EarlyDataReq,
             pStrobeOut => pEarlyDataReq);

  -- Lengthen SampleAdcData strobe to produce pSampleAdcData output
  StrobeExtender2: StrobeExtender
    generic map(gLfsrBits => 3)
    port map(pnReset    => pnReset,
             pClk       => pLClk,
             pStrobeIn  => SampleAdcData,
             pStrobeOut => pSampleAdcData);


  -- Connect register bank to module outputs
  pRegData <= RegBank;

  pLDoutput_enable <= '1' when (pnFpgaCS = '0' and LWnR = '0') else '0';

  GenIrq: process(pnReset, pLCLK)
  begin
    if pnReset = '0' then
      pnIRQ0 <= '1';
    elsif rising_edge(pLCLK) then
      pnIRQ0 <= '1';
      if RegBank(cSramCtrlNoScans)(28) = '1' and DataReady = '1' then
        pnIRQ0 <= '0';
      end if;
      if RegBank(cSramCtrlNoScans)(29) = '1' and SomeDataReady = '1' then
        pnIRQ0 <= '0';
      end if;
    end if;
  end process GenIrq;


  --
  -- Generate SRAM signals
  --
  GenSram_nCS: process(IntAddr, pnFPGACS)
  begin
    Sram_nCS <= "1111";
    Sram_nRD <= '1';

    if pnFPGACS = '0' then
      case IntAddr(23 downto 20) is
        when X"0" =>   Sram_nCS <= "1110";
                       Sram_nRD <= '0';

        when X"1" =>   Sram_nCS <= "1101";
                       Sram_nRD <= '0';

        when X"2" =>   Sram_nCS <= "1011";
                       Sram_nRD <= '0';

        when X"3" =>   Sram_nCS <= "0111";
                       Sram_nRD <= '0';

        when others => Sram_nCS <= "1111";
                       Sram_nRD <= '1';
      end case;
    end if;
  end process GenSram_nCS;


  -- Clock all SRAM signals out
  GenSramSignals: process(pnReset, pLClk)
  begin
    if pnReset = '0' then
      pSram_nCS <= "1111";
      pSram_nRD <= '1';
      pSramAddr <= (others => '0');
    elsif rising_edge(pLClk) then
      if LClkEn = '0' then
        pSram_nCS <= Sram_nCS;
        pSram_nRD <= Sram_nRD;
        pSramAddr <= IntAddr(19 downto 2);
      end if;
    end if;
  end process GenSramSignals;


  --
  --  generate DDS data / address bus and write pulse
  --
  process(pnReset, pLClk)
    variable vLastDDS_IO: std_logic_vector(1 downto 0);
  begin
    if pnReset = '0' then
      vLastDDS_IO  := "00";
      DdsWrActive  <= '0';
      pDDS_wr      <= '1';
      pDDS_data    <= (others => '0');
      pDDS_addr    <= (others => '0');

    elsif rising_edge(pLClk) then
      pDDS_data <= RegBank(cDdsCtrl)(7 downto 0);    -- DDS data bus
      pDDS_addr <= RegBank(cDdsCtrl)(13 downto 8);   -- DDS address bus

      pDDS_wr <= '1';
      if DdsWrActive = '1' and vLastDDS_IO(0) = '0' and vLastDDS_IO(1) = '1' then
        -- Falling edge of DDS_IO while DdsWrActive is asserted
        pDDS_wr     <= '0';  -- Do the write
        DdsWrActive <= '0';  -- Cancel the active strobe
      end if;

      if DdsFlag = '1' and RegBank(cDdsCtrl)(14) = '0' then
        DdsWrActive <= '1';
      end if;

      vLastDDS_IO := vLastDDS_IO(0) & pDDS_IO;

    end if;
  end process;


  -- Extend DDS reset pulse
  StrobeExtender3: StrobeExtender
    generic map(gLfsrBits => 7)
    port map(pnReset    => pnReset,
             pClk       => pLClk,
             pStrobeIn  => ResetDds,
             pStrobeOut => DDS_reset);

  pDDS_reset <= DDS_reset;


  -- Generate a reset pulse for the ClkDll (frequency doubler)
  StrobeExtender4: StrobeExtender
    generic map(gLfsrBits => 8)
    port map(pnReset    => pnReset,
             pClk       => pLClk,
             pStrobeIn  => DdsFlag,
             pStrobeOut => pResetClkDll);


end Rtl;

