-- Xilinx Vhdl netlist produced by netgen application (version G.30)
-- Command       : -intstyle ise -s 5 -pcf peripheralfpgatop.pcf -ngm peripheralfpgatop.ngm -rpw 100 -tpw 0 -ar Structure -xon true -w -ofmt vhdl -sim peripheralfpgatop.ncd peripheralfpgatop_timesim.vhd 
-- Input file    : peripheralfpgatop.ncd
-- Output file   : peripheralfpgatop_timesim.vhd
-- Design name   : peripheralfpgatop
-- # of Entities : 2
-- Xilinx        : C:/Xilinx
-- Device        : 2s50fg256-5 (PRODUCTION 1.27 2003-12-13)

-- This vhdl netlist is a simulation model and uses simulation 
-- primitives which may not represent the true implementation of the 
-- device, however the netlist is functionally correct and should not 
-- be modified. This file cannot be synthesized and should only be used 
-- with supported simulation tools.

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity delay_value_ram is
  port (
    web : in STD_LOGIC := 'X'; 
    clka : in STD_LOGIC := 'X'; 
    clkb : in STD_LOGIC := 'X'; 
    addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); 
    addrb : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
    dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
    douta : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
  );
end delay_value_ram;

architecture Structure of delay_value_ram is
  signal GSR : STD_LOGIC;
  signal N0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DOA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_DIA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_ADDRB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_ADDRB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_ADDRB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_ADDRA0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B13_LOGIC_ONE : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DOA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_DIA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_ADDRB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_ADDRB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_ADDRB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_ADDRA0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B17_LOGIC_ONE : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DOA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_DIA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_ADDRB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_ADDRB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_ADDRB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_ADDRA0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B5_LOGIC_ONE : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DOA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIB8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA15 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA14 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA13 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA12 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA11 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA10 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA9 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA8 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA7 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA6 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA5 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA4 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA3 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_DIA2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_ADDRB2 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_ADDRB1 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_ADDRB0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_ADDRA0 : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO : STD_LOGIC; 
  signal DelayValueRam0_delay_value_ram0_B9_LOGIC_ONE : STD_LOGIC; 
begin
  DelayValueRam0_delay_value_ram0_B13_LOGIC_ONE_0 : X_ONE
    port map (
      O => DelayValueRam0_delay_value_ram0_B13_LOGIC_ONE
    );
  DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO_1 : X_ZERO
    port map (
      O => DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO
    );
  B13 : X_RAMB4_S2_S8
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SETUP_ALL => 3737 ps
    )
    port map (
      CLKA => clka,
      CLKB => clkb,
      ENA => DelayValueRam0_delay_value_ram0_B13_LOGIC_ONE,
      ENB => DelayValueRam0_delay_value_ram0_B13_LOGIC_ONE,
      RSTA => DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO,
      RSTB => DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO,
      WEA => DelayValueRam0_delay_value_ram0_B13_LOGIC_ZERO,
      WEB => web,
      GSR => GSR,
      ADDRA(10) => addra(10),
      ADDRA(9) => addra(9),
      ADDRA(8) => addra(8),
      ADDRA(7) => addra(7),
      ADDRA(6) => addra(6),
      ADDRA(5) => addra(5),
      ADDRA(4) => addra(4),
      ADDRA(3) => addra(3),
      ADDRA(2) => addra(2),
      ADDRA(1) => addra(1),
      ADDRA(0) => addra(0),
      ADDRB(8) => addrb(8),
      ADDRB(7) => addrb(7),
      ADDRB(6) => addrb(6),
      ADDRB(5) => addrb(5),
      ADDRB(4) => addrb(4),
      ADDRB(3) => addrb(3),
      ADDRB(2) => addrb(2),
      ADDRB(1) => addrb(1),
      ADDRB(0) => addrb(0),
      DIA(1) => N0,
      DIA(0) => N0,
      DIB(7) => dinb(29),
      DIB(6) => dinb(28),
      DIB(5) => dinb(21),
      DIB(4) => dinb(20),
      DIB(3) => dinb(13),
      DIB(2) => dinb(12),
      DIB(1) => dinb(5),
      DIB(0) => dinb(4),
      DOA(1) => douta(5),
      DOA(0) => douta(4),
      DOB(7) => DelayValueRam0_delay_value_ram0_B13_DOB7,
      DOB(6) => DelayValueRam0_delay_value_ram0_B13_DOB6,
      DOB(5) => DelayValueRam0_delay_value_ram0_B13_DOB5,
      DOB(4) => DelayValueRam0_delay_value_ram0_B13_DOB4,
      DOB(3) => DelayValueRam0_delay_value_ram0_B13_DOB3,
      DOB(2) => DelayValueRam0_delay_value_ram0_B13_DOB2,
      DOB(1) => DelayValueRam0_delay_value_ram0_B13_DOB1,
      DOB(0) => DelayValueRam0_delay_value_ram0_B13_DOB0
    );
  DelayValueRam0_delay_value_ram0_B17_LOGIC_ONE_2 : X_ONE
    port map (
      O => DelayValueRam0_delay_value_ram0_B17_LOGIC_ONE
    );
  DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO_3 : X_ZERO
    port map (
      O => DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO
    );
  B17 : X_RAMB4_S2_S8
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SETUP_ALL => 3737 ps
    )
    port map (
      CLKA => clka,
      CLKB => clkb,
      ENA => DelayValueRam0_delay_value_ram0_B17_LOGIC_ONE,
      ENB => DelayValueRam0_delay_value_ram0_B17_LOGIC_ONE,
      RSTA => DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO,
      RSTB => DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO,
      WEA => DelayValueRam0_delay_value_ram0_B17_LOGIC_ZERO,
      WEB => web,
      GSR => GSR,
      ADDRA(10) => addra(10),
      ADDRA(9) => addra(9),
      ADDRA(8) => addra(8),
      ADDRA(7) => addra(7),
      ADDRA(6) => addra(6),
      ADDRA(5) => addra(5),
      ADDRA(4) => addra(4),
      ADDRA(3) => addra(3),
      ADDRA(2) => addra(2),
      ADDRA(1) => addra(1),
      ADDRA(0) => addra(0),
      ADDRB(8) => addrb(8),
      ADDRB(7) => addrb(7),
      ADDRB(6) => addrb(6),
      ADDRB(5) => addrb(5),
      ADDRB(4) => addrb(4),
      ADDRB(3) => addrb(3),
      ADDRB(2) => addrb(2),
      ADDRB(1) => addrb(1),
      ADDRB(0) => addrb(0),
      DIA(1) => N0,
      DIA(0) => N0,
      DIB(7) => dinb(31),
      DIB(6) => dinb(30),
      DIB(5) => dinb(23),
      DIB(4) => dinb(22),
      DIB(3) => dinb(15),
      DIB(2) => dinb(14),
      DIB(1) => dinb(7),
      DIB(0) => dinb(6),
      DOA(1) => douta(7),
      DOA(0) => douta(6),
      DOB(7) => DelayValueRam0_delay_value_ram0_B17_DOB7,
      DOB(6) => DelayValueRam0_delay_value_ram0_B17_DOB6,
      DOB(5) => DelayValueRam0_delay_value_ram0_B17_DOB5,
      DOB(4) => DelayValueRam0_delay_value_ram0_B17_DOB4,
      DOB(3) => DelayValueRam0_delay_value_ram0_B17_DOB3,
      DOB(2) => DelayValueRam0_delay_value_ram0_B17_DOB2,
      DOB(1) => DelayValueRam0_delay_value_ram0_B17_DOB1,
      DOB(0) => DelayValueRam0_delay_value_ram0_B17_DOB0
    );
  DelayValueRam0_delay_value_ram0_B5_LOGIC_ONE_4 : X_ONE
    port map (
      O => DelayValueRam0_delay_value_ram0_B5_LOGIC_ONE
    );
  DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO_5 : X_ZERO
    port map (
      O => DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO
    );
  B5 : X_RAMB4_S2_S8
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SETUP_ALL => 3737 ps
    )
    port map (
      CLKA => clka,
      CLKB => clkb,
      ENA => DelayValueRam0_delay_value_ram0_B5_LOGIC_ONE,
      ENB => DelayValueRam0_delay_value_ram0_B5_LOGIC_ONE,
      RSTA => DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO,
      RSTB => DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO,
      WEA => DelayValueRam0_delay_value_ram0_B5_LOGIC_ZERO,
      WEB => web,
      GSR => GSR,
      ADDRA(10) => addra(10),
      ADDRA(9) => addra(9),
      ADDRA(8) => addra(8),
      ADDRA(7) => addra(7),
      ADDRA(6) => addra(6),
      ADDRA(5) => addra(5),
      ADDRA(4) => addra(4),
      ADDRA(3) => addra(3),
      ADDRA(2) => addra(2),
      ADDRA(1) => addra(1),
      ADDRA(0) => addra(0),
      ADDRB(8) => addrb(8),
      ADDRB(7) => addrb(7),
      ADDRB(6) => addrb(6),
      ADDRB(5) => addrb(5),
      ADDRB(4) => addrb(4),
      ADDRB(3) => addrb(3),
      ADDRB(2) => addrb(2),
      ADDRB(1) => addrb(1),
      ADDRB(0) => addrb(0),
      DIA(1) => N0,
      DIA(0) => N0,
      DIB(7) => dinb(25),
      DIB(6) => dinb(24),
      DIB(5) => dinb(17),
      DIB(4) => dinb(16),
      DIB(3) => dinb(9),
      DIB(2) => dinb(8),
      DIB(1) => dinb(1),
      DIB(0) => dinb(0),
      DOA(1) => douta(1),
      DOA(0) => douta(0),
      DOB(7) => DelayValueRam0_delay_value_ram0_B5_DOB7,
      DOB(6) => DelayValueRam0_delay_value_ram0_B5_DOB6,
      DOB(5) => DelayValueRam0_delay_value_ram0_B5_DOB5,
      DOB(4) => DelayValueRam0_delay_value_ram0_B5_DOB4,
      DOB(3) => DelayValueRam0_delay_value_ram0_B5_DOB3,
      DOB(2) => DelayValueRam0_delay_value_ram0_B5_DOB2,
      DOB(1) => DelayValueRam0_delay_value_ram0_B5_DOB1,
      DOB(0) => DelayValueRam0_delay_value_ram0_B5_DOB0
    );
  DelayValueRam0_delay_value_ram0_B9_LOGIC_ONE_6 : X_ONE
    port map (
      O => DelayValueRam0_delay_value_ram0_B9_LOGIC_ONE
    );
  DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO_7 : X_ZERO
    port map (
      O => DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO
    );
  B9 : X_RAMB4_S2_S8
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SETUP_ALL => 3737 ps
    )
    port map (
      CLKA => clka,
      CLKB => clkb,
      ENA => DelayValueRam0_delay_value_ram0_B9_LOGIC_ONE,
      ENB => DelayValueRam0_delay_value_ram0_B9_LOGIC_ONE,
      RSTA => DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO,
      RSTB => DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO,
      WEA => DelayValueRam0_delay_value_ram0_B9_LOGIC_ZERO,
      WEB => web,
      GSR => GSR,
      ADDRA(10) => addra(10),
      ADDRA(9) => addra(9),
      ADDRA(8) => addra(8),
      ADDRA(7) => addra(7),
      ADDRA(6) => addra(6),
      ADDRA(5) => addra(5),
      ADDRA(4) => addra(4),
      ADDRA(3) => addra(3),
      ADDRA(2) => addra(2),
      ADDRA(1) => addra(1),
      ADDRA(0) => addra(0),
      ADDRB(8) => addrb(8),
      ADDRB(7) => addrb(7),
      ADDRB(6) => addrb(6),
      ADDRB(5) => addrb(5),
      ADDRB(4) => addrb(4),
      ADDRB(3) => addrb(3),
      ADDRB(2) => addrb(2),
      ADDRB(1) => addrb(1),
      ADDRB(0) => addrb(0),
      DIA(1) => N0,
      DIA(0) => N0,
      DIB(7) => dinb(27),
      DIB(6) => dinb(26),
      DIB(5) => dinb(19),
      DIB(4) => dinb(18),
      DIB(3) => dinb(11),
      DIB(2) => dinb(10),
      DIB(1) => dinb(3),
      DIB(0) => dinb(2),
      DOA(1) => douta(3),
      DOA(0) => douta(2),
      DOB(7) => DelayValueRam0_delay_value_ram0_B9_DOB7,
      DOB(6) => DelayValueRam0_delay_value_ram0_B9_DOB6,
      DOB(5) => DelayValueRam0_delay_value_ram0_B9_DOB5,
      DOB(4) => DelayValueRam0_delay_value_ram0_B9_DOB4,
      DOB(3) => DelayValueRam0_delay_value_ram0_B9_DOB3,
      DOB(2) => DelayValueRam0_delay_value_ram0_B9_DOB2,
      DOB(1) => DelayValueRam0_delay_value_ram0_B9_DOB1,
      DOB(0) => DelayValueRam0_delay_value_ram0_B9_DOB0
    );
  N0_GND : X_ZERO
    port map (
      O => N0
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);

end Structure;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library SIMPRIM;
use SIMPRIM.VCOMPONENTS.ALL;
use SIMPRIM.VPACKAGE.ALL;

entity peripheralfpgatop is
  port (
    pLWnR : in STD_LOGIC := 'X'; 
    pProbeSense : in STD_LOGIC := 'X'; 
    pnFpgaCs : in STD_LOGIC := 'X'; 
    pLCLK : in STD_LOGIC := 'X'; 
    pZ0 : in STD_LOGIC := 'X'; 
    pnLReset : in STD_LOGIC := 'X'; 
    pZ9 : in STD_LOGIC := 'X'; 
    pSampleClk : in STD_LOGIC := 'X'; 
    pPORT_FORMAT : out STD_LOGIC; 
    pSEL_1M_50R : out STD_LOGIC; 
    pLED_D8 : out STD_LOGIC; 
    pLED_D9 : out STD_LOGIC; 
    pCalDac_SDI : out STD_LOGIC; 
    pDdsFsk : out STD_LOGIC; 
    pDATA_FORMAT : out STD_LOGIC; 
    pCalDac_CLK : out STD_LOGIC; 
    pProbeDSel : out STD_LOGIC; 
    pSENSE : out STD_LOGIC; 
    pProbeDClk : out STD_LOGIC; 
    pSEL_AC_DC : out STD_LOGIC; 
    pATOD_RANGE : out STD_LOGIC; 
    pCalDac_nCS : out STD_LOGIC; 
    pDdsKey : out STD_LOGIC; 
    pCalDac_nLD : out STD_LOGIC; 
    pZ1 : out STD_LOGIC; 
    pZ2 : out STD_LOGIC; 
    pZ3 : out STD_LOGIC; 
    pZ4 : out STD_LOGIC; 
    pZ5 : out STD_LOGIC; 
    pProbeTx : out STD_LOGIC; 
    pZ6 : out STD_LOGIC; 
    pZ7 : out STD_LOGIC; 
    pZ8 : out STD_LOGIC; 
    pZ10 : out STD_LOGIC; 
    pZ11 : out STD_LOGIC; 
    pEncoder0In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pEncoder1In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pEncoder2In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pEncoder3In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pEncoder4In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pLA : in STD_LOGIC_VECTOR ( 31 downto 2 ); 
    pEncoder5In : in STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pPIO : inout STD_LOGIC_VECTOR ( 31 downto 2 ); 
    pLD : inout STD_LOGIC_VECTOR ( 31 downto 0 ); 
    pProbeAper : out STD_LOGIC_VECTOR ( 1 downto 0 ); 
    pProbeData : out STD_LOGIC_VECTOR ( 7 downto 0 ); 
    pAIN : out STD_LOGIC_VECTOR ( 3 downto 0 ); 
    pCAL : out STD_LOGIC_VECTOR ( 2 downto 0 ); 
    pGAIN : out STD_LOGIC_VECTOR ( 5 downto 0 ); 
    pAUX : out STD_LOGIC_VECTOR ( 1 downto 0 ) 
  );
end peripheralfpgatop;

architecture Structure of peripheralfpgatop is
  component delay_value_ram
    port (
      web : in STD_LOGIC := 'X'; 
      clka : in STD_LOGIC := 'X'; 
      clkb : in STD_LOGIC := 'X'; 
      addra : in STD_LOGIC_VECTOR ( 10 downto 0 ); 
      addrb : in STD_LOGIC_VECTOR ( 8 downto 0 ); 
      dinb : in STD_LOGIC_VECTOR ( 31 downto 0 ); 
      douta : out STD_LOGIC_VECTOR ( 7 downto 0 ) 
    );
  end component;
  signal PerLBusInterface0_vIncAddr : STD_LOGIC; 
  signal SampleClk : STD_LOGIC; 
  signal LCLK : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_31 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_30 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_29 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_28 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_27 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_26 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_25 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_24 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_23 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_22 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_21 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_20 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_19 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_18 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_17 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_16 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_0 : STD_LOGIC; 
  signal BScanCtrl0_BScanTrigger : STD_LOGIC; 
  signal pnLReset_IBUF : STD_LOGIC; 
  signal BScanCtrl0_n0084 : STD_LOGIC; 
  signal BScanCtrl0_BScanActive : STD_LOGIC; 
  signal BScanCtrl0_n0080 : STD_LOGIC; 
  signal BScanCtrl0_ClkEn : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount2 : STD_LOGIC; 
  signal BScanCtrl0_IncScanCount : STD_LOGIC; 
  signal pLED_D9_OBUF : STD_LOGIC; 
  signal BScanCtrl0_n0040 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_40 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_0 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_1 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_42 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_2 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_3 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_44 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_4 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_46 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_6 : STD_LOGIC; 
  signal BScanCtrl0_n0058 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_0 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_16 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_9 : STD_LOGIC; 
  signal BScanCtrl0_n0081 : STD_LOGIC; 
  signal BScanCtrl0_n0085 : STD_LOGIC; 
  signal BScanCtrl0_RxActive : STD_LOGIC; 
  signal BScanCtrl0_n0087 : STD_LOGIC; 
  signal BScanCtrl0_n0082 : STD_LOGIC; 
  signal BScanCtrl0_n0045 : STD_LOGIC; 
  signal BScanCtrl0_vRxCountDone : STD_LOGIC; 
  signal CHOICE673 : STD_LOGIC; 
  signal CHOICE674 : STD_LOGIC; 
  signal N50611 : STD_LOGIC; 
  signal CHOICE667 : STD_LOGIC; 
  signal CHOICE648 : STD_LOGIC; 
  signal CHOICE659 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_20 : STD_LOGIC; 
  signal CHOICE647 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_21 : STD_LOGIC; 
  signal CHOICE658 : STD_LOGIC; 
  signal CHOICE793 : STD_LOGIC; 
  signal CHOICE800 : STD_LOGIC; 
  signal BScanCtrl0_n004526_O : STD_LOGIC; 
  signal CHOICE808 : STD_LOGIC; 
  signal BScanCtrl0_n004553_O : STD_LOGIC; 
  signal CHOICE817 : STD_LOGIC; 
  signal BScanCtrl0_vScanCountDone : STD_LOGIC; 
  signal BScanCtrl0_n0086 : STD_LOGIC; 
  signal BScanCtrl0_pTriggerOut : STD_LOGIC; 
  signal Sample2xClk_NoBuff : STD_LOGIC; 
  signal Sample2xClk : STD_LOGIC; 
  signal SampleClk_NoBuff : STD_LOGIC; 
  signal SampleClkIn : STD_LOGIC; 
  signal pZ0_IBUF : STD_LOGIC; 
  signal Sample2xClkValid : STD_LOGIC; 
  signal EncoderMonitor0_pBScanTrigger : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_pStrobeOut : STD_LOGIC; 
  signal PerLBusInterface0_BlkRamWrite : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_0 : STD_LOGIC; 
  signal IFD0 : STD_LOGIC; 
  signal IFD1 : STD_LOGIC; 
  signal IFD2 : STD_LOGIC; 
  signal IFD3 : STD_LOGIC; 
  signal IFD4 : STD_LOGIC; 
  signal IFD5 : STD_LOGIC; 
  signal EncoderMonitor0_n0275 : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift : STD_LOGIC; 
  signal EncoderMonitor0_ClkEn1 : STD_LOGIC; 
  signal EncoderMonitor0_vTemp : STD_LOGIC; 
  signal EncoderMonitor0_ClkEn2 : STD_LOGIC; 
  signal EncoderMonitor0_n0453 : STD_LOGIC; 
  signal EncoderMonitor0_DecHysterisis : STD_LOGIC; 
  signal EncoderMonitor0_n0428 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_25 : STD_LOGIC; 
  signal EncoderMonitor0_n0428130_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_11_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_0_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0433 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_25 : STD_LOGIC; 
  signal EncoderMonitor0_n0433130_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_11_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_1_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0437 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_25 : STD_LOGIC; 
  signal EncoderMonitor0_n0437130_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_11_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_2_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0282 : STD_LOGIC; 
  signal EncoderMonitor0_n0283 : STD_LOGIC; 
  signal EncoderMonitor0_n0284 : STD_LOGIC; 
  signal EncoderMonitor0_n0415 : STD_LOGIC; 
  signal EncoderMonitor0_n0417 : STD_LOGIC; 
  signal EncoderMonitor0_n0419 : STD_LOGIC; 
  signal EncoderMonitor0_IncHysterisis : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc_1 : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMax : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMin : STD_LOGIC; 
  signal EncoderMonitor0_N26514 : STD_LOGIC; 
  signal EncoderMonitor0_SelEncDec : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc : STD_LOGIC; 
  signal EncoderMonitor0_N26680 : STD_LOGIC; 
  signal EncoderMonitor0_N26708 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_0_0 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_0_1 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_1_0 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_1_1 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_2_0 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_2_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0081 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_1 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_2 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_3 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_4 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_5 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_6 : STD_LOGIC; 
  signal EncoderMonitor0_n0295 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_0 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_16 : STD_LOGIC; 
  signal EncoderMonitor0_n0016 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_17 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_18 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_1 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_5 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_4 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_3 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_2 : STD_LOGIC; 
  signal EncoderMonitor0_n0071 : STD_LOGIC; 
  signal EncoderMonitor0_n0297 : STD_LOGIC; 
  signal EncoderMonitor0_n0452 : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0454 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_9 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_8 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_7 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_6 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_5 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_4 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_3 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_2 : STD_LOGIC; 
  signal EncoderMonitor0_n04541_1 : STD_LOGIC; 
  signal EncoderMonitor0_n0647 : STD_LOGIC; 
  signal EncoderMonitor0_n0649 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults : STD_LOGIC; 
  signal N46457 : STD_LOGIC; 
  signal N46498 : STD_LOGIC; 
  signal N46539 : STD_LOGIC; 
  signal N46580 : STD_LOGIC; 
  signal N46621 : STD_LOGIC; 
  signal N46664 : STD_LOGIC; 
  signal N45934 : STD_LOGIC; 
  signal N46119 : STD_LOGIC; 
  signal N46160 : STD_LOGIC; 
  signal N46201 : STD_LOGIC; 
  signal N46242 : STD_LOGIC; 
  signal N46283 : STD_LOGIC; 
  signal N46324 : STD_LOGIC; 
  signal N46365 : STD_LOGIC; 
  signal N46406 : STD_LOGIC; 
  signal CHOICE269 : STD_LOGIC; 
  signal CHOICE277 : STD_LOGIC; 
  signal CHOICE284 : STD_LOGIC; 
  signal N50604 : STD_LOGIC; 
  signal CHOICE367 : STD_LOGIC; 
  signal CHOICE374 : STD_LOGIC; 
  signal CHOICE751 : STD_LOGIC; 
  signal CHOICE757 : STD_LOGIC; 
  signal CHOICE783 : STD_LOGIC; 
  signal EncoderMonitor0_n042822_O : STD_LOGIC; 
  signal CHOICE764 : STD_LOGIC; 
  signal CHOICE765 : STD_LOGIC; 
  signal CHOICE754 : STD_LOGIC; 
  signal EncoderMonitor0_n042850_O : STD_LOGIC; 
  signal CHOICE772 : STD_LOGIC; 
  signal CHOICE776 : STD_LOGIC; 
  signal CHOICE780 : STD_LOGIC; 
  signal CHOICE782 : STD_LOGIC; 
  signal CHOICE679 : STD_LOGIC; 
  signal CHOICE685 : STD_LOGIC; 
  signal CHOICE711 : STD_LOGIC; 
  signal EncoderMonitor0_n043322_O : STD_LOGIC; 
  signal CHOICE692 : STD_LOGIC; 
  signal CHOICE693 : STD_LOGIC; 
  signal CHOICE682 : STD_LOGIC; 
  signal EncoderMonitor0_n043350_O : STD_LOGIC; 
  signal CHOICE700 : STD_LOGIC; 
  signal CHOICE704 : STD_LOGIC; 
  signal CHOICE708 : STD_LOGIC; 
  signal CHOICE710 : STD_LOGIC; 
  signal CHOICE715 : STD_LOGIC; 
  signal CHOICE721 : STD_LOGIC; 
  signal CHOICE747 : STD_LOGIC; 
  signal EncoderMonitor0_n043722_O : STD_LOGIC; 
  signal CHOICE728 : STD_LOGIC; 
  signal CHOICE729 : STD_LOGIC; 
  signal CHOICE718 : STD_LOGIC; 
  signal EncoderMonitor0_n043750_O : STD_LOGIC; 
  signal CHOICE736 : STD_LOGIC; 
  signal CHOICE740 : STD_LOGIC; 
  signal CHOICE744 : STD_LOGIC; 
  signal CHOICE746 : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOut : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOutEn : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd1 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_pStrobeOut : STD_LOGIC; 
  signal FocusUnitCtrl0_ProbeTx : STD_LOGIC; 
  signal CHOICE607 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd10 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd4 : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDone : STD_LOGIC; 
  signal FocusUnitCtrl0_N28907 : STD_LOGIC; 
  signal FocusUnitCtrl0_N28939 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd11 : STD_LOGIC; 
  signal FocusUnitCtrl0_StartDelay : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_pStrobeOut : STD_LOGIC; 
  signal CHOICE630 : STD_LOGIC; 
  signal CHOICE632 : STD_LOGIC; 
  signal CHOICE634 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_11 : STD_LOGIC; 
  signal FocusUnitCtrl0_N28945 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd5 : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDataDone : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd12 : STD_LOGIC; 
  signal N47138 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd13 : STD_LOGIC; 
  signal FocusUnitCtrl0_vLastTrigger : STD_LOGIC; 
  signal CHOICE347 : STD_LOGIC; 
  signal CHOICE351 : STD_LOGIC; 
  signal CHOICE353 : STD_LOGIC; 
  signal FocusUnitCtrl0_Rx_nTx : STD_LOGIC; 
  signal FocusUnitCtrl0_N28893 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd2 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd3 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd6 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd7 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd8 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd9 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0065 : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValInc : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValRst : STD_LOGIC; 
  signal FocusUnitCtrl0_N28934 : STD_LOGIC; 
  signal FocusUnitCtrl0_N28860 : STD_LOGIC; 
  signal N50619 : STD_LOGIC; 
  signal FocusUnitCtrl0_N28902 : STD_LOGIC; 
  signal FocusUnitCtrl0_N28924 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_n0007 : STD_LOGIC; 
  signal N47274 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_n0006 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_n0021 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_n0007 : STD_LOGIC; 
  signal CHOICE469 : STD_LOGIC; 
  signal N50615 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_n0006 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_n0025 : STD_LOGIC; 
  signal N47104 : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_0_Q : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_2_Q : STD_LOGIC; 
  signal N45601 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_0_8_O : STD_LOGIC; 
  signal CHOICE830 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_1_8_O : STD_LOGIC; 
  signal CHOICE823 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_2_8_O : STD_LOGIC; 
  signal CHOICE837 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_3_8_O : STD_LOGIC; 
  signal CHOICE844 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_4_SW0_O : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_5_SW0_O : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_6_SW0_O : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_7_SW0_O : STD_LOGIC; 
  signal CHOICE608 : STD_LOGIC; 
  signal CHOICE604 : STD_LOGIC; 
  signal CHOICE600 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0060 : STD_LOGIC; 
  signal N48649 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_9 : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeDClock : STD_LOGIC; 
  signal pnFpgaCs_IBUF : STD_LOGIC; 
  signal PerLBusInterface0_LWnR : STD_LOGIC; 
  signal I71_N4874 : STD_LOGIC; 
  signal PerLBusInterface0_FocusWrite : STD_LOGIC; 
  signal PerLBusInterface0_FocusCtrl : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_10_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_16 : STD_LOGIC; 
  signal pZ9_IBUF : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_9_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_0_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_1_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_2_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_3_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_4_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_5_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_6_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_7_Q : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_CLK : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nLD : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nCS : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataOut : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn : STD_LOGIC; 
  signal PerLBusInterface0_n0476 : STD_LOGIC; 
  signal PerLBusInterface0_CalClkEn1 : STD_LOGIC; 
  signal PerLBusInterface0_CalClkEn2 : STD_LOGIC; 
  signal PerLBusInterface0_CalDacStart : STD_LOGIC; 
  signal PerLBusInterface0_n0535 : STD_LOGIC; 
  signal PerLBusInterface0_CalDacActive : STD_LOGIC; 
  signal PerLBusInterface0_n0536 : STD_LOGIC; 
  signal PerLBusInterface0_n0196 : STD_LOGIC; 
  signal PerLBusInterface0_n0467 : STD_LOGIC; 
  signal PerLBusInterface0_n0473 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddrRst : STD_LOGIC; 
  signal PerLBusInterface0_n0458 : STD_LOGIC; 
  signal PerLBusInterface0_n0450 : STD_LOGIC; 
  signal PerLBusInterface0_n0510 : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus : STD_LOGIC; 
  signal PerLBusInterface0_n0502 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_53 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_55 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_56 : STD_LOGIC; 
  signal PerLBusInterface0_n0504 : STD_LOGIC; 
  signal PerLBusInterface0_ForceBScan : STD_LOGIC; 
  signal PerLBusInterface0_n0499 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_47 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_49 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_51 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_52 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataStart : STD_LOGIC; 
  signal PerLBusInterface0_n0501 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_1 : STD_LOGIC; 
  signal PerLBusInterface0_n0486 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_0 : STD_LOGIC; 
  signal PerLBusInterface0_I132_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_12 : STD_LOGIC; 
  signal PerLBusInterface0_I132_N49951_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_18 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_19 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_20 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_21 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_22 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_23 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_24 : STD_LOGIC; 
  signal PerLBusInterface0_N35462 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_0 : STD_LOGIC; 
  signal PerLBusInterface0_I156_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_15 : STD_LOGIC; 
  signal PerLBusInterface0_I180_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I199_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_N35455 : STD_LOGIC; 
  signal PerLBusInterface0_I211_N4995 : STD_LOGIC; 
  signal pProbeSense_IBUF : STD_LOGIC; 
  signal PerLBusInterface0_I230_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I262_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I262_N49951_1 : STD_LOGIC; 
  signal PerLBusInterface0_N35395 : STD_LOGIC; 
  signal PerLBusInterface0_I294_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I294_N49951_1 : STD_LOGIC; 
  signal PerLBusInterface0_I326_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I326_N49951_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_0 : STD_LOGIC; 
  signal PerLBusInterface0_I331_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_2 : STD_LOGIC; 
  signal PerLBusInterface0_N35448 : STD_LOGIC; 
  signal N50000 : STD_LOGIC; 
  signal PerLBusInterface0_I361_N4995 : STD_LOGIC; 
  signal N49884 : STD_LOGIC; 
  signal N49890 : STD_LOGIC; 
  signal N49896 : STD_LOGIC; 
  signal N49902 : STD_LOGIC; 
  signal N49904 : STD_LOGIC; 
  signal N49906 : STD_LOGIC; 
  signal N49908 : STD_LOGIC; 
  signal N49954 : STD_LOGIC; 
  signal N49956 : STD_LOGIC; 
  signal N49958 : STD_LOGIC; 
  signal N49960 : STD_LOGIC; 
  signal N49962 : STD_LOGIC; 
  signal N49966 : STD_LOGIC; 
  signal N49972 : STD_LOGIC; 
  signal N49978 : STD_LOGIC; 
  signal PerLBusInterface0_I361_N49951_1 : STD_LOGIC; 
  signal N49984 : STD_LOGIC; 
  signal N49990 : STD_LOGIC; 
  signal N49968 : STD_LOGIC; 
  signal N49974 : STD_LOGIC; 
  signal N49980 : STD_LOGIC; 
  signal N49986 : STD_LOGIC; 
  signal N49992 : STD_LOGIC; 
  signal N49996 : STD_LOGIC; 
  signal N50004 : STD_LOGIC; 
  signal N49888 : STD_LOGIC; 
  signal N49894 : STD_LOGIC; 
  signal N49900 : STD_LOGIC; 
  signal N49998 : STD_LOGIC; 
  signal N50006 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_2 : STD_LOGIC; 
  signal PerLBusInterface0_I391_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_16 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_17 : STD_LOGIC; 
  signal PerLBusInterface0_I391_N49951_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_18 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_19 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_20 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_21 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_22 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_23 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_24 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_26 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_27 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_28 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_29 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_30 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_31 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_31_Q : STD_LOGIC; 
  signal PerLBusInterface0_I392_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_I408_N4995 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_63_12 : STD_LOGIC; 
  signal N45638 : STD_LOGIC; 
  signal PerLBusInterface0_n0218 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_1 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_2 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_3 : STD_LOGIC; 
  signal PerLBusInterface0_n0217 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_1 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_2 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_3 : STD_LOGIC; 
  signal PerLBusInterface0_n0216 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_1 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_2 : STD_LOGIC; 
  signal PerLBusInterface0_n0215 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_1 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_2 : STD_LOGIC; 
  signal PerLBusInterface0_n0214 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_1 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_2 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_7_1 : STD_LOGIC; 
  signal N45718 : STD_LOGIC; 
  signal PerLBusInterface0_N35411 : STD_LOGIC; 
  signal PerLBusInterface0_N35424 : STD_LOGIC; 
  signal pLA_7_IBUF : STD_LOGIC; 
  signal pLA_6_IBUF : STD_LOGIC; 
  signal pLA_5_IBUF : STD_LOGIC; 
  signal pLA_4_IBUF : STD_LOGIC; 
  signal pLA_3_IBUF : STD_LOGIC; 
  signal pLA_2_IBUF : STD_LOGIC; 
  signal N49964 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_31 : STD_LOGIC; 
  signal N49910 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_9 : STD_LOGIC; 
  signal N49912 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_10 : STD_LOGIC; 
  signal N49914 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_11 : STD_LOGIC; 
  signal N49916 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_12 : STD_LOGIC; 
  signal N49918 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_13 : STD_LOGIC; 
  signal N49920 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_14 : STD_LOGIC; 
  signal N49924 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_15 : STD_LOGIC; 
  signal N49928 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_16 : STD_LOGIC; 
  signal N49932 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_17 : STD_LOGIC; 
  signal N49936 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_18 : STD_LOGIC; 
  signal N49970 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_0 : STD_LOGIC; 
  signal N49922 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_19 : STD_LOGIC; 
  signal N49926 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_20 : STD_LOGIC; 
  signal N49930 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_21 : STD_LOGIC; 
  signal N49934 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_22 : STD_LOGIC; 
  signal N49938 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_23 : STD_LOGIC; 
  signal N49940 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_24 : STD_LOGIC; 
  signal N49944 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_25 : STD_LOGIC; 
  signal N49948 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_26 : STD_LOGIC; 
  signal N49950 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_27 : STD_LOGIC; 
  signal N49952 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_28 : STD_LOGIC; 
  signal N49976 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_1 : STD_LOGIC; 
  signal N49942 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_29 : STD_LOGIC; 
  signal N49946 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_30 : STD_LOGIC; 
  signal N49982 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_2 : STD_LOGIC; 
  signal N49988 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_3 : STD_LOGIC; 
  signal N49994 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_4 : STD_LOGIC; 
  signal N50002 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_5 : STD_LOGIC; 
  signal N49886 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_6 : STD_LOGIC; 
  signal N49892 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_7 : STD_LOGIC; 
  signal N49898 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_8 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_9 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_10 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_11 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_12 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_13 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_14 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_16 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_17 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_18 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_0 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_19 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_20 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_21 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_22 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_23 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_24 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_25 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_26 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_27 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_28 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_29 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_30 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_5 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_6 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_7 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_8 : STD_LOGIC; 
  signal N50851 : STD_LOGIC; 
  signal PerLBusInterface0_n0372 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_0 : STD_LOGIC; 
  signal N50863 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_10 : STD_LOGIC; 
  signal PerLBusInterface0_n0409 : STD_LOGIC; 
  signal N50847 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_11 : STD_LOGIC; 
  signal N50871 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_12 : STD_LOGIC; 
  signal N50843 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_13 : STD_LOGIC; 
  signal N50887 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_1 : STD_LOGIC; 
  signal N50891 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_2 : STD_LOGIC; 
  signal N50883 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_3 : STD_LOGIC; 
  signal N50859 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_4 : STD_LOGIC; 
  signal N50855 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_5 : STD_LOGIC; 
  signal N50879 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_6 : STD_LOGIC; 
  signal N50839 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_7 : STD_LOGIC; 
  signal N50875 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_8 : STD_LOGIC; 
  signal N50867 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_9 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net40 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net55 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net58 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net61 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net64 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net67 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net70 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net73 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net76 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net79 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net82 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net43 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net85 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net88 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net91 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net94 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net100 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net103 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net133 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net46 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net49 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net52 : STD_LOGIC; 
  signal N50108 : STD_LOGIC; 
  signal N50122 : STD_LOGIC; 
  signal N50132 : STD_LOGIC; 
  signal N50104 : STD_LOGIC; 
  signal N50126 : STD_LOGIC; 
  signal N50112 : STD_LOGIC; 
  signal N50100 : STD_LOGIC; 
  signal N50092 : STD_LOGIC; 
  signal N50116 : STD_LOGIC; 
  signal N50084 : STD_LOGIC; 
  signal PerLBusInterface0_n0312 : STD_LOGIC; 
  signal PerLBusInterface0_n0508 : STD_LOGIC; 
  signal PerLBusInterface0_n0461 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_10_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_11_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_12_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_14_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_1_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_23_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_24_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_6_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_7_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_8_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_1 : STD_LOGIC; 
  signal PerLBusInterface0_n0482 : STD_LOGIC; 
  signal PerLBusInterface0_n04821_1 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_31 : STD_LOGIC; 
  signal PerLBusInterface0_n0484 : STD_LOGIC; 
  signal PerLBusInterface0_n04841_1 : STD_LOGIC; 
  signal PerLBusInterface0_n0489 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_15 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_16 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_17 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_18 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_19 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_2 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_20 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_21 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_22 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_25 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_26 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_27 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_28 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_29 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_3 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_30 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_31 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_4 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_5 : STD_LOGIC; 
  signal PerLBusInterface0_n0492 : STD_LOGIC; 
  signal PerLBusInterface0_n0464 : STD_LOGIC; 
  signal PerLBusInterface0_n0237 : STD_LOGIC; 
  signal PerLBusInterface0_n0470 : STD_LOGIC; 
  signal PerLBusInterface0_n0496 : STD_LOGIC; 
  signal PerLBusInterface0_n0479 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_0_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_1_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_10_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_14_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_15_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_16_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_17_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_18_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_19_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_20_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_3_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_4_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_5_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_6_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_63_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_7_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_8_Q : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_9_Q : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_n0007 : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_n0013 : STD_LOGIC; 
  signal PerLBusInterface0_n0347 : STD_LOGIC; 
  signal N44611 : STD_LOGIC; 
  signal N44557 : STD_LOGIC; 
  signal PerLBusInterface0_n0295 : STD_LOGIC; 
  signal PerLBusInterface0_n0297 : STD_LOGIC; 
  signal N50895 : STD_LOGIC; 
  signal N46943 : STD_LOGIC; 
  signal N46894 : STD_LOGIC; 
  signal N47040 : STD_LOGIC; 
  signal N46985 : STD_LOGIC; 
  signal PerLBusInterface0_n0537 : STD_LOGIC; 
  signal TriggerDelay0_n0021 : STD_LOGIC; 
  signal TriggerDelay0_n0022 : STD_LOGIC; 
  signal TriggerDelay0_n0084 : STD_LOGIC; 
  signal TriggerDelay0_n0023 : STD_LOGIC; 
  signal TriggerDelay0_n0082 : STD_LOGIC; 
  signal TriggerDelay0_n0024 : STD_LOGIC; 
  signal TriggerDelay0_n0080 : STD_LOGIC; 
  signal TriggerDelay0_n0025 : STD_LOGIC; 
  signal TriggerDelay0_n0078 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_59 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_61 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_63 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_65 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_67 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_69 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_71 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_72 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_281_O : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_1 : STD_LOGIC; 
  signal N50536 : STD_LOGIC; 
  signal N50556 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_59 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_61 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_63 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_65 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_67 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_69 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_71 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_72 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_281_O : STD_LOGIC; 
  signal N50560 : STD_LOGIC; 
  signal N50524 : STD_LOGIC; 
  signal N50548 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_59 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_61 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_63 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_65 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_67 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_69 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_71 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_72 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_281_O : STD_LOGIC; 
  signal N50903 : STD_LOGIC; 
  signal N50528 : STD_LOGIC; 
  signal N50564 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_59 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_61 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_63 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_65 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_67 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_69 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_71 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_72 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_281_O : STD_LOGIC; 
  signal N50552 : STD_LOGIC; 
  signal N50568 : STD_LOGIC; 
  signal TriggerDelay0_n0048 : STD_LOGIC; 
  signal TriggerDelay0_n0049 : STD_LOGIC; 
  signal TriggerDelay0_n0050 : STD_LOGIC; 
  signal TriggerDelay0_n0051 : STD_LOGIC; 
  signal TriggerDelay0_n0064 : STD_LOGIC; 
  signal CHOICE519 : STD_LOGIC; 
  signal CHOICE527 : STD_LOGIC; 
  signal CHOICE534 : STD_LOGIC; 
  signal N50592 : STD_LOGIC; 
  signal CHOICE488 : STD_LOGIC; 
  signal CHOICE496 : STD_LOGIC; 
  signal CHOICE503 : STD_LOGIC; 
  signal N50588 : STD_LOGIC; 
  signal CHOICE550 : STD_LOGIC; 
  signal CHOICE558 : STD_LOGIC; 
  signal CHOICE565 : STD_LOGIC; 
  signal N50600 : STD_LOGIC; 
  signal CHOICE581 : STD_LOGIC; 
  signal CHOICE589 : STD_LOGIC; 
  signal CHOICE596 : STD_LOGIC; 
  signal N50596 : STD_LOGIC; 
  signal GSR : STD_LOGIC; 
  signal GTS : STD_LOGIC; 
  signal PerLBusInterface0_n0372_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0376_inst_lut2_44 : STD_LOGIC; 
  signal PerLBusInterface0_n0376_1_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0376_1_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0376_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0376_inst_cy_106 : STD_LOGIC; 
  signal PerLBusInterface0_n0376_1_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0376_inst_cy_108 : STD_LOGIC; 
  signal PerLBusInterface0_n0376_2_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_4_rt : STD_LOGIC; 
  signal PerLBusInterface0_n0376_4_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0376_4_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_n0409_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0409_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0461_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0464_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0470_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0484_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0484_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0489_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0492_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0496_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0537_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0537_GROM : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_CLK_FROM : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_CLK_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0277 : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nCS_X : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nCS_FROM : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nCS_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0279 : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nLD_FROM : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nLD_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0278 : STD_LOGIC; 
  signal PerLBusInterface0_n0342 : STD_LOGIC; 
  signal PerLBusInterface0_pEncoderReset_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0343 : STD_LOGIC; 
  signal PerLBusInterface0_pEncoderReset_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0341 : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn_X : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn_FROM : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn_Y : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn_GROM : STD_LOGIC; 
  signal PerLBusInterface0_vCount_0_BXMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_vCount_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_vCount_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_vIncAddr_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_vIncAddr_GROM : STD_LOGIC; 
  signal TriggerDelay0_ActiveCount_1_GROM : STD_LOGIC; 
  signal TriggerDelay0_ActiveCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_ActiveCount_1_BYMUXNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_0_FROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_0_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_1_FROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_1_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_2_FROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_2_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_3_FROM : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_3_GROM : STD_LOGIC; 
  signal TriggerDelay0_n0022_rt : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_145 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_128 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_291_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_129 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_301_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_147 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_130 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_311_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_131 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_321_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_149 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_132 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_331_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_133 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_341_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_151 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_134 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_35 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_135 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_361_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_153 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_136 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_37 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_137 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_381_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_155 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_138 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_391_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_139 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_401_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_157 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_140 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_411_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_141 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_421_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_cy_159 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_142 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_lut3_431_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_inst_sum_143 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_72_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_72_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_72_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_n0023_rt : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_145 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_128 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_291_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_129 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_301_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_147 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_130 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_311_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_131 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_321_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_149 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_132 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_33 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_133 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_34 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_151 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_134 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_35 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_135 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_36 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_153 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_136 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_37 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_137 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_381_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_155 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_138 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_391_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_139 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_401_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_157 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_140 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_411_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_141 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_421_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_cy_159 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_142 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_lut3_431_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_inst_sum_143 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_72_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_72_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_72_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_n0024_rt : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_145 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_128 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_291_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_129 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_301_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_147 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_130 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_311_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_131 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_321_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_149 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_132 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_33 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_133 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_341_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_151 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_134 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_35 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_135 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_36 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_153 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_136 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_37 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_137 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_381_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_155 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_138 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_391_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_139 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_401_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_157 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_140 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_411_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_141 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_421_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_cy_159 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_142 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_lut3_431_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_inst_sum_143 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_72_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_72_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_72_CYINIT : STD_LOGIC; 
  signal CHOICE565_GROM : STD_LOGIC; 
  signal CHOICE581_GROM : STD_LOGIC; 
  signal CHOICE589_X : STD_LOGIC; 
  signal CHOICE589_FROM : STD_LOGIC; 
  signal CHOICE589_GROM : STD_LOGIC; 
  signal CHOICE596_GROM : STD_LOGIC; 
  signal CHOICE600_GROM : STD_LOGIC; 
  signal CHOICE608_FROM : STD_LOGIC; 
  signal CHOICE608_GROM : STD_LOGIC; 
  signal CHOICE658_FROM : STD_LOGIC; 
  signal CHOICE658_GROM : STD_LOGIC; 
  signal CHOICE667_GROM : STD_LOGIC; 
  signal CHOICE673_FROM : STD_LOGIC; 
  signal CHOICE673_GROM : STD_LOGIC; 
  signal CHOICE679_GROM : STD_LOGIC; 
  signal CHOICE682_GROM : STD_LOGIC; 
  signal CHOICE685_GROM : STD_LOGIC; 
  signal CHOICE692_GROM : STD_LOGIC; 
  signal CHOICE700_GROM : STD_LOGIC; 
  signal CHOICE704_GROM : STD_LOGIC; 
  signal CHOICE708_X : STD_LOGIC; 
  signal CHOICE708_FROM : STD_LOGIC; 
  signal CHOICE708_GROM : STD_LOGIC; 
  signal CHOICE711_FROM : STD_LOGIC; 
  signal CHOICE711_GROM : STD_LOGIC; 
  signal CHOICE721_GROM : STD_LOGIC; 
  signal CHOICE728_GROM : STD_LOGIC; 
  signal CHOICE736_GROM : STD_LOGIC; 
  signal CHOICE740_GROM : STD_LOGIC; 
  signal CHOICE744_GROM : STD_LOGIC; 
  signal CHOICE747_FROM : STD_LOGIC; 
  signal CHOICE747_GROM : STD_LOGIC; 
  signal CHOICE751_GROM : STD_LOGIC; 
  signal CHOICE754_GROM : STD_LOGIC; 
  signal CHOICE764_GROM : STD_LOGIC; 
  signal CHOICE772_GROM : STD_LOGIC; 
  signal CHOICE776_GROM : STD_LOGIC; 
  signal CHOICE780_GROM : STD_LOGIC; 
  signal CHOICE783_FROM : STD_LOGIC; 
  signal CHOICE783_GROM : STD_LOGIC; 
  signal CHOICE793_X : STD_LOGIC; 
  signal CHOICE793_FROM : STD_LOGIC; 
  signal CHOICE793_GROM : STD_LOGIC; 
  signal CHOICE800_X : STD_LOGIC; 
  signal CHOICE800_FROM : STD_LOGIC; 
  signal CHOICE800_GROM : STD_LOGIC; 
  signal CHOICE808_GROM : STD_LOGIC; 
  signal CHOICE837_FROM : STD_LOGIC; 
  signal CHOICE837_GROM : STD_LOGIC; 
  signal CHOICE844_FROM : STD_LOGIC; 
  signal CHOICE844_GROM : STD_LOGIC; 
  signal CLKDLL0_CLKDV : STD_LOGIC; 
  signal CLKDLL0_CLK90 : STD_LOGIC; 
  signal CLKDLL0_CLK270 : STD_LOGIC; 
  signal CLKDLL0_CLK180 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB15 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB14 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB13 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB12 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB11 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB10 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB9 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOB8 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA15 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA14 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA13 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA12 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA11 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA10 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA9 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA8 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA7 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA6 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA5 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA4 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA3 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA2 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA1 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_DOA0 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRB3 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRB2 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRB1 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRB0 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRA3 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRA2 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRA1 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_ADDRA0 : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO : STD_LOGIC; 
  signal DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ONE : STD_LOGIC; 
  signal Encoder0In_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Encoder1In_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal Encoder2In_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift_FROM : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift_GROM : STD_LOGIC; 
  signal EncoderMonitor0_ClkEn2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0281 : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_Madd_n0000_inst_lut2_0 : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_GROM : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_0 : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_FROM : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_3_rt : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_2 : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_2 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_101_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_3 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_111_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_4 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_121_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_5 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_131_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_6 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_141_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_7 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_151_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_161_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_171_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_181_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_191_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_201_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_211_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_41 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_221_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_231_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_43 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_241_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_45 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_47 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_49 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_60 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_51 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_62 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_53 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_64 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_55 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_66 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_57 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_68 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_38_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_38_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_59 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_0 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_81_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_multand_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut4_91_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_sum_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut2_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_11_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_11_1_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_cy_37_rt : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_2 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_101_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_3 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_111_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_4 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_121_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_5 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_131_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_6 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_141_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_7 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_151_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_161_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_171_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_181_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_191_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_201_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_211_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_41 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_221_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_231_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_43 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_241_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_45 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_47 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_49 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_60 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_51 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_62 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_53 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_64 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_55 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_66 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_57 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_68 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_38_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_38_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_59 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_0 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_81_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_multand_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut4_91_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_sum_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut2_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_11_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_11_1_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_cy_37_rt : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_2 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_101_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_3 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_111_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_4 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_121_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_5 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_131_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_6 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_141_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_7 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_151_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_8 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_161_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_9 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_171_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_10 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_181_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_11 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_191_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_12 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_201_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_40 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_13 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_211_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_41 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_14 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_221_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_42 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_15 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_231_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_43 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_16 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_241_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_44 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_17 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_45 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_18 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_46 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_47 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_20 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_48 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_21 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_49 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_22 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_50 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_23 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_31 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_60 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_51 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_24 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_32 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_52 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_25 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_33 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_62 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_53 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_26 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_34 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_54 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_27 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_35 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_64 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_55 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_36 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_56 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_37 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_66 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_57 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_30 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_58 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_39 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_68 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_38_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_38_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_59 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_0 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_81_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_28 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_multand_1 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut4_91_O : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_38 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_sum_29 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut2_19 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_11_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_11_1_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_cy_37_rt : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_n0289 : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0288 : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_2_FROM : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0290 : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_0_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_0_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_1_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_2_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_0_FROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_0_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_1_FROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_2_GROM : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0078 : STD_LOGIC; 
  signal EncoderMonitor0_IncHysterisis_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0079 : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_0_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_2_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_2_FROM : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0296 : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_0 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_5_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_1 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_4 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_2 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_3 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_6 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_7_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_4 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_5 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_8 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_9_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYINIT : STD_LOGIC; 
  signal N51044 : STD_LOGIC; 
  signal N51042 : STD_LOGIC; 
  signal EncoderMonitor0_n0072 : STD_LOGIC; 
  signal EncoderMonitor0_SelEncDec_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N51004 : STD_LOGIC; 
  signal N51002 : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc_F5MUX : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n0205 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_101_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0206 : STD_LOGIC; 
  signal EncoderMonitor0_n0203 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_103_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0204 : STD_LOGIC; 
  signal EncoderMonitor0_n0201 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_105_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0202 : STD_LOGIC; 
  signal EncoderMonitor0_n0199 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_107_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0200 : STD_LOGIC; 
  signal EncoderMonitor0_n0197 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_109_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0198 : STD_LOGIC; 
  signal EncoderMonitor0_n0195 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_111_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0196 : STD_LOGIC; 
  signal EncoderMonitor0_n0193 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_113_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0194 : STD_LOGIC; 
  signal EncoderMonitor0_n0191 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_115_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0192 : STD_LOGIC; 
  signal EncoderMonitor0_n0189 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_117_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0190 : STD_LOGIC; 
  signal EncoderMonitor0_n0187 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_119_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0188 : STD_LOGIC; 
  signal EncoderMonitor0_n0103 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0104 : STD_LOGIC; 
  signal EncoderMonitor0_n0185 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_121_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0186 : STD_LOGIC; 
  signal EncoderMonitor0_n0183 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_123_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0184 : STD_LOGIC; 
  signal EncoderMonitor0_n0181 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_125_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0182 : STD_LOGIC; 
  signal EncoderMonitor0_n0179 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_127_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0180 : STD_LOGIC; 
  signal EncoderMonitor0_n0241 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_129_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0242 : STD_LOGIC; 
  signal EncoderMonitor0_n0239 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_131_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0240 : STD_LOGIC; 
  signal EncoderMonitor0_n0237 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_133_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0238 : STD_LOGIC; 
  signal EncoderMonitor0_n0235 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_135_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0236 : STD_LOGIC; 
  signal EncoderMonitor0_n0233 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_137_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0234 : STD_LOGIC; 
  signal EncoderMonitor0_n0231 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_139_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0232 : STD_LOGIC; 
  signal EncoderMonitor0_n0101 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0102 : STD_LOGIC; 
  signal EncoderMonitor0_n0229 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_141_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0230 : STD_LOGIC; 
  signal EncoderMonitor0_n0227 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_143_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0228 : STD_LOGIC; 
  signal EncoderMonitor0_n0225 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_145_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0226 : STD_LOGIC; 
  signal EncoderMonitor0_n0223 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_147_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0224 : STD_LOGIC; 
  signal EncoderMonitor0_n0221 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_149_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0222 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_150_X : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_150_FROM : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_150_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0220 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_151_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0219 : STD_LOGIC; 
  signal EncoderMonitor0_n0217 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_153_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0218 : STD_LOGIC; 
  signal EncoderMonitor0_n0215 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_155_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0216 : STD_LOGIC; 
  signal EncoderMonitor0_n0213 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_157_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0214 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_159_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0211 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_159_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0212 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_15_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0099 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0100 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_161_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_161_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0273 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_161_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0274 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_163_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_163_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0271 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_163_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0272 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_165_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0269 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_165_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0270 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_167_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_167_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0267 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_167_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0268 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_168_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_168_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0266 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_169_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_169_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0265 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0098 : STD_LOGIC; 
  signal EncoderMonitor0_n0263 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_171_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0264 : STD_LOGIC; 
  signal EncoderMonitor0_n0261 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_173_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0262 : STD_LOGIC; 
  signal EncoderMonitor0_n0259 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_175_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0260 : STD_LOGIC; 
  signal EncoderMonitor0_n0257 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_177_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0258 : STD_LOGIC; 
  signal EncoderMonitor0_n0255 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_179_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0256 : STD_LOGIC; 
  signal EncoderMonitor0_n0253 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_181_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0254 : STD_LOGIC; 
  signal EncoderMonitor0_n0251 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_183_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0252 : STD_LOGIC; 
  signal EncoderMonitor0_n0249 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_185_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0250 : STD_LOGIC; 
  signal EncoderMonitor0_n0247 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_187_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0248 : STD_LOGIC; 
  signal EncoderMonitor0_n0245 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_189_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0246 : STD_LOGIC; 
  signal EncoderMonitor0_n0096 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0097 : STD_LOGIC; 
  signal EncoderMonitor0_n0243 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_191_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0244 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0095 : STD_LOGIC; 
  signal EncoderMonitor0_n0113 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0114 : STD_LOGIC; 
  signal EncoderMonitor0_n0093 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0094 : STD_LOGIC; 
  signal EncoderMonitor0_n0091 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0092 : STD_LOGIC; 
  signal EncoderMonitor0_n0089 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0090 : STD_LOGIC; 
  signal EncoderMonitor0_n0087 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0088 : STD_LOGIC; 
  signal EncoderMonitor0_n0085 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0086 : STD_LOGIC; 
  signal EncoderMonitor0_n0083 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0084 : STD_LOGIC; 
  signal EncoderMonitor0_n0145 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_33_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0146 : STD_LOGIC; 
  signal EncoderMonitor0_n0143 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_35_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0144 : STD_LOGIC; 
  signal EncoderMonitor0_n0141 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_37_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0142 : STD_LOGIC; 
  signal EncoderMonitor0_n0139 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_39_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0140 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_3_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0111 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0112 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_41_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0137 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_41_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0138 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_43_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_43_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0135 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_43_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0136 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_45_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_45_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0133 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_45_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0134 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_47_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_47_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0131 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_47_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0132 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_49_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0129 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_49_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0130 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_4_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_4_FROM : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0110 : STD_LOGIC; 
  signal EncoderMonitor0_n0127 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_51_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0128 : STD_LOGIC; 
  signal EncoderMonitor0_n0125 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_53_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0126 : STD_LOGIC; 
  signal EncoderMonitor0_n0123 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_55_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0124 : STD_LOGIC; 
  signal EncoderMonitor0_n0121 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_57_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0122 : STD_LOGIC; 
  signal EncoderMonitor0_n0119 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_59_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0120 : STD_LOGIC; 
  signal EncoderMonitor0_n0117 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_61_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0118 : STD_LOGIC; 
  signal EncoderMonitor0_n0115 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_63_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0116 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_64_FROM : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_64_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0178 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_65_X : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_65_FROM : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_65_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0177 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_67_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0175 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_67_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0176 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_69_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0173 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_69_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0174 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_6_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0108 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0109 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_71_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_71_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0171 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_71_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0172 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_73_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_73_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0169 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_73_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0170 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_75_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_75_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0167 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_75_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0168 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_77_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_n0165 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_77_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0166 : STD_LOGIC; 
  signal EncoderMonitor0_n0163 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_79_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0164 : STD_LOGIC; 
  signal EncoderMonitor0_n0161 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_81_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0162 : STD_LOGIC; 
  signal EncoderMonitor0_n0159 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_83_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0160 : STD_LOGIC; 
  signal EncoderMonitor0_n0157 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_85_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0158 : STD_LOGIC; 
  signal EncoderMonitor0_n0155 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_87_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0156 : STD_LOGIC; 
  signal EncoderMonitor0_n0153 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_89_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0154 : STD_LOGIC; 
  signal EncoderMonitor0_n0106 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0107 : STD_LOGIC; 
  signal EncoderMonitor0_n0151 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_91_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0152 : STD_LOGIC; 
  signal EncoderMonitor0_n0149 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_93_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0150 : STD_LOGIC; 
  signal EncoderMonitor0_n0147 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_95_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0148 : STD_LOGIC; 
  signal EncoderMonitor0_n0209 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_97_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0210 : STD_LOGIC; 
  signal EncoderMonitor0_n0207 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_99_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0208 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0105 : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift_rt : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_0_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_3 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_cy_28 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_0_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_20 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_4 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_21 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_5 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_cy_30 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_22 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_6 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_23 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_7 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_cy_32 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_24 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_8 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_25 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_LOGIC_ONE : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_9 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_cy_34 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_26 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_lut3_10 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_inst_sum_27 : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_7_GROM : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_7_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_FROM : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_GROM : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6_Y : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6_GROM : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N51009 : STD_LOGIC; 
  signal N51007 : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_10_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_10_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_11_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_11_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_12_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_12_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_13_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_13_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_14_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_14_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_15_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_15_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_1_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_1_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_2_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_2_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_3_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_3_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_4_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_4_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_5_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_5_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_6_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_6_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_7_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_7_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_8_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_8_O : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_9_FROM : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0077_9_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_131_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_10_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_10_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_10_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_141_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_22 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_10_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_151_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_12_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_12_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_12_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_16 : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_24 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_12_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_17 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_14_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_14_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_18 : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_26 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_14_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut1_0 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_1_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_1_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_41_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_12 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_1_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_51_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_2_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_2_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_2_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_61_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_14 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_2_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_71_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_4_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_4_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_4_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_81_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_16 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_4_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_91_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_6_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_6_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_6_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_101_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_18 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_6_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_111_O : STD_LOGIC; 
  signal EncoderMonitor0_n0279_8_XORF : STD_LOGIC; 
  signal EncoderMonitor0_n0279_8_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_n0279_8_XORG : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_lut2_121_O : STD_LOGIC; 
  signal EncoderMonitor0_Maddsub_n0279_inst_cy_20 : STD_LOGIC; 
  signal EncoderMonitor0_n0279_8_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_6 : STD_LOGIC; 
  signal EncoderMonitor0_n0295_CYMUXG : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_lut4_7 : STD_LOGIC; 
  signal EncoderMonitor0_Mcompar_n0295_inst_cy_10 : STD_LOGIC; 
  signal EncoderMonitor0_n0295_LOGIC_ZERO : STD_LOGIC; 
  signal EncoderMonitor0_n0295_CYINIT : STD_LOGIC; 
  signal EncoderMonitor0_n0419_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n0419_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n042822_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n042822_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n042850_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n042850_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n043322_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n043322_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n043350_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n043350_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n0437130_1_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n0437130_1_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n043722_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n043722_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n043750_O_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n043750_O_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n0453_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n0453_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_5_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_5_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_6_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_6_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_7_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_7_GROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_8_FROM : STD_LOGIC; 
  signal EncoderMonitor0_n04541_8_GROM : STD_LOGIC; 
  signal EncoderMonitor0_pBScanTrigger_FROM : STD_LOGIC; 
  signal EncoderMonitor0_pBScanTrigger_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_n0080 : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOutEn_X : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOutEn_FROM : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOutEn_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMax_FROM : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMax_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0321 : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd10_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd9_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd11_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd11_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd3_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd2_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd4_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N50048 : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd6_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd5_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd8_In : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd7_In : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDataDone_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDataDone_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0052 : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDone_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDone_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_0_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_1_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValInc_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValInc_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0045 : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValRst_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValRst_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd13_In : STD_LOGIC; 
  signal FocusUnitCtrl0_N28934_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_N28934_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_ProbeTx_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_ProbeTx_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd1_In : STD_LOGIC; 
  signal FocusUnitCtrl0_Rx_nTx_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_Rx_nTx_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0047 : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_FeedbackBit : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_pStrobeOut_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_FeedbackBit : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_X : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_n0006_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_n0006_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_pStrobeOut_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_pStrobeOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_Madd_n0059_inst_lut2_0 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_1_CYMUXG : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_1_XORG : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_1_GROM : STD_LOGIC; 
  signal FocusUnitCtrl0_Madd_n0059_inst_cy_0 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_1_LOGIC_ZERO : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_2_LOGIC_ZERO : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_2_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_2_XORF : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_2_XORG : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_3_rt : STD_LOGIC; 
  signal FocusUnitCtrl0_Madd_n0059_inst_cy_2 : STD_LOGIC; 
  signal FocusUnitCtrl0_n0059_2_CYINIT : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_0_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0044_0_Q : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_2_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0044_2_Q : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeDClock_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeDClock_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0041 : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_0_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_0_13_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_1_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_1_13_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_2_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_2_13_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_3_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_3_13_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_4_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_4_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_5_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_5_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_6_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_6_O : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_7_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0046_7_O : STD_LOGIC; 
  signal FocusUnitCtrl0_vLastTrigger_FROM : STD_LOGIC; 
  signal FocusUnitCtrl0_vLastTrigger_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd12_In : STD_LOGIC; 
  signal I69_0_TINV : STD_LOGIC; 
  signal I69_1_TINV : STD_LOGIC; 
  signal I69_2_TINV : STD_LOGIC; 
  signal I69_3_TINV : STD_LOGIC; 
  signal I69_4_TINV : STD_LOGIC; 
  signal I69_5_TINV : STD_LOGIC; 
  signal I69_6_TINV : STD_LOGIC; 
  signal I70_0_TINV : STD_LOGIC; 
  signal I70_0_TMUXNOT : STD_LOGIC; 
  signal I70_1_TINV : STD_LOGIC; 
  signal I70_1_TMUXNOT : STD_LOGIC; 
  signal I70_2_TINV : STD_LOGIC; 
  signal I70_2_TMUXNOT : STD_LOGIC; 
  signal I70_3_TINV : STD_LOGIC; 
  signal I70_3_TMUXNOT : STD_LOGIC; 
  signal I70_4_TINV : STD_LOGIC; 
  signal I70_4_TMUXNOT : STD_LOGIC; 
  signal I70_5_TINV : STD_LOGIC; 
  signal I70_5_TMUXNOT : STD_LOGIC; 
  signal I70_6_TINV : STD_LOGIC; 
  signal I70_6_TMUXNOT : STD_LOGIC; 
  signal LD_Out_11_GROM : STD_LOGIC; 
  signal LD_Out_13_GROM : STD_LOGIC; 
  signal LD_Out_15_GROM : STD_LOGIC; 
  signal LD_Out_17_GROM : STD_LOGIC; 
  signal LD_Out_19_GROM : STD_LOGIC; 
  signal LD_Out_1_GROM : STD_LOGIC; 
  signal LD_Out_21_GROM : STD_LOGIC; 
  signal LD_Out_23_GROM : STD_LOGIC; 
  signal LD_Out_25_GROM : STD_LOGIC; 
  signal LD_Out_27_GROM : STD_LOGIC; 
  signal LD_Out_29_GROM : STD_LOGIC; 
  signal LD_Out_31_GROM : STD_LOGIC; 
  signal LD_Out_3_X : STD_LOGIC; 
  signal LD_Out_3_FROM : STD_LOGIC; 
  signal LD_Out_3_GROM : STD_LOGIC; 
  signal LD_Out_5_X : STD_LOGIC; 
  signal LD_Out_5_FROM : STD_LOGIC; 
  signal LD_Out_5_GROM : STD_LOGIC; 
  signal LD_Out_7_GROM : STD_LOGIC; 
  signal LD_Out_9_GROM : STD_LOGIC; 
  signal N46985_FROM : STD_LOGIC; 
  signal N46985_GROM : STD_LOGIC; 
  signal N47040_FROM : STD_LOGIC; 
  signal N47040_GROM : STD_LOGIC; 
  signal N50528_FROM : STD_LOGIC; 
  signal N50528_GROM : STD_LOGIC; 
  signal N50552_FROM : STD_LOGIC; 
  signal N50552_GROM : STD_LOGIC; 
  signal N50588_X : STD_LOGIC; 
  signal N50588_FROM : STD_LOGIC; 
  signal N50588_GROM : STD_LOGIC; 
  signal N50592_GROM : STD_LOGIC; 
  signal N50596_GROM : STD_LOGIC; 
  signal N50600_X : STD_LOGIC; 
  signal N50600_FROM : STD_LOGIC; 
  signal N50600_GROM : STD_LOGIC; 
  signal N50903_FROM : STD_LOGIC; 
  signal N50903_GROM : STD_LOGIC; 
  signal PerLBusInterface0_BlkRamWrite_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_BlkRamWrite_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35406 : STD_LOGIC; 
  signal PerLBusInterface0_CalClkEn2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0310 : STD_LOGIC; 
  signal PerLBusInterface0_CalDacActive_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_4_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_0_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_10_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_11_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_12_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_13_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_2_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_3_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_4_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_5_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_6_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_7_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_8_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_9_FROM : STD_LOGIC; 
  signal PerLBusInterface0_CalDacStart_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_CalDacStart_GROM : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_0_FROM : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0249 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0248 : STD_LOGIC; 
  signal PerLBusInterface0_n0245 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0246 : STD_LOGIC; 
  signal PerLBusInterface0_n0243 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0244 : STD_LOGIC; 
  signal PerLBusInterface0_n0241 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0242 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_8_FROM : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0240 : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddrRst_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddrRst_GROM : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus_FROM : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus_GROM : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus_rt : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_53_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_lut3_24 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_cy_140 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_53_LOGIC_ONE : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_53_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_sum_124 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_lut3_25 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_sum_125 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_LOGIC_ONE : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_lut3_26 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_cy_142 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_sum_126 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_lut3_27 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_inst_sum_127 : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_56_GROM : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_56_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_56_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_FocusCtrl_FROM : STD_LOGIC; 
  signal PerLBusInterface0_FocusCtrl_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0264 : STD_LOGIC; 
  signal PerLBusInterface0_FocusWrite_FROM : STD_LOGIC; 
  signal PerLBusInterface0_FocusWrite_GROM : STD_LOGIC; 
  signal PerLBusInterface0_FocusWrite_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ForceBScan_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ForceBScan_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0337 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataStart_rt : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_47_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_18 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_cy_133 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_47_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_47_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_118 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_19 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_119 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_20 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_cy_135 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_120 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_21 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_121 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_22 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_cy_137 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_122 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_lut3_23 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_inst_sum_123 : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_52_GROM : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_52_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_52_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_FROM : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_GROM : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataStart_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_GateDataStart_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I108_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I109_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I110_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I111_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I112_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I113_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I114_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I115_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I116_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I117_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I118_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I119_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I120_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I121_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I122_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I243_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I244_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I245_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I246_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I247_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I248_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I249_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I250_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I251_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I252_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I253_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I254_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I255_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I256_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I257_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I258_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I259_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I260_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I261_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I262_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I263_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I264_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I265_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I266_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I267_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I268_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I269_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I270_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I271_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I272_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I273_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I274_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I275_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I276_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I277_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I278_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I279_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I280_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I281_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I282_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I283_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I284_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I285_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I286_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I287_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I288_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I289_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I290_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I291_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I292_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I293_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I294_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I294_N49951_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I294_N49951_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I295_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I296_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I297_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I298_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I299_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I300_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I301_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I302_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I303_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I304_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I305_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I306_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I307_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I308_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I309_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I310_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I311_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I312_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I313_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I314_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I315_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I316_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I317_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I318_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I319_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I320_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I321_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I322_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I323_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I324_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I325_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I326_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I326_N49951_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I326_N49951_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I327_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I328_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I329_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I330_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I123_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I126_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I127_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I128_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I129_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I130_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I131_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I132_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I140_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I141_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I142_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I143_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I144_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I145_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I146_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I147_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I148_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I149_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I150_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I151_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I152_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I153_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I154_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I155_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I156_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I180_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I180_N4995_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I180_N4995_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I181_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I182_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I183_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I184_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I185_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I186_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I187_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I188_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I189_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I190_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I191_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I192_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I193_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I194_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I195_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I196_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I197_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I198_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I199_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I200_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I201_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I202_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I203_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I204_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I205_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I206_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I207_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I208_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I209_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I210_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I211_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I211_0_IMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_I211_N4995_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I211_N4995_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I212_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I213_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I214_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I215_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I216_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I217_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I218_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I219_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I220_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I221_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I222_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I223_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I224_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I225_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I226_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I227_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I228_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I229_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I230_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I231_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I232_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I233_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I234_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I235_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I236_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I237_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I238_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I239_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I240_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I241_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I242_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I331_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I331_N4995_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I331_N4995_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I332_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I333_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I334_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I335_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I336_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I337_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I338_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I339_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I340_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I341_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I342_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I343_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I344_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I345_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I346_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I347_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I348_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I349_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I350_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I351_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I352_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I353_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I354_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I355_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I356_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I357_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I358_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I359_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I360_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I361_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I361_N49951_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I361_N49951_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I362_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I363_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I364_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I365_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I366_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I367_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I368_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I369_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I370_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I371_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I372_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I373_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I374_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I375_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I376_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I377_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I378_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I379_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I380_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I381_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I382_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I383_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I384_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I385_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I386_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I387_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I388_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I389_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I390_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I391_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I391_N49951_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_I391_N49951_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_I392_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I393_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I394_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I395_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I396_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I397_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I398_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I399_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I400_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I401_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I402_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I403_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I404_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I405_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I406_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I407_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_I408_0_TINV : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_GROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_FROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_GROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_GROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_GROM : STD_LOGIC; 
  signal PerLBusInterface0_n0213 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N50960 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_2_GROM : STD_LOGIC; 
  signal N51024 : STD_LOGIC; 
  signal N51022 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_3_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_2_GROM : STD_LOGIC; 
  signal EncoderMonitor0_BeginShift_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_3_FROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0316 : STD_LOGIC; 
  signal Encoder2In_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N50978 : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N51000 : STD_LOGIC; 
  signal N51029 : STD_LOGIC; 
  signal N51027 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net100_F5MUX : STD_LOGIC; 
  signal N51049 : STD_LOGIC; 
  signal N51047 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net103_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_46 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_45 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net40_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_49 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_48 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net43_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_52 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_51 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net46_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_55 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_54 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net49_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_58 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_57 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net52_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_61 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_60 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net55_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_64 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_63 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net58_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_67 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_66 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net61_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_70 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_69 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net64_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_73 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_72 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net67_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_76 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_75 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net70_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_79 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_78 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net73_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_82 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_81 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net76_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_85 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_84 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net79_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_88 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_87 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net82_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_91 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_90 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net85_F5MUX : STD_LOGIC; 
  signal N51019 : STD_LOGIC; 
  signal N51017 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net88_F5MUX : STD_LOGIC; 
  signal N51034 : STD_LOGIC; 
  signal N51032 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net91_F5MUX : STD_LOGIC; 
  signal N51039 : STD_LOGIC; 
  signal N51037 : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net94_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_N35395_FROM : STD_LOGIC; 
  signal PerLBusInterface0_N35395_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35411_FROM : STD_LOGIC; 
  signal PerLBusInterface0_N35411_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35424_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35448_FROM : STD_LOGIC; 
  signal PerLBusInterface0_N35448_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35455_FROM : STD_LOGIC; 
  signal PerLBusInterface0_N35455_GROM : STD_LOGIC; 
  signal PerLBusInterface0_N35462_FROM : STD_LOGIC; 
  signal PerLBusInterface0_N35462_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_11_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_11_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_13_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_13_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_15_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_15_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_17_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_17_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_19_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_19_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_1_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_21_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_21_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_23_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_23_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_25_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_25_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_27_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_27_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_29_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_29_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_31_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_31_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_3_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_3_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_X : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_7_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_7_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_9_GROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_9_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_47 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_0_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net41 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_0_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_77 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_10_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net71 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_10_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_80 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_11_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net74 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_11_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_83 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_12_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net77 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_12_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_86 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_13_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net80 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_13_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_89 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_14_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net83 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_14_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_92 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_15_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net86 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_15_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_17_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_18_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_19_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_19_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_50 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net44 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_1_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_21_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_22_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_22_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_22_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_23_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_23_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_24_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_24_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_25_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_25_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_26_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_26_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_26_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_27_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_27_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_28_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_28_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_28_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_29_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_29_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_53 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net47 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_2_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_30_FROM : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_30_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_30_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_56 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_3_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net50 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_3_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_59 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_4_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net53 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_4_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_62 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_5_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net56 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_5_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_65 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_6_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net59 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_6_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_68 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_7_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net62 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_7_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_71 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_8_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net65 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_8_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_inst_lut4_74 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_9_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Mrom_n0180_net68 : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_9_CEMUXNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_24_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_23_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_25_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_27_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_29_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_31_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_20_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_20_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_21_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_21_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_21_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_11_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_lut4_42 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_lut4_43 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_cy_72 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_lut4_42 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_lut4_43 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_cy_72 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_63_12_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_63_12_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9_X : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal N51014 : STD_LOGIC; 
  signal N51012 : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_18_F5MUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_18_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_7_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9_Y : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9_GROM : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0324 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_10_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0325 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_14_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_14_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0323 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_15_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0322 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_17_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_17_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0320 : STD_LOGIC; 
  signal PerLBusInterface0_n0318 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_19_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0319 : STD_LOGIC; 
  signal PerLBusInterface0_n0332 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0333 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_20_FROM : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_20_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0317 : STD_LOGIC; 
  signal PerLBusInterface0_n0330 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_4_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0331 : STD_LOGIC; 
  signal PerLBusInterface0_n0328 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0329 : STD_LOGIC; 
  signal PerLBusInterface0_n0326 : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_8_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_n0327 : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_1_FROM : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_FeedbackBit : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0000_inst_lut2_49 : STD_LOGIC; 
  signal PerLBusInterface0_n0000_1_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0000_1_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0000_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0000_inst_cy_111 : STD_LOGIC; 
  signal PerLBusInterface0_n0000_1_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0000_inst_cy_113 : STD_LOGIC; 
  signal PerLBusInterface0_n0000_2_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_n0000_4_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0000_4_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0000_4_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0000_4_XORG : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_7_1_rt : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0000_inst_cy_115 : STD_LOGIC; 
  signal PerLBusInterface0_n0000_4_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0152_inst_lut2_20 : STD_LOGIC; 
  signal PerLBusInterface0_n0152_1_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_1_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_1_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0152_inst_cy_74 : STD_LOGIC; 
  signal PerLBusInterface0_n0152_1_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0152_inst_cy_76 : STD_LOGIC; 
  signal PerLBusInterface0_n0152_2_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_FROM : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_CYMUXG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_LOGIC_ZERO : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_XORG : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_GROM : STD_LOGIC; 
  signal PerLBusInterface0_Madd_n0152_inst_cy_78 : STD_LOGIC; 
  signal PerLBusInterface0_n0152_4_CYINIT : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_8_rt : STD_LOGIC; 
  signal PerLBusInterface0_n0152_6_XORF : STD_LOGIC; 
  signal PerLBusInterface0_n0152_6_CYINIT : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd3_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd6_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd6_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd8_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd8_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayDataDone_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_0_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_1_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_n0025_rt : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_145 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_128 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_291_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_129 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_301_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_147 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_130 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_311_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_131 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_321_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_149 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_132 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_331_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_133 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_341_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_151 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_134 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_35 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_135 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_361_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_153 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_136 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_37 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_137 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_381_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_155 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_138 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_391_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_139 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_401_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_157 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_140 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_411_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_141 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_CYMUXG : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_LOGIC_ONE : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_421_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_cy_159 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_142 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_lut3_431_O : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_inst_sum_143 : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_72_GROM : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_72_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_72_CYINIT : STD_LOGIC; 
  signal TriggerDelay0_OutShifter_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_OutShifter_1_FROM : STD_LOGIC; 
  signal TriggerDelay0_OutShifter_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_0_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_0_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_n0029 : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_1_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_n0028 : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_2_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_n0027 : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_3_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_n0026 : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal RawTrigger : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_2_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_2_GROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_1_FROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_1_GROM : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal TriggerDelay0_n0038_2_GROM : STD_LOGIC; 
  signal pAIN_0_ENABLE : STD_LOGIC; 
  signal pAIN_0_TORGTS : STD_LOGIC; 
  signal pAIN_0_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_2_1 : STD_LOGIC; 
  signal pAIN_0_OD : STD_LOGIC; 
  signal pAIN_0_SRMUXNOT : STD_LOGIC; 
  signal pAIN_1_ENABLE : STD_LOGIC; 
  signal pAIN_1_TORGTS : STD_LOGIC; 
  signal pAIN_1_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_3_1 : STD_LOGIC; 
  signal pAIN_1_OD : STD_LOGIC; 
  signal pAIN_1_SRMUXNOT : STD_LOGIC; 
  signal pAIN_2_ENABLE : STD_LOGIC; 
  signal pAIN_2_TORGTS : STD_LOGIC; 
  signal pAIN_2_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_4_1 : STD_LOGIC; 
  signal pAIN_2_OD : STD_LOGIC; 
  signal pAIN_2_SRMUXNOT : STD_LOGIC; 
  signal pAIN_3_ENABLE : STD_LOGIC; 
  signal pAIN_3_TORGTS : STD_LOGIC; 
  signal pAIN_3_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_5_1 : STD_LOGIC; 
  signal pAIN_3_OD : STD_LOGIC; 
  signal pAIN_3_SRMUXNOT : STD_LOGIC; 
  signal pATOD_RANGE_ENABLE : STD_LOGIC; 
  signal pATOD_RANGE_TORGTS : STD_LOGIC; 
  signal pATOD_RANGE_OUTMUX : STD_LOGIC; 
  signal pAUX_0_ENABLE : STD_LOGIC; 
  signal pAUX_0_TORGTS : STD_LOGIC; 
  signal pAUX_0_OUTMUX : STD_LOGIC; 
  signal pAUX_1_ENABLE : STD_LOGIC; 
  signal pAUX_1_TORGTS : STD_LOGIC; 
  signal pAUX_1_OUTMUX : STD_LOGIC; 
  signal pCAL_0_ENABLE : STD_LOGIC; 
  signal pCAL_0_TORGTS : STD_LOGIC; 
  signal pCAL_0_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_20_1 : STD_LOGIC; 
  signal pCAL_0_OD : STD_LOGIC; 
  signal pCAL_0_SRMUXNOT : STD_LOGIC; 
  signal pCAL_1_ENABLE : STD_LOGIC; 
  signal pCAL_1_TORGTS : STD_LOGIC; 
  signal pCAL_1_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_21_1 : STD_LOGIC; 
  signal pCAL_1_OD : STD_LOGIC; 
  signal pCAL_1_SRMUXNOT : STD_LOGIC; 
  signal pCAL_2_ENABLE : STD_LOGIC; 
  signal pCAL_2_TORGTS : STD_LOGIC; 
  signal pCAL_2_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_22_1 : STD_LOGIC; 
  signal pCAL_2_OD : STD_LOGIC; 
  signal pCAL_2_SRMUXNOT : STD_LOGIC; 
  signal pCalDac_CLK_ENABLE : STD_LOGIC; 
  signal pCalDac_CLK_TORGTS : STD_LOGIC; 
  signal pCalDac_CLK_OUTMUX : STD_LOGIC; 
  signal OFD1_QBUF : STD_LOGIC; 
  signal pCalDac_CLK_OD : STD_LOGIC; 
  signal pCalDac_SDI_ENABLE : STD_LOGIC; 
  signal pCalDac_SDI_TORGTS : STD_LOGIC; 
  signal pCalDac_SDI_OUTMUX : STD_LOGIC; 
  signal OFD0_QBUF : STD_LOGIC; 
  signal pCalDac_SDI_OD : STD_LOGIC; 
  signal pCalDac_nCS_ENABLE : STD_LOGIC; 
  signal pCalDac_nCS_TORGTS : STD_LOGIC; 
  signal pCalDac_nCS_OUTMUX : STD_LOGIC; 
  signal OFD3_QBUF : STD_LOGIC; 
  signal pCalDac_nCS_OD : STD_LOGIC; 
  signal pCalDac_nLD_ENABLE : STD_LOGIC; 
  signal pCalDac_nLD_TORGTS : STD_LOGIC; 
  signal pCalDac_nLD_OUTMUX : STD_LOGIC; 
  signal OFD2_QBUF : STD_LOGIC; 
  signal pCalDac_nLD_OD : STD_LOGIC; 
  signal pDATA_FORMAT_ENABLE : STD_LOGIC; 
  signal pDATA_FORMAT_TORGTS : STD_LOGIC; 
  signal pDATA_FORMAT_OUTMUX : STD_LOGIC; 
  signal pDdsFsk_ENABLE : STD_LOGIC; 
  signal pDdsFsk_TORGTS : STD_LOGIC; 
  signal pDdsFsk_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_19_1 : STD_LOGIC; 
  signal pDdsFsk_OD : STD_LOGIC; 
  signal pDdsFsk_SRMUXNOT : STD_LOGIC; 
  signal pDdsKey_ENABLE : STD_LOGIC; 
  signal pDdsKey_TORGTS : STD_LOGIC; 
  signal pDdsKey_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_18_1 : STD_LOGIC; 
  signal pDdsKey_OD : STD_LOGIC; 
  signal pDdsKey_SRMUXNOT : STD_LOGIC; 
  signal pEncoder0In_0_IDELAY : STD_LOGIC; 
  signal IFD0_DBUF : STD_LOGIC; 
  signal pEncoder0In_1_IDELAY : STD_LOGIC; 
  signal IFD1_DBUF : STD_LOGIC; 
  signal pEncoder1In_0_IDELAY : STD_LOGIC; 
  signal IFD2_DBUF : STD_LOGIC; 
  signal pEncoder1In_1_IDELAY : STD_LOGIC; 
  signal IFD3_DBUF : STD_LOGIC; 
  signal pEncoder2In_0_IDELAY : STD_LOGIC; 
  signal IFD4_DBUF : STD_LOGIC; 
  signal pEncoder2In_1_IDELAY : STD_LOGIC; 
  signal IFD5_DBUF : STD_LOGIC; 
  signal pGAIN_0_ENABLE : STD_LOGIC; 
  signal pGAIN_0_TORGTS : STD_LOGIC; 
  signal pGAIN_0_OUTMUX : STD_LOGIC; 
  signal pGAIN_1_ENABLE : STD_LOGIC; 
  signal pGAIN_1_TORGTS : STD_LOGIC; 
  signal pGAIN_1_OUTMUX : STD_LOGIC; 
  signal pGAIN_2_ENABLE : STD_LOGIC; 
  signal pGAIN_2_TORGTS : STD_LOGIC; 
  signal pGAIN_2_OUTMUX : STD_LOGIC; 
  signal pGAIN_3_ENABLE : STD_LOGIC; 
  signal pGAIN_3_TORGTS : STD_LOGIC; 
  signal pGAIN_3_OUTMUX : STD_LOGIC; 
  signal pGAIN_4_ENABLE : STD_LOGIC; 
  signal pGAIN_4_TORGTS : STD_LOGIC; 
  signal pGAIN_4_OUTMUX : STD_LOGIC; 
  signal pGAIN_5_ENABLE : STD_LOGIC; 
  signal pGAIN_5_TORGTS : STD_LOGIC; 
  signal pGAIN_5_OUTMUX : STD_LOGIC; 
  signal pLA_2_IBUF_8 : STD_LOGIC; 
  signal pLA_3_IBUF_9 : STD_LOGIC; 
  signal pLA_4_IBUF_10 : STD_LOGIC; 
  signal pLA_5_IBUF_11 : STD_LOGIC; 
  signal pLA_6_IBUF_12 : STD_LOGIC; 
  signal pLA_7_IBUF_13 : STD_LOGIC; 
  signal pLD_0_ENABLE : STD_LOGIC; 
  signal pLD_0_TORGTS : STD_LOGIC; 
  signal pLD_0_OUTMUX : STD_LOGIC; 
  signal pLD_0_IDELAY : STD_LOGIC; 
  signal pLD_0_IBUF : STD_LOGIC; 
  signal pLD_0_SRMUXNOT : STD_LOGIC; 
  signal pLD_10_ENABLE : STD_LOGIC; 
  signal pLD_10_TORGTS : STD_LOGIC; 
  signal pLD_10_OUTMUX : STD_LOGIC; 
  signal pLD_10_IDELAY : STD_LOGIC; 
  signal pLD_10_IBUF : STD_LOGIC; 
  signal pLD_10_SRMUXNOT : STD_LOGIC; 
  signal pLD_11_ENABLE : STD_LOGIC; 
  signal pLD_11_TORGTS : STD_LOGIC; 
  signal pLD_11_OUTMUX : STD_LOGIC; 
  signal pLD_11_IDELAY : STD_LOGIC; 
  signal pLD_11_IBUF : STD_LOGIC; 
  signal pLD_11_SRMUXNOT : STD_LOGIC; 
  signal pLD_12_ENABLE : STD_LOGIC; 
  signal pLD_12_TORGTS : STD_LOGIC; 
  signal pLD_12_OUTMUX : STD_LOGIC; 
  signal pLD_12_IDELAY : STD_LOGIC; 
  signal pLD_12_IBUF : STD_LOGIC; 
  signal pLD_12_SRMUXNOT : STD_LOGIC; 
  signal pLD_13_ENABLE : STD_LOGIC; 
  signal pLD_13_TORGTS : STD_LOGIC; 
  signal pLD_13_OUTMUX : STD_LOGIC; 
  signal pLD_13_IDELAY : STD_LOGIC; 
  signal pLD_13_IBUF : STD_LOGIC; 
  signal pLD_13_SRMUXNOT : STD_LOGIC; 
  signal pLD_14_ENABLE : STD_LOGIC; 
  signal pLD_14_TORGTS : STD_LOGIC; 
  signal pLD_14_OUTMUX : STD_LOGIC; 
  signal pLD_14_IDELAY : STD_LOGIC; 
  signal pLD_14_IBUF : STD_LOGIC; 
  signal pLD_14_SRMUXNOT : STD_LOGIC; 
  signal pLD_15_ENABLE : STD_LOGIC; 
  signal pLD_15_TORGTS : STD_LOGIC; 
  signal pLD_15_OUTMUX : STD_LOGIC; 
  signal pLD_15_IDELAY : STD_LOGIC; 
  signal pLD_15_IBUF : STD_LOGIC; 
  signal pLD_15_SRMUXNOT : STD_LOGIC; 
  signal pLD_16_ENABLE : STD_LOGIC; 
  signal pLD_16_TORGTS : STD_LOGIC; 
  signal pLD_16_OUTMUX : STD_LOGIC; 
  signal pLD_16_IDELAY : STD_LOGIC; 
  signal pLD_16_IBUF : STD_LOGIC; 
  signal pLD_16_SRMUXNOT : STD_LOGIC; 
  signal pLD_17_ENABLE : STD_LOGIC; 
  signal pLD_17_TORGTS : STD_LOGIC; 
  signal pLD_17_OUTMUX : STD_LOGIC; 
  signal pLD_17_IDELAY : STD_LOGIC; 
  signal pLD_17_IBUF : STD_LOGIC; 
  signal pLD_17_SRMUXNOT : STD_LOGIC; 
  signal pLD_18_ENABLE : STD_LOGIC; 
  signal pLD_18_TORGTS : STD_LOGIC; 
  signal pLD_18_OUTMUX : STD_LOGIC; 
  signal pLD_18_IDELAY : STD_LOGIC; 
  signal pLD_18_IBUF : STD_LOGIC; 
  signal pLD_18_SRMUXNOT : STD_LOGIC; 
  signal pLD_19_ENABLE : STD_LOGIC; 
  signal pLD_19_TORGTS : STD_LOGIC; 
  signal pLD_19_OUTMUX : STD_LOGIC; 
  signal pLD_19_IDELAY : STD_LOGIC; 
  signal pLD_19_IBUF : STD_LOGIC; 
  signal pLD_19_SRMUXNOT : STD_LOGIC; 
  signal pLD_1_ENABLE : STD_LOGIC; 
  signal pLD_1_TORGTS : STD_LOGIC; 
  signal pLD_1_OUTMUX : STD_LOGIC; 
  signal pLD_1_IDELAY : STD_LOGIC; 
  signal pLD_1_IBUF : STD_LOGIC; 
  signal pLD_1_SRMUXNOT : STD_LOGIC; 
  signal pLD_20_ENABLE : STD_LOGIC; 
  signal pLD_20_TORGTS : STD_LOGIC; 
  signal pLD_20_OUTMUX : STD_LOGIC; 
  signal pLD_20_IDELAY : STD_LOGIC; 
  signal pLD_20_IBUF : STD_LOGIC; 
  signal pLD_20_SRMUXNOT : STD_LOGIC; 
  signal pLD_21_ENABLE : STD_LOGIC; 
  signal pLD_21_TORGTS : STD_LOGIC; 
  signal pLD_21_OUTMUX : STD_LOGIC; 
  signal pLD_21_IDELAY : STD_LOGIC; 
  signal pLD_21_IBUF : STD_LOGIC; 
  signal pLD_21_SRMUXNOT : STD_LOGIC; 
  signal pLD_22_ENABLE : STD_LOGIC; 
  signal pLD_22_TORGTS : STD_LOGIC; 
  signal pLD_22_OUTMUX : STD_LOGIC; 
  signal pLD_22_IDELAY : STD_LOGIC; 
  signal pLD_22_IBUF : STD_LOGIC; 
  signal pLD_22_SRMUXNOT : STD_LOGIC; 
  signal pLD_23_ENABLE : STD_LOGIC; 
  signal pLD_23_TORGTS : STD_LOGIC; 
  signal pLD_23_OUTMUX : STD_LOGIC; 
  signal pLD_23_IDELAY : STD_LOGIC; 
  signal pLD_23_IBUF : STD_LOGIC; 
  signal pLD_23_SRMUXNOT : STD_LOGIC; 
  signal pLD_24_ENABLE : STD_LOGIC; 
  signal pLD_24_TORGTS : STD_LOGIC; 
  signal pLD_24_OUTMUX : STD_LOGIC; 
  signal pLD_24_IDELAY : STD_LOGIC; 
  signal pLD_24_IBUF : STD_LOGIC; 
  signal pLD_24_SRMUXNOT : STD_LOGIC; 
  signal pLD_25_ENABLE : STD_LOGIC; 
  signal pLD_25_TORGTS : STD_LOGIC; 
  signal pLD_25_OUTMUX : STD_LOGIC; 
  signal pLD_25_IDELAY : STD_LOGIC; 
  signal pLD_25_IBUF : STD_LOGIC; 
  signal pLD_25_SRMUXNOT : STD_LOGIC; 
  signal pLD_26_ENABLE : STD_LOGIC; 
  signal pLD_26_TORGTS : STD_LOGIC; 
  signal pLD_26_OUTMUX : STD_LOGIC; 
  signal pLD_26_IDELAY : STD_LOGIC; 
  signal pLD_26_IBUF : STD_LOGIC; 
  signal pLD_26_SRMUXNOT : STD_LOGIC; 
  signal pLD_27_ENABLE : STD_LOGIC; 
  signal pLD_27_TORGTS : STD_LOGIC; 
  signal pLD_27_OUTMUX : STD_LOGIC; 
  signal pLD_27_IDELAY : STD_LOGIC; 
  signal pLD_27_IBUF : STD_LOGIC; 
  signal pLD_27_SRMUXNOT : STD_LOGIC; 
  signal pLD_28_ENABLE : STD_LOGIC; 
  signal pLD_28_TORGTS : STD_LOGIC; 
  signal pLD_28_OUTMUX : STD_LOGIC; 
  signal pLD_28_IDELAY : STD_LOGIC; 
  signal pLD_28_IBUF : STD_LOGIC; 
  signal pLD_28_SRMUXNOT : STD_LOGIC; 
  signal pLD_29_ENABLE : STD_LOGIC; 
  signal pLD_29_TORGTS : STD_LOGIC; 
  signal pLD_29_OUTMUX : STD_LOGIC; 
  signal pLD_29_IDELAY : STD_LOGIC; 
  signal pLD_29_IBUF : STD_LOGIC; 
  signal pLD_29_SRMUXNOT : STD_LOGIC; 
  signal pLD_2_ENABLE : STD_LOGIC; 
  signal pLD_2_TORGTS : STD_LOGIC; 
  signal pLD_2_OUTMUX : STD_LOGIC; 
  signal pLD_2_IDELAY : STD_LOGIC; 
  signal pLD_2_IBUF : STD_LOGIC; 
  signal pLD_2_SRMUXNOT : STD_LOGIC; 
  signal pLD_30_ENABLE : STD_LOGIC; 
  signal pLD_30_TORGTS : STD_LOGIC; 
  signal pLD_30_OUTMUX : STD_LOGIC; 
  signal pLD_30_IDELAY : STD_LOGIC; 
  signal pLD_30_IBUF : STD_LOGIC; 
  signal pLD_30_SRMUXNOT : STD_LOGIC; 
  signal pLD_31_ENABLE : STD_LOGIC; 
  signal pLD_31_TORGTS : STD_LOGIC; 
  signal pLD_31_OUTMUX : STD_LOGIC; 
  signal pLD_31_IDELAY : STD_LOGIC; 
  signal pLD_31_IBUF : STD_LOGIC; 
  signal pLD_31_SRMUXNOT : STD_LOGIC; 
  signal pLD_3_ENABLE : STD_LOGIC; 
  signal pLD_3_TORGTS : STD_LOGIC; 
  signal pLD_3_OUTMUX : STD_LOGIC; 
  signal pLD_3_IDELAY : STD_LOGIC; 
  signal pLD_3_IBUF : STD_LOGIC; 
  signal pLD_3_SRMUXNOT : STD_LOGIC; 
  signal pLD_4_ENABLE : STD_LOGIC; 
  signal pLD_4_TORGTS : STD_LOGIC; 
  signal pLD_4_OUTMUX : STD_LOGIC; 
  signal pLD_4_IDELAY : STD_LOGIC; 
  signal pLD_4_IBUF : STD_LOGIC; 
  signal pLD_4_SRMUXNOT : STD_LOGIC; 
  signal pLD_5_ENABLE : STD_LOGIC; 
  signal pLD_5_TORGTS : STD_LOGIC; 
  signal pLD_5_OUTMUX : STD_LOGIC; 
  signal pLD_5_IDELAY : STD_LOGIC; 
  signal pLD_5_IBUF : STD_LOGIC; 
  signal pLD_5_SRMUXNOT : STD_LOGIC; 
  signal pLD_6_ENABLE : STD_LOGIC; 
  signal pLD_6_TORGTS : STD_LOGIC; 
  signal pLD_6_OUTMUX : STD_LOGIC; 
  signal pLD_6_IDELAY : STD_LOGIC; 
  signal pLD_6_IBUF : STD_LOGIC; 
  signal pLD_6_SRMUXNOT : STD_LOGIC; 
  signal pLD_7_ENABLE : STD_LOGIC; 
  signal pLD_7_TORGTS : STD_LOGIC; 
  signal pLD_7_OUTMUX : STD_LOGIC; 
  signal pLD_7_IDELAY : STD_LOGIC; 
  signal pLD_7_IBUF : STD_LOGIC; 
  signal pLD_7_SRMUXNOT : STD_LOGIC; 
  signal pLD_8_ENABLE : STD_LOGIC; 
  signal pLD_8_TORGTS : STD_LOGIC; 
  signal pLD_8_OUTMUX : STD_LOGIC; 
  signal pLD_8_IDELAY : STD_LOGIC; 
  signal pLD_8_IBUF : STD_LOGIC; 
  signal pLD_8_SRMUXNOT : STD_LOGIC; 
  signal pLD_9_ENABLE : STD_LOGIC; 
  signal pLD_9_TORGTS : STD_LOGIC; 
  signal pLD_9_OUTMUX : STD_LOGIC; 
  signal pLD_9_IDELAY : STD_LOGIC; 
  signal pLD_9_IBUF : STD_LOGIC; 
  signal pLD_9_SRMUXNOT : STD_LOGIC; 
  signal pLED_D8_ENABLE : STD_LOGIC; 
  signal pLED_D8_TORGTS : STD_LOGIC; 
  signal pLED_D8_OUTMUX : STD_LOGIC; 
  signal pLED_D8_ODNOT : STD_LOGIC; 
  signal pLED_D9_ENABLE : STD_LOGIC; 
  signal pLED_D9_TORGTS : STD_LOGIC; 
  signal pLED_D9_OUTMUX : STD_LOGIC; 
  signal pLED_D9_LOGIC_ONE : STD_LOGIC; 
  signal pLWnR_IDELAY : STD_LOGIC; 
  signal pLWnR_IBUF : STD_LOGIC; 
  signal pLWnR_SRMUXNOT : STD_LOGIC; 
  signal pPIO_10_ENABLE : STD_LOGIC; 
  signal pPIO_10_TORGTS : STD_LOGIC; 
  signal pPIO_10_OUTMUX : STD_LOGIC; 
  signal pPIO_10_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_10 : STD_LOGIC; 
  signal pPIO_10_OD : STD_LOGIC; 
  signal pPIO_10_IBUF : STD_LOGIC; 
  signal pPIO_10_SRMUXNOT : STD_LOGIC; 
  signal pPIO_11_ENABLE : STD_LOGIC; 
  signal pPIO_11_TORGTS : STD_LOGIC; 
  signal pPIO_11_OUTMUX : STD_LOGIC; 
  signal pPIO_11_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_11 : STD_LOGIC; 
  signal pPIO_11_OD : STD_LOGIC; 
  signal pPIO_11_IBUF : STD_LOGIC; 
  signal pPIO_11_SRMUXNOT : STD_LOGIC; 
  signal pPIO_12_ENABLE : STD_LOGIC; 
  signal pPIO_12_TORGTS : STD_LOGIC; 
  signal pPIO_12_OUTMUX : STD_LOGIC; 
  signal pPIO_12_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_12 : STD_LOGIC; 
  signal pPIO_12_OD : STD_LOGIC; 
  signal pPIO_12_IBUF : STD_LOGIC; 
  signal pPIO_12_SRMUXNOT : STD_LOGIC; 
  signal pPIO_13_ENABLE : STD_LOGIC; 
  signal pPIO_13_TORGTS : STD_LOGIC; 
  signal pPIO_13_OUTMUX : STD_LOGIC; 
  signal pPIO_13_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_13 : STD_LOGIC; 
  signal pPIO_13_OD : STD_LOGIC; 
  signal pPIO_13_IBUF : STD_LOGIC; 
  signal pPIO_13_SRMUXNOT : STD_LOGIC; 
  signal pPIO_14_ENABLE : STD_LOGIC; 
  signal pPIO_14_TORGTS : STD_LOGIC; 
  signal pPIO_14_OUTMUX : STD_LOGIC; 
  signal pPIO_14_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_14 : STD_LOGIC; 
  signal pPIO_14_OD : STD_LOGIC; 
  signal pPIO_14_IBUF : STD_LOGIC; 
  signal pPIO_14_SRMUXNOT : STD_LOGIC; 
  signal pPIO_15_ENABLE : STD_LOGIC; 
  signal pPIO_15_TORGTS : STD_LOGIC; 
  signal pPIO_15_OUTMUX : STD_LOGIC; 
  signal pPIO_15_TDATANOT : STD_LOGIC; 
  signal pPIO_15_IBUF : STD_LOGIC; 
  signal pPIO_16_ENABLE : STD_LOGIC; 
  signal pPIO_16_TORGTS : STD_LOGIC; 
  signal pPIO_16_OUTMUX : STD_LOGIC; 
  signal pPIO_16_TDATANOT : STD_LOGIC; 
  signal pPIO_16_IBUF : STD_LOGIC; 
  signal pPIO_17_ENABLE : STD_LOGIC; 
  signal pPIO_17_TORGTS : STD_LOGIC; 
  signal pPIO_17_OUTMUX : STD_LOGIC; 
  signal pPIO_17_TDATANOT : STD_LOGIC; 
  signal pPIO_17_IBUF : STD_LOGIC; 
  signal pPIO_18_ENABLE : STD_LOGIC; 
  signal pPIO_18_TORGTS : STD_LOGIC; 
  signal pPIO_18_OUTMUX : STD_LOGIC; 
  signal pPIO_18_TDATANOT : STD_LOGIC; 
  signal pPIO_18_IBUF : STD_LOGIC; 
  signal pPIO_19_ENABLE : STD_LOGIC; 
  signal pPIO_19_TORGTS : STD_LOGIC; 
  signal pPIO_19_OUTMUX : STD_LOGIC; 
  signal pPIO_19_TDATANOT : STD_LOGIC; 
  signal pPIO_19_IBUF : STD_LOGIC; 
  signal pPIO_20_ENABLE : STD_LOGIC; 
  signal pPIO_20_TORGTS : STD_LOGIC; 
  signal pPIO_20_OUTMUX : STD_LOGIC; 
  signal pPIO_20_TDATANOT : STD_LOGIC; 
  signal pPIO_20_IBUF : STD_LOGIC; 
  signal pPIO_21_ENABLE : STD_LOGIC; 
  signal pPIO_21_TORGTS : STD_LOGIC; 
  signal pPIO_21_OUTMUX : STD_LOGIC; 
  signal pPIO_21_TDATANOT : STD_LOGIC; 
  signal pPIO_21_IBUF : STD_LOGIC; 
  signal pPIO_22_ENABLE : STD_LOGIC; 
  signal pPIO_22_TORGTS : STD_LOGIC; 
  signal pPIO_22_OUTMUX : STD_LOGIC; 
  signal pPIO_22_TDATANOT : STD_LOGIC; 
  signal pPIO_22_IBUF : STD_LOGIC; 
  signal pPIO_23_ENABLE : STD_LOGIC; 
  signal pPIO_23_TORGTS : STD_LOGIC; 
  signal pPIO_23_OUTMUX : STD_LOGIC; 
  signal pPIO_23_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_23 : STD_LOGIC; 
  signal pPIO_23_OD : STD_LOGIC; 
  signal pPIO_23_IBUF : STD_LOGIC; 
  signal pPIO_23_SRMUXNOT : STD_LOGIC; 
  signal pPIO_24_ENABLE : STD_LOGIC; 
  signal pPIO_24_TORGTS : STD_LOGIC; 
  signal pPIO_24_OUTMUX : STD_LOGIC; 
  signal pPIO_24_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_24 : STD_LOGIC; 
  signal pPIO_24_OD : STD_LOGIC; 
  signal pPIO_24_IBUF : STD_LOGIC; 
  signal pPIO_24_SRMUXNOT : STD_LOGIC; 
  signal pPIO_25_ENABLE : STD_LOGIC; 
  signal pPIO_25_TORGTS : STD_LOGIC; 
  signal pPIO_25_OUTMUX : STD_LOGIC; 
  signal pPIO_25_TDATANOT : STD_LOGIC; 
  signal pPIO_25_IBUF : STD_LOGIC; 
  signal pPIO_26_ENABLE : STD_LOGIC; 
  signal pPIO_26_TORGTS : STD_LOGIC; 
  signal pPIO_26_OUTMUX : STD_LOGIC; 
  signal pPIO_26_TDATANOT : STD_LOGIC; 
  signal pPIO_26_IBUF : STD_LOGIC; 
  signal pPIO_27_ENABLE : STD_LOGIC; 
  signal pPIO_27_TORGTS : STD_LOGIC; 
  signal pPIO_27_OUTMUX : STD_LOGIC; 
  signal pPIO_27_TDATANOT : STD_LOGIC; 
  signal pPIO_27_IBUF : STD_LOGIC; 
  signal pPIO_28_ENABLE : STD_LOGIC; 
  signal pPIO_28_TORGTS : STD_LOGIC; 
  signal pPIO_28_OUTMUX : STD_LOGIC; 
  signal pPIO_28_TDATANOT : STD_LOGIC; 
  signal pPIO_28_IBUF : STD_LOGIC; 
  signal pPIO_29_ENABLE : STD_LOGIC; 
  signal pPIO_29_TORGTS : STD_LOGIC; 
  signal pPIO_29_OUTMUX : STD_LOGIC; 
  signal pPIO_29_TDATANOT : STD_LOGIC; 
  signal pPIO_29_IBUF : STD_LOGIC; 
  signal pPIO_2_ENABLE : STD_LOGIC; 
  signal pPIO_2_TORGTS : STD_LOGIC; 
  signal pPIO_2_OUTMUX : STD_LOGIC; 
  signal pPIO_2_TDATANOT : STD_LOGIC; 
  signal pPIO_2_IBUF : STD_LOGIC; 
  signal pPIO_30_ENABLE : STD_LOGIC; 
  signal pPIO_30_TORGTS : STD_LOGIC; 
  signal pPIO_30_OUTMUX : STD_LOGIC; 
  signal pPIO_30_TDATANOT : STD_LOGIC; 
  signal pPIO_30_IBUF : STD_LOGIC; 
  signal pPIO_31_ENABLE : STD_LOGIC; 
  signal pPIO_31_TORGTS : STD_LOGIC; 
  signal pPIO_31_OUTMUX : STD_LOGIC; 
  signal pPIO_31_TDATANOT : STD_LOGIC; 
  signal pPIO_31_IBUF : STD_LOGIC; 
  signal pPIO_3_ENABLE : STD_LOGIC; 
  signal pPIO_3_TORGTS : STD_LOGIC; 
  signal pPIO_3_OUTMUX : STD_LOGIC; 
  signal pPIO_3_TDATANOT : STD_LOGIC; 
  signal pPIO_3_IBUF : STD_LOGIC; 
  signal pPIO_4_ENABLE : STD_LOGIC; 
  signal pPIO_4_TORGTS : STD_LOGIC; 
  signal pPIO_4_OUTMUX : STD_LOGIC; 
  signal pPIO_4_TDATANOT : STD_LOGIC; 
  signal pPIO_4_IBUF : STD_LOGIC; 
  signal pPIO_5_ENABLE : STD_LOGIC; 
  signal pPIO_5_TORGTS : STD_LOGIC; 
  signal pPIO_5_OUTMUX : STD_LOGIC; 
  signal pPIO_5_TDATANOT : STD_LOGIC; 
  signal pPIO_5_IBUF : STD_LOGIC; 
  signal pPIO_6_ENABLE : STD_LOGIC; 
  signal pPIO_6_TORGTS : STD_LOGIC; 
  signal pPIO_6_OUTMUX : STD_LOGIC; 
  signal pPIO_6_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_6 : STD_LOGIC; 
  signal pPIO_6_OD : STD_LOGIC; 
  signal pPIO_6_IBUF : STD_LOGIC; 
  signal pPIO_6_SRMUXNOT : STD_LOGIC; 
  signal pPIO_7_ENABLE : STD_LOGIC; 
  signal pPIO_7_TORGTS : STD_LOGIC; 
  signal pPIO_7_OUTMUX : STD_LOGIC; 
  signal pPIO_7_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_7 : STD_LOGIC; 
  signal pPIO_7_OD : STD_LOGIC; 
  signal pPIO_7_IBUF : STD_LOGIC; 
  signal pPIO_7_SRMUXNOT : STD_LOGIC; 
  signal pPIO_8_ENABLE : STD_LOGIC; 
  signal pPIO_8_TORGTS : STD_LOGIC; 
  signal pPIO_8_OUTMUX : STD_LOGIC; 
  signal pPIO_8_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_8 : STD_LOGIC; 
  signal pPIO_8_OD : STD_LOGIC; 
  signal pPIO_8_IBUF : STD_LOGIC; 
  signal pPIO_8_SRMUXNOT : STD_LOGIC; 
  signal pPIO_9_ENABLE : STD_LOGIC; 
  signal pPIO_9_TORGTS : STD_LOGIC; 
  signal pPIO_9_OUTMUX : STD_LOGIC; 
  signal pPIO_9_TDATANOT : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_17_9 : STD_LOGIC; 
  signal pPIO_9_OD : STD_LOGIC; 
  signal pPIO_9_IBUF : STD_LOGIC; 
  signal pPIO_9_SRMUXNOT : STD_LOGIC; 
  signal pPORT_FORMAT_ENABLE : STD_LOGIC; 
  signal pPORT_FORMAT_TORGTS : STD_LOGIC; 
  signal pPORT_FORMAT_OUTMUX : STD_LOGIC; 
  signal pProbeAper_0_ENABLE : STD_LOGIC; 
  signal pProbeAper_0_TORGTS : STD_LOGIC; 
  signal pProbeAper_0_OUTMUX : STD_LOGIC; 
  signal pProbeAper_1_ENABLE : STD_LOGIC; 
  signal pProbeAper_1_TORGTS : STD_LOGIC; 
  signal pProbeAper_1_OUTMUX : STD_LOGIC; 
  signal pProbeAper_1_OBUF_FROM : STD_LOGIC; 
  signal pProbeAper_1_OBUF_GROM : STD_LOGIC; 
  signal pProbeDClk_ENABLE : STD_LOGIC; 
  signal pProbeDClk_TORGTS : STD_LOGIC; 
  signal pProbeDClk_OUTMUX : STD_LOGIC; 
  signal pProbeDSel_ENABLE : STD_LOGIC; 
  signal pProbeDSel_TORGTS : STD_LOGIC; 
  signal pProbeDSel_OUTMUX : STD_LOGIC; 
  signal pProbeData_0_ENABLE : STD_LOGIC; 
  signal pProbeData_0_TORGTS : STD_LOGIC; 
  signal pProbeData_0_OUTMUX : STD_LOGIC; 
  signal pProbeData_1_ENABLE : STD_LOGIC; 
  signal pProbeData_1_TORGTS : STD_LOGIC; 
  signal pProbeData_1_OUTMUX : STD_LOGIC; 
  signal pProbeData_2_ENABLE : STD_LOGIC; 
  signal pProbeData_2_TORGTS : STD_LOGIC; 
  signal pProbeData_2_OUTMUX : STD_LOGIC; 
  signal pProbeData_3_ENABLE : STD_LOGIC; 
  signal pProbeData_3_TORGTS : STD_LOGIC; 
  signal pProbeData_3_OUTMUX : STD_LOGIC; 
  signal pProbeData_4_ENABLE : STD_LOGIC; 
  signal pProbeData_4_TORGTS : STD_LOGIC; 
  signal pProbeData_4_OUTMUX : STD_LOGIC; 
  signal pProbeData_5_ENABLE : STD_LOGIC; 
  signal pProbeData_5_TORGTS : STD_LOGIC; 
  signal pProbeData_5_OUTMUX : STD_LOGIC; 
  signal pProbeData_6_ENABLE : STD_LOGIC; 
  signal pProbeData_6_TORGTS : STD_LOGIC; 
  signal pProbeData_6_OUTMUX : STD_LOGIC; 
  signal pProbeData_7_ENABLE : STD_LOGIC; 
  signal pProbeData_7_TORGTS : STD_LOGIC; 
  signal pProbeData_7_OUTMUX : STD_LOGIC; 
  signal pProbeData_4_OBUF_FROM : STD_LOGIC; 
  signal pProbeData_4_OBUF_GROM : STD_LOGIC; 
  signal pProbeData_5_OBUF_FROM : STD_LOGIC; 
  signal pProbeData_5_OBUF_GROM : STD_LOGIC; 
  signal pProbeData_6_OBUF_FROM : STD_LOGIC; 
  signal pProbeData_6_OBUF_GROM : STD_LOGIC; 
  signal pProbeData_7_OBUF_FROM : STD_LOGIC; 
  signal pProbeData_7_OBUF_GROM : STD_LOGIC; 
  signal pProbeSense_IBUF_14 : STD_LOGIC; 
  signal pProbeTx_ENABLE : STD_LOGIC; 
  signal pProbeTx_TORGTS : STD_LOGIC; 
  signal pProbeTx_OUTMUX : STD_LOGIC; 
  signal pSEL_1M_50R_ENABLE : STD_LOGIC; 
  signal pSEL_1M_50R_TORGTS : STD_LOGIC; 
  signal pSEL_1M_50R_OUTMUX : STD_LOGIC; 
  signal pSEL_AC_DC_ENABLE : STD_LOGIC; 
  signal pSEL_AC_DC_TORGTS : STD_LOGIC; 
  signal pSEL_AC_DC_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_0_1 : STD_LOGIC; 
  signal pSEL_AC_DC_OD : STD_LOGIC; 
  signal pSEL_AC_DC_SRMUXNOT : STD_LOGIC; 
  signal pSENSE_ENABLE : STD_LOGIC; 
  signal pSENSE_TORGTS : STD_LOGIC; 
  signal pSENSE_OUTMUX : STD_LOGIC; 
  signal pSENSE_LOGIC_ONE : STD_LOGIC; 
  signal pSENSE_TDATANOT : STD_LOGIC; 
  signal pZ0_IBUF_15 : STD_LOGIC; 
  signal pZ1_ENABLE : STD_LOGIC; 
  signal pZ1_TORGTS : STD_LOGIC; 
  signal pZ1_OUTMUX : STD_LOGIC; 
  signal OFD4_QBUF : STD_LOGIC; 
  signal pZ1_OD : STD_LOGIC; 
  signal pZ10_ENABLE : STD_LOGIC; 
  signal pZ10_TORGTS : STD_LOGIC; 
  signal pZ10_OUTMUX : STD_LOGIC; 
  signal pZ10_OD : STD_LOGIC; 
  signal pZ10_SRMUXNOT : STD_LOGIC; 
  signal pZ11_ENABLE : STD_LOGIC; 
  signal pZ11_TORGTS : STD_LOGIC; 
  signal pZ11_OUTMUX : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_16_1 : STD_LOGIC; 
  signal pZ11_OD : STD_LOGIC; 
  signal pZ11_SRMUXNOT : STD_LOGIC; 
  signal pZ2_ENABLE : STD_LOGIC; 
  signal pZ2_TORGTS : STD_LOGIC; 
  signal pZ2_OUTMUX : STD_LOGIC; 
  signal OFD5_QBUF : STD_LOGIC; 
  signal pZ2_OD : STD_LOGIC; 
  signal pZ3_ENABLE : STD_LOGIC; 
  signal pZ3_TORGTS : STD_LOGIC; 
  signal pZ3_OUTMUX : STD_LOGIC; 
  signal OFD6_QBUF : STD_LOGIC; 
  signal pZ3_OD : STD_LOGIC; 
  signal pZ4_ENABLE : STD_LOGIC; 
  signal pZ4_TORGTS : STD_LOGIC; 
  signal pZ4_OUTMUX : STD_LOGIC; 
  signal OFD7_QBUF : STD_LOGIC; 
  signal pZ4_OD : STD_LOGIC; 
  signal pZ5_ENABLE : STD_LOGIC; 
  signal pZ5_TORGTS : STD_LOGIC; 
  signal pZ5_OUTMUX : STD_LOGIC; 
  signal OFD8_QBUF : STD_LOGIC; 
  signal pZ5_OD : STD_LOGIC; 
  signal pZ6_ENABLE : STD_LOGIC; 
  signal pZ6_TORGTS : STD_LOGIC; 
  signal pZ6_OUTMUX : STD_LOGIC; 
  signal OFD9_QBUF : STD_LOGIC; 
  signal pZ6_OD : STD_LOGIC; 
  signal pZ7_ENABLE : STD_LOGIC; 
  signal pZ7_TORGTS : STD_LOGIC; 
  signal pZ7_OUTMUX : STD_LOGIC; 
  signal OFD10_QBUF : STD_LOGIC; 
  signal pZ7_OD : STD_LOGIC; 
  signal pZ9_IBUF_16 : STD_LOGIC; 
  signal pnFpgaCs_IBUF_17 : STD_LOGIC; 
  signal pnLReset_IBUF_18 : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_29_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_149_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_150_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_143_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_147_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_147_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_149_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_145_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_157_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_151_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_159_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_155_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_157_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_153_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_155_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_141_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_143_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_13_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_141_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_137_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_13_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_139_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_133_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_125_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_129_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_129_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_131_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_127_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_139_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_133_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_135_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_131_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_137_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_115_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_117_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_113_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_115_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_111_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_11_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_121_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_117_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_119_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_123_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_11_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_127_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_121_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_123_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_125_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_101_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_103_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_113_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_109_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_111_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_107_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_109_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_105_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_107_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_103_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_IncHysterisis_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_0_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_2_FFY_SET : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_2_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_2_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_1_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_1_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_LastInputs_0_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_4_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_2_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_6_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncInc_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncDec_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncDec_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncDec_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_0_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_1_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_2_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_0_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_2_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_0_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncInc_1_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncoderReset_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_IncHysterisis_FFY_SET : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_4_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_LatchData_6_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_38_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_36_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_34_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_8_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_38_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_29_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_26_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_30_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_32_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_28_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_33_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_22_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_89_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_24_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_21_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_61_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_20_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_119_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_105_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_18_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_79_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_12_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_16_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_6_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_14_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_38_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_165_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_15_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SelEncReset_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_101_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_38_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_2_10_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_145_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_135_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_8_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_36_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_34_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_153_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_16_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_32_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_30_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_67_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_85_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_26_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_28_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_20_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_24_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_22_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_10_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_18_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_16_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_14_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_1_12_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_38_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFY_SET : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_36_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_8_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFY_SET : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_38_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_22_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_6_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_28_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_32_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_26_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataSel_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_34_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_30_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_31_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_24_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_12_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_18_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_16_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_14_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_20_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEn2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEn2_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_EncCounts_0_10_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ClkEnCount_0_FFX_RST : STD_LOGIC; 
  signal Encoder0In_1_FFY_RST : STD_LOGIC; 
  signal Encoder1In_1_FFY_RST : STD_LOGIC; 
  signal Encoder0In_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_7_FFY_RST : STD_LOGIC; 
  signal Encoder2In_1_FFY_RST : STD_LOGIC; 
  signal Encoder1In_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_24_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_21_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_23_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_31_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_20_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_14_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_2_FFY_SET : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_177_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_175_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_179_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_181_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_179_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_183_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_175_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_171_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_173_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_171_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_173_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_177_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_18_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_187_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_189_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_185_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_187_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_183_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_185_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_181_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_27_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_31_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_BScanActive_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_BScanActive_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_BScanTrigger_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_BScanTrigger_FROM : STD_LOGIC; 
  signal BScanCtrl0_BScanTrigger_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0063 : STD_LOGIC; 
  signal BScanCtrl0_ClkEn_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_ClkEn_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0037 : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount2_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount2_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount2_FROM : STD_LOGIC; 
  signal BScanCtrl0_IncRxCount2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0034 : STD_LOGIC; 
  signal BScanCtrl0_IncScanCount_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_IncScanCount_FROM : STD_LOGIC; 
  signal BScanCtrl0_IncScanCount_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0024 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_lut4_40 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_cy_71_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_lut4_41 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_cy_70 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ONE : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_lut4_40 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_cy_71_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_lut4_41 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_cy_70 : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ONE : STD_LOGIC; 
  signal BScanCtrl0_RepCount_11_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_11_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_11_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_11_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_10_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_13_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_13_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_13_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_13_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_12_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_15_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_15_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_15_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_15_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_14_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_16_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_43 : STD_LOGIC; 
  signal BScanCtrl0_RepCount_16_XORF : STD_LOGIC; 
  signal BScanCtrl0_RepCount_16_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_RepCount_16_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_16_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_1_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_1_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_1_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_0_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_3_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_3_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_3_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_2_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_5_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_5_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_5_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_4_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_7_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_7_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_7_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_7_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_6_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_9_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RepCount_9_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_9_1_O : STD_LOGIC; 
  signal BScanCtrl0_RepCount_9_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_Mmux_n0023_Result_8_1_O : STD_LOGIC; 
  signal BScanCtrl0_RxActive_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RxActive_X : STD_LOGIC; 
  signal BScanCtrl0_RxActive_FROM : STD_LOGIC; 
  signal BScanCtrl0_RxActive_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0031 : STD_LOGIC; 
  signal BScanCtrl0_RxCount_1_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_1_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_RxCount_3_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_3_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_RxCount_5_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_5_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_RxCount_6_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_RxCount_6_FROM : STD_LOGIC; 
  signal BScanCtrl0_RxCount_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_40_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_BScanTrigger_rt : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_40_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_11 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_cy_98 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_40_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_40_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_84 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_12 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_85 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_13 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_cy_100 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_41_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_86 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_14 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_87 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_15 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_cy_102 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_43_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_88 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_16 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_89 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_lut3_17 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_cy_104 : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_45_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_ScanCount_inst_sum_90 : STD_LOGIC; 
  signal BScanCtrl0_n0045_FROM : STD_LOGIC; 
  signal BScanCtrl0_n0045_GROM : STD_LOGIC; 
  signal BScanCtrl0_n004526_O_FROM : STD_LOGIC; 
  signal BScanCtrl0_n004526_O_GROM : STD_LOGIC; 
  signal BScanCtrl0_n004553_O_FROM : STD_LOGIC; 
  signal BScanCtrl0_n004553_O_GROM : STD_LOGIC; 
  signal BScanCtrl0_Madd_n0048_inst_lut2_20 : STD_LOGIC; 
  signal BScanCtrl0_n0048_1_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0048_1_XORG : STD_LOGIC; 
  signal BScanCtrl0_n0048_1_GROM : STD_LOGIC; 
  signal BScanCtrl0_Madd_n0048_inst_cy_74 : STD_LOGIC; 
  signal BScanCtrl0_n0048_1_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_FROM : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_XORG : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_GROM : STD_LOGIC; 
  signal BScanCtrl0_Madd_n0048_inst_cy_76 : STD_LOGIC; 
  signal BScanCtrl0_n0048_2_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_FROM : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_LOGIC_ZERO : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_XORG : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_GROM : STD_LOGIC; 
  signal BScanCtrl0_Madd_n0048_inst_cy_78 : STD_LOGIC; 
  signal BScanCtrl0_n0048_4_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_RxCount_6_rt : STD_LOGIC; 
  signal BScanCtrl0_n0048_6_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0048_6_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_FROM : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_28 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_81 : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_n0088_0_LOGIC_ONE : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_37 : STD_LOGIC; 
  signal BScanCtrl0_n0088_10_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_10_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_10_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_38 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_91 : STD_LOGIC; 
  signal BScanCtrl0_n0088_10_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_39 : STD_LOGIC; 
  signal BScanCtrl0_n0088_12_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_12_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_12_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_40 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_93 : STD_LOGIC; 
  signal BScanCtrl0_n0088_12_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_41 : STD_LOGIC; 
  signal BScanCtrl0_n0088_14_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_14_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_14_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_42 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_95 : STD_LOGIC; 
  signal BScanCtrl0_n0088_14_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_29 : STD_LOGIC; 
  signal BScanCtrl0_n0088_2_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_2_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_2_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_30 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_83 : STD_LOGIC; 
  signal BScanCtrl0_n0088_2_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_31 : STD_LOGIC; 
  signal BScanCtrl0_n0088_4_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_4_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_4_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_32 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_85 : STD_LOGIC; 
  signal BScanCtrl0_n0088_4_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_33 : STD_LOGIC; 
  signal BScanCtrl0_n0088_6_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_6_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_6_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_34 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_87 : STD_LOGIC; 
  signal BScanCtrl0_n0088_6_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_35 : STD_LOGIC; 
  signal BScanCtrl0_n0088_8_XORF : STD_LOGIC; 
  signal BScanCtrl0_n0088_8_CYMUXG : STD_LOGIC; 
  signal BScanCtrl0_n0088_8_XORG : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_lut2_36 : STD_LOGIC; 
  signal BScanCtrl0_Msub_n0044_inst_cy_89 : STD_LOGIC; 
  signal BScanCtrl0_n0088_8_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_pTriggerOut_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_pTriggerOut_FROM : STD_LOGIC; 
  signal BScanCtrl0_pTriggerOut_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_n0035 : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_1_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_1_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_X : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_FROM : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_Y : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_GROM : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_3_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_5_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_5_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_5_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_6_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_pTxCount_6_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_1_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_1_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_1_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal DoBScan : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_2_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_2_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_2_FROM : STD_LOGIC; 
  signal BScanCtrl0_vBScanTrigger_2_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal FocusUnitCtrl0_n0048 : STD_LOGIC; 
  signal BScanCtrl0_vCount_1_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_vCount_1_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_vCount_2_FFY_RST : STD_LOGIC; 
  signal BScanCtrl0_vRxCountDone_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_vRxCountDone_FROM : STD_LOGIC; 
  signal BScanCtrl0_n0041_rt : STD_LOGIC; 
  signal BScanCtrl0_vRxCountDone_CYINIT : STD_LOGIC; 
  signal BScanCtrl0_vScanCountDone_FFX_RST : STD_LOGIC; 
  signal BScanCtrl0_vScanCountDone_FROM : STD_LOGIC; 
  signal BScanCtrl0_vScanCountDone_GROM : STD_LOGIC; 
  signal BScanCtrl0_vScanCountDone_SRMUX_OUTPUTNOT : STD_LOGIC; 
  signal CHOICE269_GROM : STD_LOGIC; 
  signal CHOICE277_GROM : STD_LOGIC; 
  signal CHOICE284_GROM : STD_LOGIC; 
  signal CHOICE367_X : STD_LOGIC; 
  signal CHOICE367_FROM : STD_LOGIC; 
  signal CHOICE367_GROM : STD_LOGIC; 
  signal CHOICE374_FROM : STD_LOGIC; 
  signal CHOICE374_GROM : STD_LOGIC; 
  signal CHOICE488_GROM : STD_LOGIC; 
  signal CHOICE496_X : STD_LOGIC; 
  signal CHOICE496_FROM : STD_LOGIC; 
  signal CHOICE496_GROM : STD_LOGIC; 
  signal CHOICE503_GROM : STD_LOGIC; 
  signal CHOICE519_X : STD_LOGIC; 
  signal CHOICE519_FROM : STD_LOGIC; 
  signal CHOICE519_GROM : STD_LOGIC; 
  signal CHOICE527_GROM : STD_LOGIC; 
  signal CHOICE534_GROM : STD_LOGIC; 
  signal CHOICE550_GROM : STD_LOGIC; 
  signal CHOICE558_GROM : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_23_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_25_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_21_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_23_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_27_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_25_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_19_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_191_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_18_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_189_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_191_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_87_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_8_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_89_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_91_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_8_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_93_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_91_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_95_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_93_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_97_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_35_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_31_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_33_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_37_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_35_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_39_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_37_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_3_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_39_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_41_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_49_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_51_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_53_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_51_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_55_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_53_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_57_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_55_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_59_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_57_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_10_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_11_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_12_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_13_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_14_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_15_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_59_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_63_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_61_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_64_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_63_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_65_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_69_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_77_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_81_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_79_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_83_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_81_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_87_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_83_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_85_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_99_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_95_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_97_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_99_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_SerialResults_9_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_0_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_7_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_2_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_4_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_4_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_0_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_6_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_2_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_3_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_4_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_5_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_6_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_7_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_3_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValAddr_3_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValInc_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValRst_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_DelayValRst_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_ProbeTx_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_Rx_nTx_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_1_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_3_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftResults_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_ShiftCount_5_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_8_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_TrigCount_9_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_0_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeCtrl_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_BlkRamWrite_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalClkEn2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacActive_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalClkEn2_FFX_RST : STD_LOGIC; 
  signal EncoderMonitor0_pBScanTrigger_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOut_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_ProbeTx_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFY_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFX_SET : STD_LOGIC; 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FFY_SET : STD_LOGIC; 
  signal EncoderMonitor0_pSerialOutEn_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMax_FFY_RST : STD_LOGIC; 
  signal EncoderMonitor0_vTrigCountMax_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd10_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd10_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd11_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd3_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_CtrlState_FFd4_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_6_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_7_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_vLastTrigger_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_vLastTrigger_FFX_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeDClock_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_0_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_1_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_2_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_3_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_5_FFY_RST : STD_LOGIC; 
  signal FocusUnitCtrl0_pProbeData_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacCount_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_0_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_10_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_8_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacStart_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_0_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_12_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_CalDacShiftReg_6_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddr_8_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DelayValAddrRst_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_53_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusWrite_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ForceBScan_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_47_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_DoFocus_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_56_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusCount_54_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_FocusCtrl_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_48_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_52_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataCount_50_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataStart_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_GateDataOut_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_4_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_6_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_IntAddr_2_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_30_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_6_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_8_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_1_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_13_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_23_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_23_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_25_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_27_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_31_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_29_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_31_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_0_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegData_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_16_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_24_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_26_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_28_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_10_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_12_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_14_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_18_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_18_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_22_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_23_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_6_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_8_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_ReadRegMask_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_10_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_10_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_19_4_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_15_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_23_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_3_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_7_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_0_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_31_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_25_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_27_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_29_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_31_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_31_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_2_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_25_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_27_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_29_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_14_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_17_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_17_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_18_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_5_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_20_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_20_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_15_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_16_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_15_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_29_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_31_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_31_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_1_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_8_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_63_12_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_17_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_21_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_23_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_23_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_25_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_18_27_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_7_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_9_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_10_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_9_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_10_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_5_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_21_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_23_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_23_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_25_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_25_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_27_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_27_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_29_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_29_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_31_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_20_31_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_11_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_3_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_4_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_11_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_13_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_13_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_14_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_3_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_5_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_7_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_6_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_17_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_19_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_19_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_4_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_6_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_4_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_66_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_68_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_3_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_5_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_7_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_7_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegBank_7_9_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_10_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_15_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_10_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_6_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_8_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_RegWriteEn_8_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFX_SET : STD_LOGIC; 
  signal PerLBusInterface0_StrobeExtender0_pStrobeOut_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nCS_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_nLD_FFY_SET : STD_LOGIC; 
  signal PerLBusInterface0_pEncoderReset_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pEncoderReset_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_pEncoderReset_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataEn_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataOut_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_68_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_72_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_70_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_57_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataSel_1_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pGateDataSel_1_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_vCount_0_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_vCount_0_FFX_RST : STD_LOGIC; 
  signal PerLBusInterface0_vCount_2_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_vIncAddr_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_ActiveCount_1_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_0_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_ActiveCount_1_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_2_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayActive_3_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_57_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_FFY_RST : STD_LOGIC; 
  signal PerLBusInterface0_pCalDac_CLK_FFY_SET : STD_LOGIC; 
  signal pLD_13_IFF_SET : STD_LOGIC; 
  signal pLD_14_IFF_RST : STD_LOGIC; 
  signal pLD_15_IFF_RST : STD_LOGIC; 
  signal pLD_16_IFF_RST : STD_LOGIC; 
  signal pLD_24_IFF_RST : STD_LOGIC; 
  signal pLD_25_IFF_RST : STD_LOGIC; 
  signal pLD_26_IFF_RST : STD_LOGIC; 
  signal pLD_27_IFF_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_58_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_60_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_62_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_0_64_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_72_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_70_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_57_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_68_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_FFY_RST : STD_LOGIC; 
  signal pLD_17_IFF_RST : STD_LOGIC; 
  signal pLD_18_IFF_RST : STD_LOGIC; 
  signal pLD_19_IFF_RST : STD_LOGIC; 
  signal pLD_1_IFF_SET : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_62_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_64_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_58_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_60_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_62_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_64_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_1_66_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_58_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_60_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_62_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_64_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_66_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_70_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_2_72_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_57_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_60_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_58_FFX_RST : STD_LOGIC; 
  signal pLD_0_IFF_RST : STD_LOGIC; 
  signal pLD_10_IFF_RST : STD_LOGIC; 
  signal pLD_11_IFF_RST : STD_LOGIC; 
  signal pLD_12_IFF_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_66_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_68_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_3_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_2_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerRegs_1_1_FFY_RST : STD_LOGIC; 
  signal pAIN_0_OFF_RST : STD_LOGIC; 
  signal pAIN_1_OFF_SET : STD_LOGIC; 
  signal pAIN_2_OFF_RST : STD_LOGIC; 
  signal pAIN_3_OFF_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_70_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_DelayCount_3_72_FFX_RST : STD_LOGIC; 
  signal TriggerDelay0_OutShifter_0_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_OutShifter_1_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_0_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_1_FFY_RST : STD_LOGIC; 
  signal TriggerDelay0_TriggerOut_2_FFY_RST : STD_LOGIC; 
  signal pCAL_0_OFF_SET : STD_LOGIC; 
  signal pCAL_1_OFF_RST : STD_LOGIC; 
  signal pCAL_2_OFF_RST : STD_LOGIC; 
  signal pCalDac_CLK_OFF_RST : STD_LOGIC; 
  signal pCalDac_SDI_OFF_RST : STD_LOGIC; 
  signal pEncoder0In_0_IFF_RST : STD_LOGIC; 
  signal pEncoder0In_1_IFF_RST : STD_LOGIC; 
  signal pEncoder1In_0_IFF_RST : STD_LOGIC; 
  signal pEncoder1In_1_IFF_RST : STD_LOGIC; 
  signal pEncoder2In_0_IFF_RST : STD_LOGIC; 
  signal pEncoder2In_1_IFF_RST : STD_LOGIC; 
  signal pCalDac_nCS_OFF_RST : STD_LOGIC; 
  signal pCalDac_nLD_OFF_RST : STD_LOGIC; 
  signal pDdsFsk_OFF_RST : STD_LOGIC; 
  signal pDdsKey_OFF_RST : STD_LOGIC; 
  signal pLD_31_IFF_RST : STD_LOGIC; 
  signal pLD_3_IFF_RST : STD_LOGIC; 
  signal pLD_4_IFF_RST : STD_LOGIC; 
  signal pLD_5_IFF_RST : STD_LOGIC; 
  signal pZ6_OFF_RST : STD_LOGIC; 
  signal pZ7_OFF_RST : STD_LOGIC; 
  signal pZ11_OFF_SET : STD_LOGIC; 
  signal pZ2_OFF_RST : STD_LOGIC; 
  signal pZ3_OFF_RST : STD_LOGIC; 
  signal pZ4_OFF_RST : STD_LOGIC; 
  signal pZ5_OFF_RST : STD_LOGIC; 
  signal pLD_20_IFF_RST : STD_LOGIC; 
  signal pLD_21_IFF_RST : STD_LOGIC; 
  signal pLD_22_IFF_RST : STD_LOGIC; 
  signal pLD_23_IFF_RST : STD_LOGIC; 
  signal pPIO_12_OFF_RST : STD_LOGIC; 
  signal pPIO_13_OFF_RST : STD_LOGIC; 
  signal pPIO_14_OFF_RST : STD_LOGIC; 
  signal pLD_6_IFF_SET : STD_LOGIC; 
  signal pLD_7_IFF_RST : STD_LOGIC; 
  signal pLD_8_IFF_RST : STD_LOGIC; 
  signal pLD_9_IFF_RST : STD_LOGIC; 
  signal pLD_28_IFF_RST : STD_LOGIC; 
  signal pLD_29_IFF_RST : STD_LOGIC; 
  signal pLD_2_IFF_RST : STD_LOGIC; 
  signal pLD_30_IFF_RST : STD_LOGIC; 
  signal pLWnR_IFF_SET : STD_LOGIC; 
  signal pPIO_10_OFF_RST : STD_LOGIC; 
  signal pPIO_11_OFF_RST : STD_LOGIC; 
  signal pPIO_7_OFF_RST : STD_LOGIC; 
  signal pPIO_8_OFF_RST : STD_LOGIC; 
  signal pPIO_9_OFF_RST : STD_LOGIC; 
  signal pPIO_6_OFF_RST : STD_LOGIC; 
  signal pPIO_23_OFF_RST : STD_LOGIC; 
  signal pPIO_24_OFF_RST : STD_LOGIC; 
  signal pSEL_AC_DC_OFF_RST : STD_LOGIC; 
  signal pZ1_OFF_RST : STD_LOGIC; 
  signal pZ10_OFF_RST : STD_LOGIC; 
  signal BUFG0_CE : STD_LOGIC; 
  signal BUFG1_CE : STD_LOGIC; 
  signal VCC : STD_LOGIC; 
  signal NLW_EncoderMonitor0_EncCounts_0_inst_cy_37_rt_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_EncoderMonitor0_EncCounts_1_inst_cy_37_rt_IA_UNCONNECTED : STD_LOGIC; 
  signal NLW_EncoderMonitor0_EncCounts_2_inst_cy_37_rt_IA_UNCONNECTED : STD_LOGIC; 
  signal GND : STD_LOGIC; 
  signal TxCountMux : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal FocusUnitCtrl0_DelayValAddr : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal PerLBusInterface0_DelayValAddr : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal DelayValData : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal EncoderMonitor0_EncoderReset : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal BScanCtrl0_RxCount : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BScanCtrl0_n0048 : STD_LOGIC_VECTOR ( 6 downto 1 ); 
  signal BScanCtrl0_n0088 : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal BScanCtrl0_RepCount : STD_LOGIC_VECTOR ( 16 downto 0 ); 
  signal BScanCtrl0_vCount : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal BScanCtrl0_vBScanTrigger : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal BScanCtrl0_pTxCount : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal ElementNumOut : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal Encoder0In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Encoder1In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal Encoder2In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal EncoderMonitor0_ClkEnCount : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal EncoderMonitor0_EncInc : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal EncoderMonitor0_EncDec : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal PerLBusInterface0_pEncoderReset : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal EncoderMonitor0_TrigCount : STD_LOGIC_VECTOR ( 15 downto 0 ); 
  signal EncoderMonitor0_n0279 : STD_LOGIC_VECTOR ( 15 downto 1 ); 
  signal EncoderMonitor0_SerialResults : STD_LOGIC_VECTOR ( 191 downto 0 ); 
  signal EncoderMonitor0_ShiftCount : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal FocusUnitCtrl0_n0059 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal FocusUnitCtrl0_StrobeExtender0_CountLFSR : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal FocusUnitCtrl0_StrobeExtender1_CountLFSR : STD_LOGIC_VECTOR ( 8 downto 0 ); 
  signal FocusUnitCtrl0_pProbeData : STD_LOGIC_VECTOR ( 7 downto 0 ); 
  signal NlwRenamedSig_IO_pEncoder0In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_IO_pEncoder1In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal NlwRenamedSig_IO_pEncoder2In : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal PerLBusInterface0_CalDacShiftReg : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal PerLBusInterface0_pGateDataSel : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal PerLBusInterface0_CalDacCount : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal PerLBusInterface0_ReadRegDataMux : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal PerLBusInterface0_IntAddr : STD_LOGIC_VECTOR ( 7 downto 2 ); 
  signal PerLBusInterface0_vCount : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal PerLBusInterface0_n0000 : STD_LOGIC_VECTOR ( 5 downto 1 ); 
  signal PerLBusInterface0_n0152 : STD_LOGIC_VECTOR ( 6 downto 1 ); 
  signal PerLBusInterface0_n0376 : STD_LOGIC_VECTOR ( 4 downto 1 ); 
  signal PerLBusInterface0_ReadRegData : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal PerLBusInterface0_ReadRegMask : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal PerLBusInterface0_StrobeExtender0_CountLFSR : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal TriggerDelay0_ActiveCount : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal TriggerDelay0_DelayActive : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal TriggerDelay0_TriggerRegs : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal TriggerDelay0_OutShifter : STD_LOGIC_VECTOR ( 2 downto 0 ); 
  signal TriggerDelay0_TriggerOut : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal PerLBusInterface0_vCount_n0000 : STD_LOGIC_VECTOR ( 2 downto 1 ); 
  signal TriggerDelay0_ActiveCount_n0000 : STD_LOGIC_VECTOR ( 1 downto 1 ); 
  signal EncoderMonitor0_ClkEnCount_n0000 : STD_LOGIC_VECTOR ( 3 downto 1 ); 
  signal EncoderMonitor0_n0077 : STD_LOGIC_VECTOR ( 0 downto 0 ); 
  signal FocusUnitCtrl0_n0050 : STD_LOGIC_VECTOR ( 3 downto 0 ); 
  signal PerLBusInterface0_n0275 : STD_LOGIC_VECTOR ( 4 downto 0 ); 
  signal PerLBusInterface0_n0280 : STD_LOGIC_VECTOR ( 13 downto 0 ); 
  signal PerLBusInterface0_n0180 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal PerLBusInterface0_n0250 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal PerLBusInterface0_n0251 : STD_LOGIC_VECTOR ( 31 downto 0 ); 
  signal TriggerDelay0_n0038 : STD_LOGIC_VECTOR ( 1 downto 0 ); 
  signal BScanCtrl0_n0033 : STD_LOGIC_VECTOR ( 6 downto 0 ); 
  signal BScanCtrl0_n0019 : STD_LOGIC_VECTOR ( 2 downto 0 ); 
begin
  NlwRenamedSig_IO_pEncoder0In(1) <= pEncoder0In(1);
  NlwRenamedSig_IO_pEncoder0In(0) <= pEncoder0In(0);
  NlwRenamedSig_IO_pEncoder1In(1) <= pEncoder1In(1);
  NlwRenamedSig_IO_pEncoder1In(0) <= pEncoder1In(0);
  NlwRenamedSig_IO_pEncoder2In(1) <= pEncoder2In(1);
  NlwRenamedSig_IO_pEncoder2In(0) <= pEncoder2In(0);
  DelayValueRam0_delay_value_ram0 : delay_value_ram
    port map (
      web => PerLBusInterface0_vIncAddr,
      clka => SampleClk,
      clkb => LCLK,
      addra(10) => TxCountMux(6),
      addra(9) => TxCountMux(5),
      addra(8) => TxCountMux(4),
      addra(7) => TxCountMux(3),
      addra(6) => TxCountMux(2),
      addra(5) => TxCountMux(1),
      addra(4) => TxCountMux(0),
      addra(3) => FocusUnitCtrl0_DelayValAddr(3),
      addra(2) => FocusUnitCtrl0_DelayValAddr(2),
      addra(1) => FocusUnitCtrl0_DelayValAddr(1),
      addra(0) => FocusUnitCtrl0_DelayValAddr(0),
      addrb(8) => PerLBusInterface0_DelayValAddr(8),
      addrb(7) => PerLBusInterface0_DelayValAddr(7),
      addrb(6) => PerLBusInterface0_DelayValAddr(6),
      addrb(5) => PerLBusInterface0_DelayValAddr(5),
      addrb(4) => PerLBusInterface0_DelayValAddr(4),
      addrb(3) => PerLBusInterface0_DelayValAddr(3),
      addrb(2) => PerLBusInterface0_DelayValAddr(2),
      addrb(1) => PerLBusInterface0_DelayValAddr(1),
      addrb(0) => PerLBusInterface0_DelayValAddr(0),
      dinb(31) => PerLBusInterface0_RegBank_20_31,
      dinb(30) => PerLBusInterface0_RegBank_20_30,
      dinb(29) => PerLBusInterface0_RegBank_20_29,
      dinb(28) => PerLBusInterface0_RegBank_20_28,
      dinb(27) => PerLBusInterface0_RegBank_20_27,
      dinb(26) => PerLBusInterface0_RegBank_20_26,
      dinb(25) => PerLBusInterface0_RegBank_20_25,
      dinb(24) => PerLBusInterface0_RegBank_20_24,
      dinb(23) => PerLBusInterface0_RegBank_20_23,
      dinb(22) => PerLBusInterface0_RegBank_20_22,
      dinb(21) => PerLBusInterface0_RegBank_20_21,
      dinb(20) => PerLBusInterface0_RegBank_20_20,
      dinb(19) => PerLBusInterface0_RegBank_20_19,
      dinb(18) => PerLBusInterface0_RegBank_20_18,
      dinb(17) => PerLBusInterface0_RegBank_20_17,
      dinb(16) => PerLBusInterface0_RegBank_20_16,
      dinb(15) => PerLBusInterface0_RegBank_20_15,
      dinb(14) => PerLBusInterface0_RegBank_20_14,
      dinb(13) => PerLBusInterface0_RegBank_20_13,
      dinb(12) => PerLBusInterface0_RegBank_20_12,
      dinb(11) => PerLBusInterface0_RegBank_20_11,
      dinb(10) => PerLBusInterface0_RegBank_20_10,
      dinb(9) => PerLBusInterface0_RegBank_20_9,
      dinb(8) => PerLBusInterface0_RegBank_20_8,
      dinb(7) => PerLBusInterface0_RegBank_20_7,
      dinb(6) => PerLBusInterface0_RegBank_20_6,
      dinb(5) => PerLBusInterface0_RegBank_20_5,
      dinb(4) => PerLBusInterface0_RegBank_20_4,
      dinb(3) => PerLBusInterface0_RegBank_20_3,
      dinb(2) => PerLBusInterface0_RegBank_20_2,
      dinb(1) => PerLBusInterface0_RegBank_20_1,
      dinb(0) => PerLBusInterface0_RegBank_20_0,
      douta(7) => DelayValData(7),
      douta(6) => DelayValData(6),
      douta(5) => DelayValData(5),
      douta(4) => DelayValData(4),
      douta(3) => DelayValData(3),
      douta(2) => DelayValData(2),
      douta(1) => DelayValData(1),
      douta(0) => DelayValData(0)
    );
  PerLBusInterface0_n03721 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => PerLBusInterface0_CalDacCount(1),
      ADR2 => PerLBusInterface0_CalDacCount(0),
      ADR3 => PerLBusInterface0_CalDacCount(3),
      O => PerLBusInterface0_n0372_GROM
    );
  PerLBusInterface0_n0372_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0372_GROM,
      O => PerLBusInterface0_n0372
    );
  PerLBusInterface0_n0376_1_LOGIC_ZERO_19 : X_ZERO
    port map (
      O => PerLBusInterface0_n0376_1_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0376_inst_cy_106_20 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => PerLBusInterface0_n0376_1_LOGIC_ZERO,
      SEL => PerLBusInterface0_Madd_n0376_inst_lut2_44,
      O => PerLBusInterface0_Madd_n0376_inst_cy_106
    );
  PerLBusInterface0_Madd_n0376_inst_lut2_441 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_CalDacCount(0),
      O => PerLBusInterface0_Madd_n0376_inst_lut2_44
    );
  PerLBusInterface0_n0376_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_CalDacCount(1),
      ADR3 => VCC,
      O => PerLBusInterface0_n0376_1_GROM
    );
  PerLBusInterface0_n0376_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0376_1_XORG,
      O => PerLBusInterface0_n0376(1)
    );
  PerLBusInterface0_Madd_n0376_inst_cy_107 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => PerLBusInterface0_Madd_n0376_inst_cy_106,
      SEL => PerLBusInterface0_n0376_1_GROM,
      O => PerLBusInterface0_n0376_1_CYMUXG
    );
  PerLBusInterface0_Madd_n0376_inst_sum_92 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0376_inst_cy_106,
      I1 => PerLBusInterface0_n0376_1_GROM,
      O => PerLBusInterface0_n0376_1_XORG
    );
  PerLBusInterface0_n0376_2_LOGIC_ZERO_21 : X_ZERO
    port map (
      O => PerLBusInterface0_n0376_2_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0376_inst_cy_108_22 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0376_2_LOGIC_ZERO,
      IB => PerLBusInterface0_n0376_2_CYINIT,
      SEL => PerLBusInterface0_n0376_2_FROM,
      O => PerLBusInterface0_Madd_n0376_inst_cy_108
    );
  PerLBusInterface0_Madd_n0376_inst_sum_93 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0376_2_CYINIT,
      I1 => PerLBusInterface0_n0376_2_FROM,
      O => PerLBusInterface0_n0376_2_XORF
    );
  PerLBusInterface0_n0376_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0376_2_FROM
    );
  PerLBusInterface0_n0376_2_G : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalDacCount(3),
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0376_2_GROM
    );
  PerLBusInterface0_n0376_2_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0376_2_XORF,
      O => PerLBusInterface0_n0376(2)
    );
  PerLBusInterface0_n0376_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0376_2_XORG,
      O => PerLBusInterface0_n0376(3)
    );
  PerLBusInterface0_Madd_n0376_inst_cy_109 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0376_2_LOGIC_ZERO,
      IB => PerLBusInterface0_Madd_n0376_inst_cy_108,
      SEL => PerLBusInterface0_n0376_2_GROM,
      O => PerLBusInterface0_n0376_2_CYMUXG
    );
  PerLBusInterface0_Madd_n0376_inst_sum_94 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0376_inst_cy_108,
      I1 => PerLBusInterface0_n0376_2_GROM,
      O => PerLBusInterface0_n0376_2_XORG
    );
  PerLBusInterface0_n0376_2_CYINIT_23 : X_BUF
    port map (
      I => PerLBusInterface0_n0376_1_CYMUXG,
      O => PerLBusInterface0_n0376_2_CYINIT
    );
  PerLBusInterface0_Madd_n0376_inst_sum_95 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0376_4_CYINIT,
      I1 => PerLBusInterface0_CalDacCount_4_rt,
      O => PerLBusInterface0_n0376_4_XORF
    );
  PerLBusInterface0_CalDacCount_4_rt_24 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_CalDacCount_4_rt
    );
  PerLBusInterface0_n0376_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0376_4_XORF,
      O => PerLBusInterface0_n0376(4)
    );
  PerLBusInterface0_n0376_4_CYINIT_25 : X_BUF
    port map (
      I => PerLBusInterface0_n0376_2_CYMUXG,
      O => PerLBusInterface0_n0376_4_CYINIT
    );
  PerLBusInterface0_n04091 : X_LUT4
    generic map(
      INIT => X"7FFA"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => PerLBusInterface0_CalDacCount(0),
      ADR2 => PerLBusInterface0_CalDacCount(3),
      ADR3 => PerLBusInterface0_CalDacCount(1),
      O => PerLBusInterface0_n0409_FROM
    );
  PerLBusInterface0_Ker35285_SW0 : X_LUT4
    generic map(
      INIT => X"8001"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => PerLBusInterface0_CalDacCount(3),
      ADR2 => PerLBusInterface0_CalDacCount(0),
      ADR3 => PerLBusInterface0_CalDacCount(1),
      O => PerLBusInterface0_n0409_GROM
    );
  PerLBusInterface0_n0409_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0409_FROM,
      O => PerLBusInterface0_n0409
    );
  PerLBusInterface0_n0409_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0409_GROM,
      O => N45718
    );
  PerLBusInterface0_n04611 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_0_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_n0461_GROM
    );
  PerLBusInterface0_n0461_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0461_GROM,
      O => PerLBusInterface0_n0461
    );
  PerLBusInterface0_n04641 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_1_Q,
      O => PerLBusInterface0_n0464_GROM
    );
  PerLBusInterface0_n0464_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0464_GROM,
      O => PerLBusInterface0_n0464
    );
  PerLBusInterface0_n04701 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => PerLBusInterface0_RegWriteEn_4_Q,
      ADR3 => VCC,
      O => PerLBusInterface0_n0470_GROM
    );
  PerLBusInterface0_n0470_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0470_GROM,
      O => PerLBusInterface0_n0470
    );
  PerLBusInterface0_n04841 : X_LUT4
    generic map(
      INIT => X"AAFA"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegWriteEn_15_Q,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_n0484_FROM
    );
  PerLBusInterface0_n04841_1_26 : X_LUT4
    generic map(
      INIT => X"CCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_GateDataOut,
      ADR2 => PerLBusInterface0_RegWriteEn_15_Q,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_n0484_GROM
    );
  PerLBusInterface0_n0484_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0484_FROM,
      O => PerLBusInterface0_n0484
    );
  PerLBusInterface0_n0484_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0484_GROM,
      O => PerLBusInterface0_n04841_1
    );
  PerLBusInterface0_n04891 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegWriteEn_17_Q,
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_n0489_GROM
    );
  PerLBusInterface0_n0489_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0489_GROM,
      O => PerLBusInterface0_n0489
    );
  PerLBusInterface0_n04921 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_18_Q,
      O => PerLBusInterface0_n0492_GROM
    );
  PerLBusInterface0_n0492_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0492_GROM,
      O => PerLBusInterface0_n0492
    );
  PerLBusInterface0_n04961 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_63_Q,
      O => PerLBusInterface0_n0496_GROM
    );
  PerLBusInterface0_n0496_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0496_GROM,
      O => PerLBusInterface0_n0496
    );
  PerLBusInterface0_n05371 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => PerLBusInterface0_CalClkEn2,
      ADR1 => PerLBusInterface0_CalClkEn1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0537_FROM
    );
  PerLBusInterface0_n01961 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalClkEn1,
      ADR2 => pnLReset_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_n0537_GROM
    );
  PerLBusInterface0_n0537_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0537_FROM,
      O => PerLBusInterface0_n0537
    );
  PerLBusInterface0_n0537_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0537_GROM,
      O => PerLBusInterface0_n0196
    );
  PerLBusInterface0_Mrom_n0312_inst_lut4_441 : X_LUT4
    generic map(
      INIT => X"8001"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(0),
      ADR1 => PerLBusInterface0_CalDacCount(1),
      ADR2 => PerLBusInterface0_CalDacCount(3),
      ADR3 => PerLBusInterface0_CalDacCount(2),
      O => PerLBusInterface0_pCalDac_CLK_FROM
    );
  PerLBusInterface0_n02771 : X_LUT4
    generic map(
      INIT => X"FFCF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => PerLBusInterface0_CalClkEn1,
      ADR3 => PerLBusInterface0_n0312,
      O => PerLBusInterface0_n0277
    );
  PerLBusInterface0_pCalDac_CLK_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_CLK_FROM,
      O => PerLBusInterface0_n0312
    );
  PerLBusInterface0_pCalDac_CLK_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_pCalDac_CLK_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pCalDac_nCS_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_pCalDac_nCS_FROM
    );
  PerLBusInterface0_n02791 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0312,
      O => PerLBusInterface0_n0279
    );
  PerLBusInterface0_pCalDac_nCS_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_nCS_FROM,
      O => PerLBusInterface0_pCalDac_nCS_X
    );
  PerLBusInterface0_pCalDac_nCS_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_pCalDac_nCS_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0278_SW0 : X_LUT4
    generic map(
      INIT => X"F0FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_CalDacCount(3),
      ADR3 => PerLBusInterface0_CalDacCount(4),
      O => PerLBusInterface0_pCalDac_nLD_FROM
    );
  PerLBusInterface0_n0278_27 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => PerLBusInterface0_CalDacCount(1),
      ADR2 => PerLBusInterface0_CalDacCount(0),
      ADR3 => N44557,
      O => PerLBusInterface0_n0278
    );
  PerLBusInterface0_pCalDac_nLD_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_nLD_FROM,
      O => N44557
    );
  PerLBusInterface0_pCalDac_nLD_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_pCalDac_nLD_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03421 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_9_Q,
      O => PerLBusInterface0_n0342
    );
  PerLBusInterface0_n03431 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_8_Q,
      O => PerLBusInterface0_n0343
    );
  PerLBusInterface0_pEncoderReset_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_pEncoderReset_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03411 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegWriteEn_10_Q,
      O => PerLBusInterface0_n0341
    );
  PerLBusInterface0_pEncoderReset_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_pEncoderReset_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pGateDataEn_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_pGateDataEn_FROM
    );
  PerLBusInterface0_pGateDataEn_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_pGateDataEn_GROM
    );
  PerLBusInterface0_pGateDataEn_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataEn_FROM,
      O => PerLBusInterface0_pGateDataEn_X
    );
  PerLBusInterface0_pGateDataEn_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataEn_GROM,
      O => PerLBusInterface0_pGateDataEn_Y
    );
  PerLBusInterface0_vCount_Madd_n0000_Mxor_Result_1_Result1 : X_LUT4
    generic map(
      INIT => X"5A5A"
    )
    port map (
      ADR0 => PerLBusInterface0_vCount(0),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_vCount(1),
      ADR3 => VCC,
      O => PerLBusInterface0_vCount_n0000(1)
    );
  PerLBusInterface0_vCount_0_BXMUX : X_INV
    port map (
      I => PerLBusInterface0_vCount(0),
      O => PerLBusInterface0_vCount_0_BXMUXNOT
    );
  PerLBusInterface0_vCount_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_vCount_0_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_vCount_Madd_n0000_Mxor_Result_2_Result1 : X_LUT4
    generic map(
      INIT => X"7878"
    )
    port map (
      ADR0 => PerLBusInterface0_vCount(1),
      ADR1 => PerLBusInterface0_vCount(0),
      ADR2 => PerLBusInterface0_vCount(2),
      ADR3 => VCC,
      O => PerLBusInterface0_vCount_n0000(2)
    );
  PerLBusInterface0_vCount_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_vCount_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n02371 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_RegWriteEn_20_Q,
      O => PerLBusInterface0_vIncAddr_GROM
    );
  PerLBusInterface0_vIncAddr_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_vIncAddr_GROM,
      O => PerLBusInterface0_n0237
    );
  PerLBusInterface0_vIncAddr_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_vIncAddr_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_ActiveCount_Madd_n0000_Mxor_Result_1_Result1 : X_LUT4
    generic map(
      INIT => X"6666"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_ActiveCount(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => TriggerDelay0_ActiveCount_n0000(1)
    );
  TriggerDelay0_n00211 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs(2),
      ADR1 => VCC,
      ADR2 => TriggerDelay0_TriggerRegs(1),
      ADR3 => VCC,
      O => TriggerDelay0_ActiveCount_1_GROM
    );
  TriggerDelay0_ActiveCount_1_YUSED : X_BUF
    port map (
      I => TriggerDelay0_ActiveCount_1_GROM,
      O => TriggerDelay0_n0021
    );
  TriggerDelay0_ActiveCount_1_BYMUX : X_INV
    port map (
      I => TriggerDelay0_ActiveCount(0),
      O => TriggerDelay0_ActiveCount_1_BYMUXNOT
    );
  TriggerDelay0_ActiveCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_ActiveCount_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_inst_lut3_351_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(0),
      ADR1 => TriggerDelay0_TriggerRegs(2),
      ADR2 => TriggerDelay0_DelayActive(0),
      ADR3 => TriggerDelay0_ActiveCount(1),
      O => TriggerDelay0_DelayActive_0_FROM
    );
  TriggerDelay0_n00221 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_DelayActive(0),
      ADR2 => TriggerDelay0_ActiveCount(0),
      ADR3 => TriggerDelay0_n0021,
      O => TriggerDelay0_DelayActive_0_GROM
    );
  TriggerDelay0_DelayActive_0_XUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_0_FROM,
      O => N50556
    );
  TriggerDelay0_DelayActive_0_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_0_GROM,
      O => TriggerDelay0_n0022
    );
  TriggerDelay0_DelayActive_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayActive_0_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_inst_lut3_341_SW0 : X_LUT4
    generic map(
      INIT => X"FFFB"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(1),
      ADR1 => TriggerDelay0_ActiveCount(0),
      ADR2 => TriggerDelay0_ActiveCount(1),
      ADR3 => TriggerDelay0_TriggerRegs(2),
      O => TriggerDelay0_DelayActive_1_FROM
    );
  TriggerDelay0_n00231 : X_LUT4
    generic map(
      INIT => X"0400"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(1),
      ADR1 => TriggerDelay0_n0021,
      ADR2 => TriggerDelay0_ActiveCount(1),
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => TriggerDelay0_DelayActive_1_GROM
    );
  TriggerDelay0_DelayActive_1_XUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_1_FROM,
      O => N50548
    );
  TriggerDelay0_DelayActive_1_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_1_GROM,
      O => TriggerDelay0_n0023
    );
  TriggerDelay0_DelayActive_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayActive_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_inst_lut3_351_SW0 : X_LUT4
    generic map(
      INIT => X"FEFF"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(0),
      ADR1 => TriggerDelay0_DelayActive(2),
      ADR2 => TriggerDelay0_TriggerRegs(2),
      ADR3 => TriggerDelay0_ActiveCount(1),
      O => TriggerDelay0_DelayActive_2_FROM
    );
  TriggerDelay0_n00241 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_DelayActive(2),
      ADR2 => TriggerDelay0_n0021,
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => TriggerDelay0_DelayActive_2_GROM
    );
  TriggerDelay0_DelayActive_2_XUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_2_FROM,
      O => N50564
    );
  TriggerDelay0_DelayActive_2_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_2_GROM,
      O => TriggerDelay0_n0024
    );
  TriggerDelay0_DelayActive_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayActive_2_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_inst_lut3_351_SW0 : X_LUT4
    generic map(
      INIT => X"EFFF"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(3),
      ADR1 => TriggerDelay0_TriggerRegs(2),
      ADR2 => TriggerDelay0_ActiveCount(1),
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => TriggerDelay0_DelayActive_3_FROM
    );
  TriggerDelay0_n00251 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_DelayActive(3),
      ADR2 => TriggerDelay0_ActiveCount(0),
      ADR3 => TriggerDelay0_n0021,
      O => TriggerDelay0_DelayActive_3_GROM
    );
  TriggerDelay0_DelayActive_3_XUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_3_FROM,
      O => N50568
    );
  TriggerDelay0_DelayActive_3_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayActive_3_GROM,
      O => TriggerDelay0_n0025
    );
  TriggerDelay0_DelayActive_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayActive_3_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_57_LOGIC_ONE_28 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_57_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_145_29 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => TriggerDelay0_DelayCount_0_57_LOGIC_ONE,
      SEL => TriggerDelay0_n0022_rt,
      O => TriggerDelay0_DelayCount_0_inst_cy_145
    );
  TriggerDelay0_n0022_rt_30 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0022,
      O => TriggerDelay0_n0022_rt
    );
  TriggerDelay0_DelayCount_0_57_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_DelayCount_0_inst_lut3_281_O,
      O => TriggerDelay0_DelayCount_0_57_GROM
    );
  TriggerDelay0_DelayCount_0_inst_cy_146 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => TriggerDelay0_DelayCount_0_inst_cy_145,
      SEL => TriggerDelay0_DelayCount_0_57_GROM,
      O => TriggerDelay0_DelayCount_0_57_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_128_31 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_145,
      I1 => TriggerDelay0_DelayCount_0_57_GROM,
      O => TriggerDelay0_DelayCount_0_inst_sum_128
    );
  TriggerDelay0_DelayCount_0_57_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_57_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_58_LOGIC_ONE_32 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_58_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_147_33 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_58_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_0_inst_cy_147
    );
  TriggerDelay0_DelayCount_0_inst_sum_129_34 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_58_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_129
    );
  TriggerDelay0_DelayCount_0_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"3353"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_1,
      ADR1 => TriggerDelay0_DelayCount_0_58,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => N50536,
      O => TriggerDelay0_DelayCount_0_inst_lut3_291_O
    );
  TriggerDelay0_DelayCount_0_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"02F7"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_2,
      ADR2 => N50536,
      ADR3 => TriggerDelay0_DelayCount_0_59,
      O => TriggerDelay0_DelayCount_0_inst_lut3_301_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_148 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_147,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_0_58_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_130_35 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_147,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_130
    );
  TriggerDelay0_DelayCount_0_58_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_58_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_58_CYINIT_36 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_57_CYMUXG,
      O => TriggerDelay0_DelayCount_0_58_CYINIT
    );
  TriggerDelay0_DelayCount_0_60_LOGIC_ONE_37 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_60_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_149_38 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_60_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_0_inst_cy_149
    );
  TriggerDelay0_DelayCount_0_inst_sum_131_39 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_60_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_131
    );
  TriggerDelay0_DelayCount_0_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"2373"
    )
    port map (
      ADR0 => N50536,
      ADR1 => TriggerDelay0_DelayCount_0_60,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => PerLBusInterface0_RegBank_1_3,
      O => TriggerDelay0_DelayCount_0_inst_lut3_311_O
    );
  TriggerDelay0_DelayCount_0_inst_lut3_321 : X_LUT4
    generic map(
      INIT => X"1B0F"
    )
    port map (
      ADR0 => N50536,
      ADR1 => PerLBusInterface0_RegBank_1_4,
      ADR2 => TriggerDelay0_DelayCount_0_61,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_0_inst_lut3_321_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_150 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_149,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_0_60_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_132_40 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_149,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_132
    );
  TriggerDelay0_DelayCount_0_60_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_60_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_60_CYINIT_41 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_58_CYMUXG,
      O => TriggerDelay0_DelayCount_0_60_CYINIT
    );
  TriggerDelay0_DelayCount_0_62_LOGIC_ONE_42 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_62_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_151_43 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_62_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_331_O,
      O => TriggerDelay0_DelayCount_0_inst_cy_151
    );
  TriggerDelay0_DelayCount_0_inst_sum_133_44 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_62_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_331_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_133
    );
  TriggerDelay0_DelayCount_0_inst_lut3_331 : X_LUT4
    generic map(
      INIT => X"0F27"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_5,
      ADR2 => TriggerDelay0_DelayCount_0_62,
      ADR3 => N50536,
      O => TriggerDelay0_DelayCount_0_inst_lut3_331_O
    );
  TriggerDelay0_DelayCount_0_inst_lut3_341 : X_LUT4
    generic map(
      INIT => X"02DF"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => N50536,
      ADR2 => PerLBusInterface0_RegBank_1_6,
      ADR3 => TriggerDelay0_DelayCount_0_63,
      O => TriggerDelay0_DelayCount_0_inst_lut3_341_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_152 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_151,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_0_62_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_134_45 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_151,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_134
    );
  TriggerDelay0_DelayCount_0_62_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_62_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_62_CYINIT_46 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_60_CYMUXG,
      O => TriggerDelay0_DelayCount_0_62_CYINIT
    );
  TriggerDelay0_DelayCount_0_64_LOGIC_ONE_47 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_64_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_153_48 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_64_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_35,
      O => TriggerDelay0_DelayCount_0_inst_cy_153
    );
  TriggerDelay0_DelayCount_0_inst_sum_135_49 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_64_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_35,
      O => TriggerDelay0_DelayCount_0_inst_sum_135
    );
  TriggerDelay0_DelayCount_0_inst_lut3_351 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_7,
      ADR1 => TriggerDelay0_DelayCount_0_64,
      ADR2 => N50556,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_0_inst_lut3_35
    );
  TriggerDelay0_DelayCount_0_inst_lut3_361 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_8,
      ADR1 => TriggerDelay0_DelayCount_0_65,
      ADR2 => N50536,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_0_inst_lut3_361_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_154 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_153,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_361_O,
      O => TriggerDelay0_DelayCount_0_64_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_136_50 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_153,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_361_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_136
    );
  TriggerDelay0_DelayCount_0_64_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_64_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_64_CYINIT_51 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_62_CYMUXG,
      O => TriggerDelay0_DelayCount_0_64_CYINIT
    );
  TriggerDelay0_DelayCount_0_66_LOGIC_ONE_52 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_66_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_155_53 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_66_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_37,
      O => TriggerDelay0_DelayCount_0_inst_cy_155
    );
  TriggerDelay0_DelayCount_0_inst_sum_137_54 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_66_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_37,
      O => TriggerDelay0_DelayCount_0_inst_sum_137
    );
  TriggerDelay0_DelayCount_0_inst_lut3_371 : X_LUT4
    generic map(
      INIT => X"313B"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => TriggerDelay0_DelayCount_0_66,
      ADR2 => N50536,
      ADR3 => PerLBusInterface0_RegBank_1_9,
      O => TriggerDelay0_DelayCount_0_inst_lut3_37
    );
  TriggerDelay0_DelayCount_0_inst_lut3_381 : X_LUT4
    generic map(
      INIT => X"05F5"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_67,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0022,
      ADR3 => PerLBusInterface0_RegBank_1_10,
      O => TriggerDelay0_DelayCount_0_inst_lut3_381_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_156 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_155,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_0_66_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_138_55 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_155,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_138
    );
  TriggerDelay0_DelayCount_0_66_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_66_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_66_CYINIT_56 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_64_CYMUXG,
      O => TriggerDelay0_DelayCount_0_66_CYINIT
    );
  TriggerDelay0_DelayCount_0_68_LOGIC_ONE_57 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_68_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_157_58 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_68_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_0_inst_cy_157
    );
  TriggerDelay0_DelayCount_0_inst_sum_139_59 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_68_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_139
    );
  TriggerDelay0_DelayCount_0_inst_lut3_391 : X_LUT4
    generic map(
      INIT => X"5353"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_11,
      ADR1 => TriggerDelay0_DelayCount_0_68,
      ADR2 => TriggerDelay0_n0022,
      ADR3 => VCC,
      O => TriggerDelay0_DelayCount_0_inst_lut3_391_O
    );
  TriggerDelay0_DelayCount_0_inst_lut3_401 : X_LUT4
    generic map(
      INIT => X"3535"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_69,
      ADR1 => PerLBusInterface0_RegBank_1_12,
      ADR2 => TriggerDelay0_n0022,
      ADR3 => VCC,
      O => TriggerDelay0_DelayCount_0_inst_lut3_401_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_158 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_157,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_0_68_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_140_60 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_157,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_140
    );
  TriggerDelay0_DelayCount_0_68_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_68_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_68_CYINIT_61 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_66_CYMUXG,
      O => TriggerDelay0_DelayCount_0_68_CYINIT
    );
  TriggerDelay0_DelayCount_0_70_LOGIC_ONE_62 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_0_70_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_0_inst_cy_159_63 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_70_CYINIT,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_0_inst_cy_159
    );
  TriggerDelay0_DelayCount_0_inst_sum_141_64 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_70_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_141
    );
  TriggerDelay0_DelayCount_0_inst_lut3_411 : X_LUT4
    generic map(
      INIT => X"03F3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_0_70,
      ADR2 => TriggerDelay0_n0022,
      ADR3 => PerLBusInterface0_RegBank_1_13,
      O => TriggerDelay0_DelayCount_0_inst_lut3_411_O
    );
  TriggerDelay0_DelayCount_0_inst_lut3_421 : X_LUT4
    generic map(
      INIT => X"0F33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_0_71,
      ADR2 => PerLBusInterface0_RegBank_1_14,
      ADR3 => TriggerDelay0_n0022,
      O => TriggerDelay0_DelayCount_0_inst_lut3_421_O
    );
  TriggerDelay0_DelayCount_0_inst_cy_160 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_0_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_0_inst_cy_159,
      SEL => TriggerDelay0_DelayCount_0_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_0_70_CYMUXG
    );
  TriggerDelay0_DelayCount_0_inst_sum_142_65 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_inst_cy_159,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_142
    );
  TriggerDelay0_DelayCount_0_70_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_70_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_70_CYINIT_66 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_68_CYMUXG,
      O => TriggerDelay0_DelayCount_0_70_CYINIT
    );
  TriggerDelay0_DelayCount_0_inst_sum_143_67 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_72_CYINIT,
      I1 => TriggerDelay0_DelayCount_0_inst_lut3_431_O,
      O => TriggerDelay0_DelayCount_0_inst_sum_143
    );
  TriggerDelay0_DelayCount_0_inst_lut3_431 : X_LUT4
    generic map(
      INIT => X"0F33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_0_72,
      ADR2 => PerLBusInterface0_RegBank_1_15,
      ADR3 => TriggerDelay0_n0022,
      O => TriggerDelay0_DelayCount_0_inst_lut3_431_O
    );
  TriggerDelay0_n00841 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(0),
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0051,
      ADR3 => TriggerDelay0_n0022,
      O => TriggerDelay0_DelayCount_0_72_GROM
    );
  TriggerDelay0_DelayCount_0_72_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_72_GROM,
      O => TriggerDelay0_n0084
    );
  TriggerDelay0_DelayCount_0_72_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_0_72_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_72_CYINIT_68 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_0_70_CYMUXG,
      O => TriggerDelay0_DelayCount_0_72_CYINIT
    );
  TriggerDelay0_DelayCount_1_57_LOGIC_ONE_69 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_57_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_145_70 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => TriggerDelay0_DelayCount_1_57_LOGIC_ONE,
      SEL => TriggerDelay0_n0023_rt,
      O => TriggerDelay0_DelayCount_1_inst_cy_145
    );
  TriggerDelay0_n0023_rt_71 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => TriggerDelay0_n0023,
      ADR2 => VCC,
      ADR3 => VCC,
      O => TriggerDelay0_n0023_rt
    );
  TriggerDelay0_DelayCount_1_57_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_DelayCount_1_inst_lut3_281_O,
      O => TriggerDelay0_DelayCount_1_57_GROM
    );
  TriggerDelay0_DelayCount_1_inst_cy_146 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => TriggerDelay0_DelayCount_1_inst_cy_145,
      SEL => TriggerDelay0_DelayCount_1_57_GROM,
      O => TriggerDelay0_DelayCount_1_57_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_128_72 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_145,
      I1 => TriggerDelay0_DelayCount_1_57_GROM,
      O => TriggerDelay0_DelayCount_1_inst_sum_128
    );
  TriggerDelay0_DelayCount_1_57_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_57_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_58_LOGIC_ONE_73 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_58_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_147_74 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_58_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_1_inst_cy_147
    );
  TriggerDelay0_DelayCount_1_inst_sum_129_75 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_58_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_129
    );
  TriggerDelay0_DelayCount_1_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"0F47"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_1,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => TriggerDelay0_DelayCount_1_58,
      ADR3 => N50560,
      O => TriggerDelay0_DelayCount_1_inst_lut3_291_O
    );
  TriggerDelay0_DelayCount_1_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"5535"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_59,
      ADR1 => PerLBusInterface0_RegBank_1_2,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => N50560,
      O => TriggerDelay0_DelayCount_1_inst_lut3_301_O
    );
  TriggerDelay0_DelayCount_1_inst_cy_148 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_147,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_1_58_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_130_76 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_147,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_130
    );
  TriggerDelay0_DelayCount_1_58_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_58_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_58_CYINIT_77 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_57_CYMUXG,
      O => TriggerDelay0_DelayCount_1_58_CYINIT
    );
  TriggerDelay0_DelayCount_1_60_LOGIC_ONE_78 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_60_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_149_79 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_60_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_1_inst_cy_149
    );
  TriggerDelay0_DelayCount_1_inst_sum_131_80 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_60_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_131
    );
  TriggerDelay0_DelayCount_1_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"4755"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_60,
      ADR1 => N50560,
      ADR2 => PerLBusInterface0_RegBank_1_3,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_1_inst_lut3_311_O
    );
  TriggerDelay0_DelayCount_1_inst_lut3_321 : X_LUT4
    generic map(
      INIT => X"10DF"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_4,
      ADR1 => N50560,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => TriggerDelay0_DelayCount_1_61,
      O => TriggerDelay0_DelayCount_1_inst_lut3_321_O
    );
  TriggerDelay0_DelayCount_1_inst_cy_150 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_149,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_1_60_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_132_81 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_149,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_132
    );
  TriggerDelay0_DelayCount_1_60_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_60_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_60_CYINIT_82 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_58_CYMUXG,
      O => TriggerDelay0_DelayCount_1_60_CYINIT
    );
  TriggerDelay0_DelayCount_1_62_LOGIC_ONE_83 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_62_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_151_84 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_62_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_33,
      O => TriggerDelay0_DelayCount_1_inst_cy_151
    );
  TriggerDelay0_DelayCount_1_inst_sum_133_85 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_62_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_33,
      O => TriggerDelay0_DelayCount_1_inst_sum_133
    );
  TriggerDelay0_DelayCount_1_inst_lut3_331 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => N50524,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => PerLBusInterface0_RegBank_1_5,
      ADR3 => TriggerDelay0_DelayCount_1_62,
      O => TriggerDelay0_DelayCount_1_inst_lut3_33
    );
  TriggerDelay0_DelayCount_1_inst_lut3_341 : X_LUT4
    generic map(
      INIT => X"10BF"
    )
    port map (
      ADR0 => N50548,
      ADR1 => PerLBusInterface0_RegBank_1_6,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => TriggerDelay0_DelayCount_1_63,
      O => TriggerDelay0_DelayCount_1_inst_lut3_34
    );
  TriggerDelay0_DelayCount_1_inst_cy_152 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_151,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_34,
      O => TriggerDelay0_DelayCount_1_62_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_134_86 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_151,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_34,
      O => TriggerDelay0_DelayCount_1_inst_sum_134
    );
  TriggerDelay0_DelayCount_1_62_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_62_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_62_CYINIT_87 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_60_CYMUXG,
      O => TriggerDelay0_DelayCount_1_62_CYINIT
    );
  TriggerDelay0_DelayCount_1_64_LOGIC_ONE_88 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_64_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_153_89 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_64_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_35,
      O => TriggerDelay0_DelayCount_1_inst_cy_153
    );
  TriggerDelay0_DelayCount_1_inst_sum_135_90 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_64_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_35,
      O => TriggerDelay0_DelayCount_1_inst_sum_135
    );
  TriggerDelay0_DelayCount_1_inst_lut3_351 : X_LUT4
    generic map(
      INIT => X"4575"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_64,
      ADR1 => N50560,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => PerLBusInterface0_RegBank_1_7,
      O => TriggerDelay0_DelayCount_1_inst_lut3_35
    );
  TriggerDelay0_DelayCount_1_inst_lut3_361 : X_LUT4
    generic map(
      INIT => X"1D0F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_8,
      ADR1 => N50560,
      ADR2 => TriggerDelay0_DelayCount_1_65,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_1_inst_lut3_36
    );
  TriggerDelay0_DelayCount_1_inst_cy_154 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_153,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_36,
      O => TriggerDelay0_DelayCount_1_64_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_136_91 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_153,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_36,
      O => TriggerDelay0_DelayCount_1_inst_sum_136
    );
  TriggerDelay0_DelayCount_1_64_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_64_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_64_CYINIT_92 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_62_CYMUXG,
      O => TriggerDelay0_DelayCount_1_64_CYINIT
    );
  TriggerDelay0_DelayCount_1_66_LOGIC_ONE_93 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_66_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_155_94 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_66_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_37,
      O => TriggerDelay0_DelayCount_1_inst_cy_155
    );
  TriggerDelay0_DelayCount_1_inst_sum_137_95 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_66_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_37,
      O => TriggerDelay0_DelayCount_1_inst_sum_137
    );
  TriggerDelay0_DelayCount_1_inst_lut3_371 : X_LUT4
    generic map(
      INIT => X"10BF"
    )
    port map (
      ADR0 => N50560,
      ADR1 => PerLBusInterface0_RegBank_1_9,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => TriggerDelay0_DelayCount_1_66,
      O => TriggerDelay0_DelayCount_1_inst_lut3_37
    );
  TriggerDelay0_DelayCount_1_inst_lut3_381 : X_LUT4
    generic map(
      INIT => X"4747"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_10,
      ADR1 => TriggerDelay0_n0023,
      ADR2 => TriggerDelay0_DelayCount_1_67,
      ADR3 => VCC,
      O => TriggerDelay0_DelayCount_1_inst_lut3_381_O
    );
  TriggerDelay0_DelayCount_1_inst_cy_156 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_155,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_1_66_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_138_96 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_155,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_138
    );
  TriggerDelay0_DelayCount_1_66_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_66_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_66_CYINIT_97 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_64_CYMUXG,
      O => TriggerDelay0_DelayCount_1_66_CYINIT
    );
  TriggerDelay0_DelayCount_1_68_LOGIC_ONE_98 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_68_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_157_99 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_68_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_1_inst_cy_157
    );
  TriggerDelay0_DelayCount_1_inst_sum_139_100 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_68_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_139
    );
  TriggerDelay0_DelayCount_1_inst_lut3_391 : X_LUT4
    generic map(
      INIT => X"303F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_1_11,
      ADR2 => TriggerDelay0_n0023,
      ADR3 => TriggerDelay0_DelayCount_1_68,
      O => TriggerDelay0_DelayCount_1_inst_lut3_391_O
    );
  TriggerDelay0_DelayCount_1_inst_lut3_401 : X_LUT4
    generic map(
      INIT => X"0F33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_1_69,
      ADR2 => PerLBusInterface0_RegBank_1_12,
      ADR3 => TriggerDelay0_n0023,
      O => TriggerDelay0_DelayCount_1_inst_lut3_401_O
    );
  TriggerDelay0_DelayCount_1_inst_cy_158 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_157,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_1_68_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_140_101 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_157,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_140
    );
  TriggerDelay0_DelayCount_1_68_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_68_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_68_CYINIT_102 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_66_CYMUXG,
      O => TriggerDelay0_DelayCount_1_68_CYINIT
    );
  TriggerDelay0_DelayCount_1_70_LOGIC_ONE_103 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_1_70_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_1_inst_cy_159_104 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_70_CYINIT,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_1_inst_cy_159
    );
  TriggerDelay0_DelayCount_1_inst_sum_141_105 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_70_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_141
    );
  TriggerDelay0_DelayCount_1_inst_lut3_411 : X_LUT4
    generic map(
      INIT => X"550F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_13,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_DelayCount_1_70,
      ADR3 => TriggerDelay0_n0023,
      O => TriggerDelay0_DelayCount_1_inst_lut3_411_O
    );
  TriggerDelay0_DelayCount_1_inst_lut3_421 : X_LUT4
    generic map(
      INIT => X"5533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_14,
      ADR1 => TriggerDelay0_DelayCount_1_71,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0023,
      O => TriggerDelay0_DelayCount_1_inst_lut3_421_O
    );
  TriggerDelay0_DelayCount_1_inst_cy_160 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_1_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_1_inst_cy_159,
      SEL => TriggerDelay0_DelayCount_1_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_1_70_CYMUXG
    );
  TriggerDelay0_DelayCount_1_inst_sum_142_106 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_inst_cy_159,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_142
    );
  TriggerDelay0_DelayCount_1_70_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_70_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_70_CYINIT_107 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_68_CYMUXG,
      O => TriggerDelay0_DelayCount_1_70_CYINIT
    );
  TriggerDelay0_DelayCount_1_inst_sum_143_108 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_72_CYINIT,
      I1 => TriggerDelay0_DelayCount_1_inst_lut3_431_O,
      O => TriggerDelay0_DelayCount_1_inst_sum_143
    );
  TriggerDelay0_DelayCount_1_inst_lut3_431 : X_LUT4
    generic map(
      INIT => X"0C3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_n0023,
      ADR2 => PerLBusInterface0_RegBank_1_15,
      ADR3 => TriggerDelay0_DelayCount_1_72,
      O => TriggerDelay0_DelayCount_1_inst_lut3_431_O
    );
  TriggerDelay0_n00821 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(1),
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0050,
      ADR3 => TriggerDelay0_n0023,
      O => TriggerDelay0_DelayCount_1_72_GROM
    );
  TriggerDelay0_DelayCount_1_72_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_72_GROM,
      O => TriggerDelay0_n0082
    );
  TriggerDelay0_DelayCount_1_72_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_1_72_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_72_CYINIT_109 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_1_70_CYMUXG,
      O => TriggerDelay0_DelayCount_1_72_CYINIT
    );
  TriggerDelay0_DelayCount_2_57_LOGIC_ONE_110 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_57_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_145_111 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => TriggerDelay0_DelayCount_2_57_LOGIC_ONE,
      SEL => TriggerDelay0_n0024_rt,
      O => TriggerDelay0_DelayCount_2_inst_cy_145
    );
  TriggerDelay0_n0024_rt_112 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0024,
      ADR3 => VCC,
      O => TriggerDelay0_n0024_rt
    );
  TriggerDelay0_DelayCount_2_57_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_DelayCount_2_inst_lut3_281_O,
      O => TriggerDelay0_DelayCount_2_57_GROM
    );
  TriggerDelay0_DelayCount_2_inst_cy_146 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => TriggerDelay0_DelayCount_2_inst_cy_145,
      SEL => TriggerDelay0_DelayCount_2_57_GROM,
      O => TriggerDelay0_DelayCount_2_57_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_128_113 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_145,
      I1 => TriggerDelay0_DelayCount_2_57_GROM,
      O => TriggerDelay0_DelayCount_2_inst_sum_128
    );
  TriggerDelay0_DelayCount_2_57_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_57_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_58_LOGIC_ONE_114 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_58_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_147_115 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_58_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_2_inst_cy_147
    );
  TriggerDelay0_DelayCount_2_inst_sum_129_116 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_58_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_129
    );
  TriggerDelay0_DelayCount_2_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"0F47"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_1,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => TriggerDelay0_DelayCount_2_58,
      ADR3 => N50903,
      O => TriggerDelay0_DelayCount_2_inst_lut3_291_O
    );
  TriggerDelay0_DelayCount_2_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"515D"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_59,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => N50903,
      ADR3 => PerLBusInterface0_RegBank_1_2,
      O => TriggerDelay0_DelayCount_2_inst_lut3_301_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_148 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_147,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_2_58_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_130_117 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_147,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_130
    );
  TriggerDelay0_DelayCount_2_58_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_58_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_58_CYINIT_118 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_57_CYMUXG,
      O => TriggerDelay0_DelayCount_2_58_CYINIT
    );
  TriggerDelay0_DelayCount_2_60_LOGIC_ONE_119 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_60_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_149_120 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_60_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_2_inst_cy_149
    );
  TriggerDelay0_DelayCount_2_inst_sum_131_121 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_60_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_131
    );
  TriggerDelay0_DelayCount_2_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_3,
      ADR1 => TriggerDelay0_DelayCount_2_60,
      ADR2 => N50903,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_2_inst_lut3_311_O
    );
  TriggerDelay0_DelayCount_2_inst_lut3_321 : X_LUT4
    generic map(
      INIT => X"0F47"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_4,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => TriggerDelay0_DelayCount_2_61,
      ADR3 => N50903,
      O => TriggerDelay0_DelayCount_2_inst_lut3_321_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_150 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_149,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_2_60_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_132_122 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_149,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_132
    );
  TriggerDelay0_DelayCount_2_60_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_60_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_60_CYINIT_123 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_58_CYMUXG,
      O => TriggerDelay0_DelayCount_2_60_CYINIT
    );
  TriggerDelay0_DelayCount_2_62_LOGIC_ONE_124 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_62_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_151_125 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_62_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_33,
      O => TriggerDelay0_DelayCount_2_inst_cy_151
    );
  TriggerDelay0_DelayCount_2_inst_sum_133_126 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_62_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_33,
      O => TriggerDelay0_DelayCount_2_inst_sum_133
    );
  TriggerDelay0_DelayCount_2_inst_lut3_331 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_5,
      ADR1 => TriggerDelay0_DelayCount_2_62,
      ADR2 => N50528,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_2_inst_lut3_33
    );
  TriggerDelay0_DelayCount_2_inst_lut3_341 : X_LUT4
    generic map(
      INIT => X"0F47"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_6,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => TriggerDelay0_DelayCount_2_63,
      ADR3 => N50903,
      O => TriggerDelay0_DelayCount_2_inst_lut3_341_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_152 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_151,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_2_62_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_134_127 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_151,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_134
    );
  TriggerDelay0_DelayCount_2_62_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_62_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_62_CYINIT_128 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_60_CYMUXG,
      O => TriggerDelay0_DelayCount_2_62_CYINIT
    );
  TriggerDelay0_DelayCount_2_64_LOGIC_ONE_129 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_64_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_153_130 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_64_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_35,
      O => TriggerDelay0_DelayCount_2_inst_cy_153
    );
  TriggerDelay0_DelayCount_2_inst_sum_135_131 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_64_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_35,
      O => TriggerDelay0_DelayCount_2_inst_sum_135
    );
  TriggerDelay0_DelayCount_2_inst_lut3_351 : X_LUT4
    generic map(
      INIT => X"1D0F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_7,
      ADR1 => N50564,
      ADR2 => TriggerDelay0_DelayCount_2_64,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_2_inst_lut3_35
    );
  TriggerDelay0_DelayCount_2_inst_lut3_361 : X_LUT4
    generic map(
      INIT => X"515D"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_65,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => N50903,
      ADR3 => PerLBusInterface0_RegBank_1_8,
      O => TriggerDelay0_DelayCount_2_inst_lut3_36
    );
  TriggerDelay0_DelayCount_2_inst_cy_154 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_153,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_36,
      O => TriggerDelay0_DelayCount_2_64_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_136_132 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_153,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_36,
      O => TriggerDelay0_DelayCount_2_inst_sum_136
    );
  TriggerDelay0_DelayCount_2_64_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_64_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_64_CYINIT_133 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_62_CYMUXG,
      O => TriggerDelay0_DelayCount_2_64_CYINIT
    );
  TriggerDelay0_DelayCount_2_66_LOGIC_ONE_134 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_66_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_155_135 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_66_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_37,
      O => TriggerDelay0_DelayCount_2_inst_cy_155
    );
  TriggerDelay0_DelayCount_2_inst_sum_137_136 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_66_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_37,
      O => TriggerDelay0_DelayCount_2_inst_sum_137
    );
  TriggerDelay0_DelayCount_2_inst_lut3_371 : X_LUT4
    generic map(
      INIT => X"3533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_9,
      ADR1 => TriggerDelay0_DelayCount_2_66,
      ADR2 => N50903,
      ADR3 => TriggerDelay0_TriggerRegs_1_1,
      O => TriggerDelay0_DelayCount_2_inst_lut3_37
    );
  TriggerDelay0_DelayCount_2_inst_lut3_381 : X_LUT4
    generic map(
      INIT => X"5533"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_10,
      ADR1 => TriggerDelay0_DelayCount_2_67,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0024,
      O => TriggerDelay0_DelayCount_2_inst_lut3_381_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_156 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_155,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_2_66_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_138_137 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_155,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_138
    );
  TriggerDelay0_DelayCount_2_66_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_66_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_66_CYINIT_138 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_64_CYMUXG,
      O => TriggerDelay0_DelayCount_2_66_CYINIT
    );
  TriggerDelay0_DelayCount_2_68_LOGIC_ONE_139 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_68_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_157_140 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_68_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_2_inst_cy_157
    );
  TriggerDelay0_DelayCount_2_inst_sum_139_141 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_68_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_139
    );
  TriggerDelay0_DelayCount_2_inst_lut3_391 : X_LUT4
    generic map(
      INIT => X"0F33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_2_68,
      ADR2 => PerLBusInterface0_RegBank_1_11,
      ADR3 => TriggerDelay0_n0024,
      O => TriggerDelay0_DelayCount_2_inst_lut3_391_O
    );
  TriggerDelay0_DelayCount_2_inst_lut3_401 : X_LUT4
    generic map(
      INIT => X"330F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_1_12,
      ADR2 => TriggerDelay0_DelayCount_2_69,
      ADR3 => TriggerDelay0_n0024,
      O => TriggerDelay0_DelayCount_2_inst_lut3_401_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_158 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_157,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_2_68_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_140_142 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_157,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_140
    );
  TriggerDelay0_DelayCount_2_68_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_68_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_68_CYINIT_143 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_66_CYMUXG,
      O => TriggerDelay0_DelayCount_2_68_CYINIT
    );
  TriggerDelay0_DelayCount_2_70_LOGIC_ONE_144 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_2_70_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_2_inst_cy_159_145 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_70_CYINIT,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_2_inst_cy_159
    );
  TriggerDelay0_DelayCount_2_inst_sum_141_146 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_70_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_141
    );
  TriggerDelay0_DelayCount_2_inst_lut3_411 : X_LUT4
    generic map(
      INIT => X"505F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_13,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0024,
      ADR3 => TriggerDelay0_DelayCount_2_70,
      O => TriggerDelay0_DelayCount_2_inst_lut3_411_O
    );
  TriggerDelay0_DelayCount_2_inst_lut3_421 : X_LUT4
    generic map(
      INIT => X"505F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_14,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0024,
      ADR3 => TriggerDelay0_DelayCount_2_71,
      O => TriggerDelay0_DelayCount_2_inst_lut3_421_O
    );
  TriggerDelay0_DelayCount_2_inst_cy_160 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_2_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_2_inst_cy_159,
      SEL => TriggerDelay0_DelayCount_2_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_2_70_CYMUXG
    );
  TriggerDelay0_DelayCount_2_inst_sum_142_147 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_inst_cy_159,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_142
    );
  TriggerDelay0_DelayCount_2_70_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_70_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_70_CYINIT_148 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_68_CYMUXG,
      O => TriggerDelay0_DelayCount_2_70_CYINIT
    );
  TriggerDelay0_DelayCount_2_inst_sum_143_149 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_72_CYINIT,
      I1 => TriggerDelay0_DelayCount_2_inst_lut3_431_O,
      O => TriggerDelay0_DelayCount_2_inst_sum_143
    );
  TriggerDelay0_DelayCount_2_inst_lut3_431 : X_LUT4
    generic map(
      INIT => X"05F5"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_72,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0024,
      ADR3 => PerLBusInterface0_RegBank_1_15,
      O => TriggerDelay0_DelayCount_2_inst_lut3_431_O
    );
  TriggerDelay0_n00801 : X_LUT4
    generic map(
      INIT => X"FAF0"
    )
    port map (
      ADR0 => TriggerDelay0_n0049,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0024,
      ADR3 => TriggerDelay0_DelayActive(2),
      O => TriggerDelay0_DelayCount_2_72_GROM
    );
  TriggerDelay0_DelayCount_2_72_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_72_GROM,
      O => TriggerDelay0_n0080
    );
  TriggerDelay0_DelayCount_2_72_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_2_72_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_2_72_CYINIT_150 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_2_70_CYMUXG,
      O => TriggerDelay0_DelayCount_2_72_CYINIT
    );
  TriggerDelay0_n005062 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_72,
      ADR1 => TriggerDelay0_DelayCount_1_70,
      ADR2 => TriggerDelay0_DelayCount_1_69,
      ADR3 => TriggerDelay0_DelayCount_1_71,
      O => CHOICE565_GROM
    );
  CHOICE565_YUSED : X_BUF
    port map (
      I => CHOICE565_GROM,
      O => CHOICE565
    );
  TriggerDelay0_n005125 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_63,
      ADR1 => TriggerDelay0_DelayCount_0_61,
      ADR2 => TriggerDelay0_DelayCount_0_64,
      ADR3 => TriggerDelay0_DelayCount_0_62,
      O => CHOICE581_GROM
    );
  CHOICE581_YUSED : X_BUF
    port map (
      I => CHOICE581_GROM,
      O => CHOICE581
    );
  CHOICE589_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE589_FROM
    );
  TriggerDelay0_n005149 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_67,
      ADR1 => TriggerDelay0_DelayCount_0_66,
      ADR2 => TriggerDelay0_DelayCount_0_65,
      ADR3 => TriggerDelay0_DelayCount_0_68,
      O => CHOICE589_GROM
    );
  CHOICE589_XUSED : X_BUF
    port map (
      I => CHOICE589_FROM,
      O => CHOICE589_X
    );
  CHOICE589_YUSED : X_BUF
    port map (
      I => CHOICE589_GROM,
      O => CHOICE589
    );
  TriggerDelay0_n005162 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_71,
      ADR1 => TriggerDelay0_DelayCount_0_72,
      ADR2 => TriggerDelay0_DelayCount_0_70,
      ADR3 => TriggerDelay0_DelayCount_0_69,
      O => CHOICE596_GROM
    );
  CHOICE596_YUSED : X_BUF
    port map (
      I => CHOICE596_GROM,
      O => CHOICE596
    );
  FocusUnitCtrl0_n00482 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => FocusUnitCtrl0_Rx_nTx,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE600_GROM
    );
  CHOICE600_YUSED : X_BUF
    port map (
      I => CHOICE600_GROM,
      O => CHOICE600
    );
  FocusUnitCtrl0_n00473 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd4,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd1,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd10,
      O => CHOICE608_FROM
    );
  FocusUnitCtrl0_Ker289221 : X_LUT4
    generic map(
      INIT => X"FEFE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd10,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd4,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd1,
      ADR3 => VCC,
      O => CHOICE608_GROM
    );
  CHOICE608_XUSED : X_BUF
    port map (
      I => CHOICE608_FROM,
      O => CHOICE608
    );
  CHOICE608_YUSED : X_BUF
    port map (
      I => CHOICE608_GROM,
      O => FocusUnitCtrl0_N28924
    );
  BScanCtrl0_n003450 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => BScanCtrl0_ScanCount_40,
      ADR1 => PerLBusInterface0_RegBank_4_20,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE658_FROM
    );
  BScanCtrl0_n003459 : X_LUT4
    generic map(
      INIT => X"4020"
    )
    port map (
      ADR0 => BScanCtrl0_ScanCount_41,
      ADR1 => PerLBusInterface0_RegBank_4_21,
      ADR2 => CHOICE658,
      ADR3 => BScanCtrl0_ScanCount_42,
      O => CHOICE658_GROM
    );
  CHOICE658_XUSED : X_BUF
    port map (
      I => CHOICE658_FROM,
      O => CHOICE658
    );
  CHOICE658_YUSED : X_BUF
    port map (
      I => CHOICE658_GROM,
      O => CHOICE659
    );
  BScanCtrl0_n003489 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => BScanCtrl0_ScanCount_46,
      ADR1 => BScanCtrl0_ScanCount_44,
      ADR2 => BScanCtrl0_ScanCount_43,
      ADR3 => BScanCtrl0_ScanCount_45,
      O => CHOICE667_GROM
    );
  CHOICE667_YUSED : X_BUF
    port map (
      I => CHOICE667_GROM,
      O => CHOICE667
    );
  BScanCtrl0_n0034111 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(1),
      ADR1 => BScanCtrl0_RxCount(0),
      ADR2 => BScanCtrl0_RxCount(2),
      ADR3 => BScanCtrl0_RxCount(3),
      O => CHOICE673_FROM
    );
  BScanCtrl0_n0034114 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(6),
      ADR1 => BScanCtrl0_RxCount(4),
      ADR2 => BScanCtrl0_RxCount(5),
      ADR3 => CHOICE673,
      O => CHOICE673_GROM
    );
  CHOICE673_XUSED : X_BUF
    port map (
      I => CHOICE673_FROM,
      O => CHOICE673
    );
  CHOICE673_YUSED : X_BUF
    port map (
      I => CHOICE673_GROM,
      O => CHOICE674
    );
  EncoderMonitor0_n04330 : X_LUT4
    generic map(
      INIT => X"FAFA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncDec(1),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_EncInc(1),
      ADR3 => VCC,
      O => CHOICE679_GROM
    );
  CHOICE679_YUSED : X_BUF
    port map (
      I => CHOICE679_GROM,
      O => CHOICE679
    );
  EncoderMonitor0_n04335 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_9,
      ADR1 => EncoderMonitor0_EncCounts_1_10,
      ADR2 => EncoderMonitor0_EncCounts_1_11,
      ADR3 => EncoderMonitor0_EncCounts_1_8,
      O => CHOICE682_GROM
    );
  CHOICE682_YUSED : X_BUF
    port map (
      I => CHOICE682_GROM,
      O => CHOICE682
    );
  EncoderMonitor0_n043310 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_13,
      ADR1 => EncoderMonitor0_EncCounts_1_14,
      ADR2 => EncoderMonitor0_EncCounts_1_15,
      ADR3 => EncoderMonitor0_EncCounts_1_12,
      O => CHOICE685_GROM
    );
  CHOICE685_YUSED : X_BUF
    port map (
      I => CHOICE685_GROM,
      O => CHOICE685
    );
  EncoderMonitor0_n043327 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_22,
      ADR1 => EncoderMonitor0_EncCounts_1_21,
      ADR2 => EncoderMonitor0_EncCounts_1_23,
      ADR3 => EncoderMonitor0_EncCounts_1_20,
      O => CHOICE692_GROM
    );
  CHOICE692_YUSED : X_BUF
    port map (
      I => CHOICE692_GROM,
      O => CHOICE692
    );
  EncoderMonitor0_n043355 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_31,
      ADR1 => EncoderMonitor0_EncCounts_1_30,
      ADR2 => EncoderMonitor0_EncCounts_1_29,
      ADR3 => EncoderMonitor0_EncCounts_1_28,
      O => CHOICE700_GROM
    );
  CHOICE700_YUSED : X_BUF
    port map (
      I => CHOICE700_GROM,
      O => CHOICE700
    );
  EncoderMonitor0_n043367 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_35,
      ADR1 => EncoderMonitor0_EncCounts_1_34,
      ADR2 => EncoderMonitor0_EncCounts_1_32,
      ADR3 => EncoderMonitor0_EncCounts_1_33,
      O => CHOICE704_GROM
    );
  CHOICE704_YUSED : X_BUF
    port map (
      I => CHOICE704_GROM,
      O => CHOICE704
    );
  CHOICE708_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE708_FROM
    );
  EncoderMonitor0_n043375 : X_LUT4
    generic map(
      INIT => X"FEFF"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_38,
      ADR1 => EncoderMonitor0_EncCounts_1_36,
      ADR2 => EncoderMonitor0_EncCounts_1_37,
      ADR3 => EncoderMonitor0_EncCounts_1_39,
      O => CHOICE708_GROM
    );
  CHOICE708_XUSED : X_BUF
    port map (
      I => CHOICE708_FROM,
      O => CHOICE708_X
    );
  CHOICE708_YUSED : X_BUF
    port map (
      I => CHOICE708_GROM,
      O => CHOICE708
    );
  EncoderMonitor0_n043397 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE685,
      ADR1 => CHOICE693,
      ADR2 => CHOICE682,
      ADR3 => CHOICE710,
      O => CHOICE711_FROM
    );
  EncoderMonitor0_n0433130 : X_LUT4
    generic map(
      INIT => X"C888"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(1),
      ADR1 => EncoderMonitor0_ClkEn2,
      ADR2 => CHOICE679,
      ADR3 => CHOICE711,
      O => CHOICE711_GROM
    );
  CHOICE711_XUSED : X_BUF
    port map (
      I => CHOICE711_FROM,
      O => CHOICE711
    );
  CHOICE711_YUSED : X_BUF
    port map (
      I => CHOICE711_GROM,
      O => EncoderMonitor0_n0433
    );
  EncoderMonitor0_n043710 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_15,
      ADR1 => EncoderMonitor0_EncCounts_2_14,
      ADR2 => EncoderMonitor0_EncCounts_2_13,
      ADR3 => EncoderMonitor0_EncCounts_2_12,
      O => CHOICE721_GROM
    );
  CHOICE721_YUSED : X_BUF
    port map (
      I => CHOICE721_GROM,
      O => CHOICE721
    );
  EncoderMonitor0_n043727 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_22,
      ADR1 => EncoderMonitor0_EncCounts_2_21,
      ADR2 => EncoderMonitor0_EncCounts_2_20,
      ADR3 => EncoderMonitor0_EncCounts_2_23,
      O => CHOICE728_GROM
    );
  CHOICE728_YUSED : X_BUF
    port map (
      I => CHOICE728_GROM,
      O => CHOICE728
    );
  EncoderMonitor0_n043755 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_30,
      ADR1 => EncoderMonitor0_EncCounts_2_29,
      ADR2 => EncoderMonitor0_EncCounts_2_31,
      ADR3 => EncoderMonitor0_EncCounts_2_28,
      O => CHOICE736_GROM
    );
  CHOICE736_YUSED : X_BUF
    port map (
      I => CHOICE736_GROM,
      O => CHOICE736
    );
  EncoderMonitor0_n043767 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_35,
      ADR1 => EncoderMonitor0_EncCounts_2_32,
      ADR2 => EncoderMonitor0_EncCounts_2_34,
      ADR3 => EncoderMonitor0_EncCounts_2_33,
      O => CHOICE740_GROM
    );
  CHOICE740_YUSED : X_BUF
    port map (
      I => CHOICE740_GROM,
      O => CHOICE740
    );
  EncoderMonitor0_n043775 : X_LUT4
    generic map(
      INIT => X"FFFB"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_37,
      ADR1 => EncoderMonitor0_EncCounts_2_39,
      ADR2 => EncoderMonitor0_EncCounts_2_38,
      ADR3 => EncoderMonitor0_EncCounts_2_36,
      O => CHOICE744_GROM
    );
  CHOICE744_YUSED : X_BUF
    port map (
      I => CHOICE744_GROM,
      O => CHOICE744
    );
  EncoderMonitor0_n043797 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE729,
      ADR1 => CHOICE746,
      ADR2 => CHOICE718,
      ADR3 => CHOICE721,
      O => CHOICE747_FROM
    );
  EncoderMonitor0_n0437130 : X_LUT4
    generic map(
      INIT => X"A888"
    )
    port map (
      ADR0 => EncoderMonitor0_ClkEn2,
      ADR1 => EncoderMonitor0_EncoderReset(2),
      ADR2 => CHOICE715,
      ADR3 => CHOICE747,
      O => CHOICE747_GROM
    );
  CHOICE747_XUSED : X_BUF
    port map (
      I => CHOICE747_FROM,
      O => CHOICE747
    );
  CHOICE747_YUSED : X_BUF
    port map (
      I => CHOICE747_GROM,
      O => EncoderMonitor0_n0437
    );
  EncoderMonitor0_n04280 : X_LUT4
    generic map(
      INIT => X"FAFA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncDec(0),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => CHOICE751_GROM
    );
  CHOICE751_YUSED : X_BUF
    port map (
      I => CHOICE751_GROM,
      O => CHOICE751
    );
  EncoderMonitor0_n04285 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_10,
      ADR1 => EncoderMonitor0_EncCounts_0_11,
      ADR2 => EncoderMonitor0_EncCounts_0_8,
      ADR3 => EncoderMonitor0_EncCounts_0_9,
      O => CHOICE754_GROM
    );
  CHOICE754_YUSED : X_BUF
    port map (
      I => CHOICE754_GROM,
      O => CHOICE754
    );
  EncoderMonitor0_n042827 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_23,
      ADR1 => EncoderMonitor0_EncCounts_0_22,
      ADR2 => EncoderMonitor0_EncCounts_0_20,
      ADR3 => EncoderMonitor0_EncCounts_0_21,
      O => CHOICE764_GROM
    );
  CHOICE764_YUSED : X_BUF
    port map (
      I => CHOICE764_GROM,
      O => CHOICE764
    );
  EncoderMonitor0_n042855 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_28,
      ADR1 => EncoderMonitor0_EncCounts_0_30,
      ADR2 => EncoderMonitor0_EncCounts_0_31,
      ADR3 => EncoderMonitor0_EncCounts_0_29,
      O => CHOICE772_GROM
    );
  CHOICE772_YUSED : X_BUF
    port map (
      I => CHOICE772_GROM,
      O => CHOICE772
    );
  EncoderMonitor0_n042867 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_34,
      ADR1 => EncoderMonitor0_EncCounts_0_32,
      ADR2 => EncoderMonitor0_EncCounts_0_33,
      ADR3 => EncoderMonitor0_EncCounts_0_35,
      O => CHOICE776_GROM
    );
  CHOICE776_YUSED : X_BUF
    port map (
      I => CHOICE776_GROM,
      O => CHOICE776
    );
  EncoderMonitor0_n042875 : X_LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_36,
      ADR1 => EncoderMonitor0_EncCounts_0_37,
      ADR2 => EncoderMonitor0_EncCounts_0_39,
      ADR3 => EncoderMonitor0_EncCounts_0_38,
      O => CHOICE780_GROM
    );
  CHOICE780_YUSED : X_BUF
    port map (
      I => CHOICE780_GROM,
      O => CHOICE780
    );
  EncoderMonitor0_n042897 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE757,
      ADR1 => CHOICE765,
      ADR2 => CHOICE754,
      ADR3 => CHOICE782,
      O => CHOICE783_FROM
    );
  EncoderMonitor0_n0428130 : X_LUT4
    generic map(
      INIT => X"A888"
    )
    port map (
      ADR0 => EncoderMonitor0_ClkEn2,
      ADR1 => EncoderMonitor0_EncoderReset(0),
      ADR2 => CHOICE751,
      ADR3 => CHOICE783,
      O => CHOICE783_GROM
    );
  CHOICE783_XUSED : X_BUF
    port map (
      I => CHOICE783_FROM,
      O => CHOICE783
    );
  CHOICE783_YUSED : X_BUF
    port map (
      I => CHOICE783_GROM,
      O => EncoderMonitor0_n0428
    );
  CHOICE793_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE793_FROM
    );
  BScanCtrl0_n004512 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(12),
      ADR1 => BScanCtrl0_RepCount(10),
      ADR2 => BScanCtrl0_RepCount(15),
      ADR3 => BScanCtrl0_RepCount(11),
      O => CHOICE793_GROM
    );
  CHOICE793_XUSED : X_BUF
    port map (
      I => CHOICE793_FROM,
      O => CHOICE793_X
    );
  CHOICE793_YUSED : X_BUF
    port map (
      I => CHOICE793_GROM,
      O => CHOICE793
    );
  CHOICE800_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE800_FROM
    );
  BScanCtrl0_n004525 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(3),
      ADR1 => BScanCtrl0_RepCount(4),
      ADR2 => BScanCtrl0_RepCount(13),
      ADR3 => BScanCtrl0_RepCount(2),
      O => CHOICE800_GROM
    );
  CHOICE800_XUSED : X_BUF
    port map (
      I => CHOICE800_FROM,
      O => CHOICE800_X
    );
  CHOICE800_YUSED : X_BUF
    port map (
      I => CHOICE800_GROM,
      O => CHOICE800
    );
  BScanCtrl0_n004549 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(8),
      ADR1 => BScanCtrl0_RepCount(7),
      ADR2 => BScanCtrl0_RepCount(6),
      ADR3 => BScanCtrl0_RepCount(5),
      O => CHOICE808_GROM
    );
  CHOICE808_YUSED : X_BUF
    port map (
      I => CHOICE808_GROM,
      O => CHOICE808
    );
  FocusUnitCtrl0_n0046_2_5 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(2),
      ADR1 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR2 => DelayValData(2),
      ADR3 => FocusUnitCtrl0_CtrlState_FFd7,
      O => CHOICE837_FROM
    );
  FocusUnitCtrl0_n0046_1_5 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(1),
      ADR1 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR2 => DelayValData(1),
      ADR3 => FocusUnitCtrl0_CtrlState_FFd7,
      O => CHOICE837_GROM
    );
  CHOICE837_XUSED : X_BUF
    port map (
      I => CHOICE837_FROM,
      O => CHOICE837
    );
  CHOICE837_YUSED : X_BUF
    port map (
      I => CHOICE837_GROM,
      O => CHOICE823
    );
  FocusUnitCtrl0_n0046_3_5 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR2 => DelayValData(3),
      ADR3 => FocusUnitCtrl0_DelayValAddr(3),
      O => CHOICE844_FROM
    );
  FocusUnitCtrl0_n0046_0_5 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(0),
      ADR1 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR2 => DelayValData(0),
      ADR3 => FocusUnitCtrl0_CtrlState_FFd12,
      O => CHOICE844_GROM
    );
  CHOICE844_XUSED : X_BUF
    port map (
      I => CHOICE844_FROM,
      O => CHOICE844
    );
  CHOICE844_YUSED : X_BUF
    port map (
      I => CHOICE844_GROM,
      O => CHOICE830
    );
  CLKDLL0 : X_CLKDLL
    generic map(
      CLKDV_DIVIDE => 2.0,
      DUTY_CYCLE_CORRECTION => TRUE,
      MAXPERCLKIN => 40000 ps
    )
    port map (
      RST => pZ0_IBUF,
      CLK0 => SampleClk_NoBuff,
      CLK180 => CLKDLL0_CLK180,
      CLK270 => CLKDLL0_CLK270,
      CLK2X => Sample2xClk_NoBuff,
      CLK90 => CLKDLL0_CLK90,
      CLKDV => CLKDLL0_CLKDV,
      CLKFB => Sample2xClk,
      CLKIN => SampleClkIn,
      LOCKED => Sample2xClkValid
    );
  DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ONE_151 : X_ONE
    port map (
      O => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ONE
    );
  DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO_152 : X_ZERO
    port map (
      O => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO
    );
  DualPortRam0_Mram_Ram_inst_ramb_0 : X_RAMB4_S16_S16
    generic map(
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
      SETUP_ALL => 3737 ps
    )
    port map (
      CLKA => LCLK,
      CLKB => SampleClk,
      ENA => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ONE,
      ENB => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ONE,
      RSTA => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO,
      RSTB => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO,
      WEA => PerLBusInterface0_BlkRamWrite,
      WEB => DualPortRam0_Mram_Ram_inst_ramb_0_LOGIC_ZERO,
      GSR => GSR,
      ADDRA(7) => EncoderMonitor0_EncoderReset(3),
      ADDRA(6) => PerLBusInterface0_RegBank_6_14,
      ADDRA(5) => PerLBusInterface0_RegBank_6_13,
      ADDRA(4) => PerLBusInterface0_RegBank_6_12,
      ADDRA(3) => PerLBusInterface0_RegBank_6_11,
      ADDRA(2) => PerLBusInterface0_RegBank_6_10,
      ADDRA(1) => PerLBusInterface0_RegBank_6_9,
      ADDRA(0) => PerLBusInterface0_RegBank_6_8,
      ADDRB(7) => EncoderMonitor0_EncoderReset(3),
      ADDRB(6) => TxCountMux(6),
      ADDRB(5) => TxCountMux(5),
      ADDRB(4) => TxCountMux(4),
      ADDRB(3) => TxCountMux(3),
      ADDRB(2) => TxCountMux(2),
      ADDRB(1) => TxCountMux(1),
      ADDRB(0) => TxCountMux(0),
      DIA(15) => EncoderMonitor0_EncoderReset(3),
      DIA(14) => EncoderMonitor0_EncoderReset(3),
      DIA(13) => EncoderMonitor0_EncoderReset(3),
      DIA(12) => EncoderMonitor0_EncoderReset(3),
      DIA(11) => EncoderMonitor0_EncoderReset(3),
      DIA(10) => EncoderMonitor0_EncoderReset(3),
      DIA(9) => EncoderMonitor0_EncoderReset(3),
      DIA(8) => EncoderMonitor0_EncoderReset(3),
      DIA(7) => PerLBusInterface0_RegBank_6_7,
      DIA(6) => PerLBusInterface0_RegBank_6_6,
      DIA(5) => PerLBusInterface0_RegBank_6_5,
      DIA(4) => PerLBusInterface0_RegBank_6_4,
      DIA(3) => PerLBusInterface0_RegBank_6_3,
      DIA(2) => PerLBusInterface0_RegBank_6_2,
      DIA(1) => PerLBusInterface0_RegBank_6_1,
      DIA(0) => PerLBusInterface0_RegBank_6_0,
      DIB(15) => EncoderMonitor0_EncoderReset(3),
      DIB(14) => EncoderMonitor0_EncoderReset(3),
      DIB(13) => EncoderMonitor0_EncoderReset(3),
      DIB(12) => EncoderMonitor0_EncoderReset(3),
      DIB(11) => EncoderMonitor0_EncoderReset(3),
      DIB(10) => EncoderMonitor0_EncoderReset(3),
      DIB(9) => EncoderMonitor0_EncoderReset(3),
      DIB(8) => EncoderMonitor0_EncoderReset(3),
      DIB(7) => EncoderMonitor0_EncoderReset(3),
      DIB(6) => EncoderMonitor0_EncoderReset(3),
      DIB(5) => EncoderMonitor0_EncoderReset(3),
      DIB(4) => EncoderMonitor0_EncoderReset(3),
      DIB(3) => EncoderMonitor0_EncoderReset(3),
      DIB(2) => EncoderMonitor0_EncoderReset(3),
      DIB(1) => EncoderMonitor0_EncoderReset(3),
      DIB(0) => EncoderMonitor0_EncoderReset(3),
      DOA(15) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA15,
      DOA(14) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA14,
      DOA(13) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA13,
      DOA(12) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA12,
      DOA(11) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA11,
      DOA(10) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA10,
      DOA(9) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA9,
      DOA(8) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA8,
      DOA(7) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA7,
      DOA(6) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA6,
      DOA(5) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA5,
      DOA(4) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA4,
      DOA(3) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA3,
      DOA(2) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA2,
      DOA(1) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA1,
      DOA(0) => DualPortRam0_Mram_Ram_inst_ramb_0_DOA0,
      DOB(15) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB15,
      DOB(14) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB14,
      DOB(13) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB13,
      DOB(12) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB12,
      DOB(11) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB11,
      DOB(10) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB10,
      DOB(9) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB9,
      DOB(8) => DualPortRam0_Mram_Ram_inst_ramb_0_DOB8,
      DOB(7) => ElementNumOut(7),
      DOB(6) => ElementNumOut(6),
      DOB(5) => ElementNumOut(5),
      DOB(4) => ElementNumOut(4),
      DOB(3) => ElementNumOut(3),
      DOB(2) => ElementNumOut(2),
      DOB(1) => ElementNumOut(1),
      DOB(0) => ElementNumOut(0)
    );
  Encoder0In_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => Encoder0In_1_SRMUX_OUTPUTNOT
    );
  Encoder1In_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => Encoder1In_1_SRMUX_OUTPUTNOT
    );
  Encoder2In_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => Encoder2In_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Ker266781 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => EncoderMonitor0_DecHysterisis,
      ADR1 => EncoderMonitor0_SelEncInc,
      ADR2 => EncoderMonitor0_vTrigCountMin,
      ADR3 => EncoderMonitor0_SelEncDec,
      O => EncoderMonitor0_BeginShift_FROM
    );
  EncoderMonitor0_n02751 : X_LUT4
    generic map(
      INIT => X"BAAA"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData,
      ADR1 => EncoderMonitor0_SelEncReset,
      ADR2 => EncoderMonitor0_ClkEn2,
      ADR3 => EncoderMonitor0_N26680,
      O => EncoderMonitor0_BeginShift_GROM
    );
  EncoderMonitor0_BeginShift_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_BeginShift_FROM,
      O => EncoderMonitor0_N26680
    );
  EncoderMonitor0_BeginShift_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_BeginShift_GROM,
      O => EncoderMonitor0_n0275
    );
  EncoderMonitor0_BeginShift_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_BeginShift_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n02811 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => EncoderMonitor0_ClkEnCount(0),
      ADR1 => EncoderMonitor0_ClkEnCount(1),
      ADR2 => EncoderMonitor0_ClkEnCount(2),
      ADR3 => EncoderMonitor0_ClkEnCount(3),
      O => EncoderMonitor0_n0281
    );
  EncoderMonitor0_ClkEn2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ClkEn2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ClkEnCount_0_LOGIC_ZERO_153 : X_ZERO
    port map (
      O => EncoderMonitor0_ClkEnCount_0_LOGIC_ZERO
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_0_154 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => EncoderMonitor0_ClkEnCount_0_LOGIC_ZERO,
      SEL => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_lut2_0,
      O => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_0
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ClkEnCount(0),
      O => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_lut2_0
    );
  EncoderMonitor0_ClkEnCount_0_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ClkEnCount(1),
      O => EncoderMonitor0_ClkEnCount_0_GROM
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_1 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_0,
      SEL => EncoderMonitor0_ClkEnCount_0_GROM,
      O => EncoderMonitor0_ClkEnCount_0_CYMUXG
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_sum_1 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_0,
      I1 => EncoderMonitor0_ClkEnCount_0_GROM,
      O => EncoderMonitor0_ClkEnCount_n0000(1)
    );
  EncoderMonitor0_ClkEnCount_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ClkEnCount_0_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ClkEnCount_2_LOGIC_ZERO_155 : X_ZERO
    port map (
      O => EncoderMonitor0_ClkEnCount_2_LOGIC_ZERO
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_2_156 : X_MUX2
    port map (
      IA => EncoderMonitor0_ClkEnCount_2_LOGIC_ZERO,
      IB => EncoderMonitor0_ClkEnCount_2_CYINIT,
      SEL => EncoderMonitor0_ClkEnCount_2_FROM,
      O => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_2
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_sum_2 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_2_CYINIT,
      I1 => EncoderMonitor0_ClkEnCount_2_FROM,
      O => EncoderMonitor0_ClkEnCount_n0000(2)
    );
  EncoderMonitor0_ClkEnCount_2_F : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ClkEnCount(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_ClkEnCount_2_FROM
    );
  EncoderMonitor0_ClkEnCount_3_rt_157 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ClkEnCount(3),
      ADR3 => VCC,
      O => EncoderMonitor0_ClkEnCount_3_rt
    );
  EncoderMonitor0_ClkEnCount_Madd_n0000_inst_sum_3 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_cy_2,
      I1 => EncoderMonitor0_ClkEnCount_3_rt,
      O => EncoderMonitor0_ClkEnCount_n0000(3)
    );
  EncoderMonitor0_ClkEnCount_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ClkEnCount_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ClkEnCount_2_CYINIT_158 : X_BUF
    port map (
      I => EncoderMonitor0_ClkEnCount_0_CYMUXG,
      O => EncoderMonitor0_ClkEnCount_2_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_40_159 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_2,
      IB => EncoderMonitor0_EncCounts_0_10_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_40
    );
  EncoderMonitor0_EncCounts_0_inst_sum_30_160 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_10_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_30
    );
  EncoderMonitor0_EncCounts_0_inst_multand_2_161 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_10,
      O => EncoderMonitor0_EncCounts_0_inst_multand_2
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_101 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_10,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_101_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_111 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_11,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_111_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_3_162 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_11,
      O => EncoderMonitor0_EncCounts_0_inst_multand_3
    );
  EncoderMonitor0_EncCounts_0_inst_cy_41 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_3,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_40,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_0_10_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_31_163 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_40,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_31
    );
  EncoderMonitor0_EncCounts_0_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_10_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_10_CYINIT_164 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_8_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_10_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_42_165 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_4,
      IB => EncoderMonitor0_EncCounts_0_12_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_42
    );
  EncoderMonitor0_EncCounts_0_inst_sum_32_166 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_12_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_32
    );
  EncoderMonitor0_EncCounts_0_inst_multand_4_167 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_12,
      O => EncoderMonitor0_EncCounts_0_inst_multand_4
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_121 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_12,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_121_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_131 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_13,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_131_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_5_168 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_13,
      O => EncoderMonitor0_EncCounts_0_inst_multand_5
    );
  EncoderMonitor0_EncCounts_0_inst_cy_43 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_5,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_42,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_0_12_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_33_169 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_42,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_33
    );
  EncoderMonitor0_EncCounts_0_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_12_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_12_CYINIT_170 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_10_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_12_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_44_171 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_6,
      IB => EncoderMonitor0_EncCounts_0_14_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_44
    );
  EncoderMonitor0_EncCounts_0_inst_sum_34_172 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_14_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_34
    );
  EncoderMonitor0_EncCounts_0_inst_multand_6_173 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_14,
      O => EncoderMonitor0_EncCounts_0_inst_multand_6
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_141 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_14,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_141_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_151 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_15,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_151_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_7_174 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_15,
      O => EncoderMonitor0_EncCounts_0_inst_multand_7
    );
  EncoderMonitor0_EncCounts_0_inst_cy_45 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_7,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_44,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_0_14_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_35_175 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_44,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_35
    );
  EncoderMonitor0_EncCounts_0_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_14_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_14_CYINIT_176 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_12_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_14_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_46_177 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_8,
      IB => EncoderMonitor0_EncCounts_0_16_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_46
    );
  EncoderMonitor0_EncCounts_0_inst_sum_36_178 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_16_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_36
    );
  EncoderMonitor0_EncCounts_0_inst_multand_8_179 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_16,
      O => EncoderMonitor0_EncCounts_0_inst_multand_8
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_161 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_16,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_161_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_171 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_17,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_171_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_9_180 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_17,
      O => EncoderMonitor0_EncCounts_0_inst_multand_9
    );
  EncoderMonitor0_EncCounts_0_inst_cy_47 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_9,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_46,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_0_16_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_37_181 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_46,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_37
    );
  EncoderMonitor0_EncCounts_0_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_16_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_16_CYINIT_182 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_14_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_16_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_48_183 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_10,
      IB => EncoderMonitor0_EncCounts_0_18_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_48
    );
  EncoderMonitor0_EncCounts_0_inst_sum_38_184 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_18_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_38
    );
  EncoderMonitor0_EncCounts_0_inst_multand_10_185 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_18,
      O => EncoderMonitor0_EncCounts_0_inst_multand_10
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_181 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_18,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_181_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_191 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_19,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_191_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_11_186 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_19,
      O => EncoderMonitor0_EncCounts_0_inst_multand_11
    );
  EncoderMonitor0_EncCounts_0_inst_cy_49 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_11,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_48,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_0_18_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_39_187 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_48,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_39
    );
  EncoderMonitor0_EncCounts_0_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_18_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_18_CYINIT_188 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_16_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_18_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_50_189 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_12,
      IB => EncoderMonitor0_EncCounts_0_20_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_50
    );
  EncoderMonitor0_EncCounts_0_inst_sum_40_190 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_20_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_40
    );
  EncoderMonitor0_EncCounts_0_inst_multand_12_191 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_20,
      O => EncoderMonitor0_EncCounts_0_inst_multand_12
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_201 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_20,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_201_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_211 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_21,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_211_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_13_192 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_21,
      O => EncoderMonitor0_EncCounts_0_inst_multand_13
    );
  EncoderMonitor0_EncCounts_0_inst_cy_51 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_13,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_50,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_0_20_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_41_193 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_50,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_41
    );
  EncoderMonitor0_EncCounts_0_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_20_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_20_CYINIT_194 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_18_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_20_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_52_195 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_14,
      IB => EncoderMonitor0_EncCounts_0_22_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_52
    );
  EncoderMonitor0_EncCounts_0_inst_sum_42_196 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_22_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_42
    );
  EncoderMonitor0_EncCounts_0_inst_multand_14_197 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_22,
      O => EncoderMonitor0_EncCounts_0_inst_multand_14
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_221 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_22,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_221_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_231 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_23,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_231_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_15_198 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_23,
      O => EncoderMonitor0_EncCounts_0_inst_multand_15
    );
  EncoderMonitor0_EncCounts_0_inst_cy_53 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_15,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_52,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_0_22_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_43_199 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_52,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_43
    );
  EncoderMonitor0_EncCounts_0_22_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_22_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_22_CYINIT_200 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_20_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_22_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_54_201 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_16,
      IB => EncoderMonitor0_EncCounts_0_24_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_54
    );
  EncoderMonitor0_EncCounts_0_inst_sum_44_202 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_24_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_44
    );
  EncoderMonitor0_EncCounts_0_inst_multand_16_203 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_24,
      O => EncoderMonitor0_EncCounts_0_inst_multand_16
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_241 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_24,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_241_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_251 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_25,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_25
    );
  EncoderMonitor0_EncCounts_0_inst_multand_17_204 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_25,
      O => EncoderMonitor0_EncCounts_0_inst_multand_17
    );
  EncoderMonitor0_EncCounts_0_inst_cy_55 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_17,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_54,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_0_24_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_45_205 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_54,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_0_inst_sum_45
    );
  EncoderMonitor0_EncCounts_0_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_24_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_24_CYINIT_206 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_22_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_24_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_56_207 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_18,
      IB => EncoderMonitor0_EncCounts_0_26_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_0_inst_cy_56
    );
  EncoderMonitor0_EncCounts_0_inst_sum_46_208 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_26_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_0_inst_sum_46
    );
  EncoderMonitor0_EncCounts_0_inst_multand_18_209 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_26,
      O => EncoderMonitor0_EncCounts_0_inst_multand_18
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_261 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_26,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_26
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_271 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_27,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_27
    );
  EncoderMonitor0_EncCounts_0_inst_multand_19_210 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_27,
      O => EncoderMonitor0_EncCounts_0_inst_multand_19
    );
  EncoderMonitor0_EncCounts_0_inst_cy_57 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_19,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_56,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_0_26_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_47_211 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_56,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_0_inst_sum_47
    );
  EncoderMonitor0_EncCounts_0_26_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_26_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_26_CYINIT_212 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_24_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_26_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_58_213 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_20,
      IB => EncoderMonitor0_EncCounts_0_28_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_0_inst_cy_58
    );
  EncoderMonitor0_EncCounts_0_inst_sum_48_214 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_28_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_0_inst_sum_48
    );
  EncoderMonitor0_EncCounts_0_inst_multand_20_215 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_28,
      O => EncoderMonitor0_EncCounts_0_inst_multand_20
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_281 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_28,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_28
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_291 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_29,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_29
    );
  EncoderMonitor0_EncCounts_0_inst_multand_21_216 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_29,
      O => EncoderMonitor0_EncCounts_0_inst_multand_21
    );
  EncoderMonitor0_EncCounts_0_inst_cy_59 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_21,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_58,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_0_28_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_49_217 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_58,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_0_inst_sum_49
    );
  EncoderMonitor0_EncCounts_0_28_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_28_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_28_CYINIT_218 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_26_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_28_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_60_219 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_22,
      IB => EncoderMonitor0_EncCounts_0_30_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_0_inst_cy_60
    );
  EncoderMonitor0_EncCounts_0_inst_sum_50_220 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_30_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_0_inst_sum_50
    );
  EncoderMonitor0_EncCounts_0_inst_multand_22_221 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_30,
      O => EncoderMonitor0_EncCounts_0_inst_multand_22
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_301 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_30,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_30
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_311 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_31,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_31
    );
  EncoderMonitor0_EncCounts_0_inst_multand_23_222 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_31,
      O => EncoderMonitor0_EncCounts_0_inst_multand_23
    );
  EncoderMonitor0_EncCounts_0_inst_cy_61 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_23,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_60,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_0_30_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_51_223 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_60,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_0_inst_sum_51
    );
  EncoderMonitor0_EncCounts_0_30_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_30_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_30_CYINIT_224 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_28_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_30_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_62_225 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_24,
      IB => EncoderMonitor0_EncCounts_0_32_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_0_inst_cy_62
    );
  EncoderMonitor0_EncCounts_0_inst_sum_52_226 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_32_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_0_inst_sum_52
    );
  EncoderMonitor0_EncCounts_0_inst_multand_24_227 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_32,
      O => EncoderMonitor0_EncCounts_0_inst_multand_24
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_321 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_32,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_32
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_331 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_33,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_33
    );
  EncoderMonitor0_EncCounts_0_inst_multand_25_228 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_33,
      O => EncoderMonitor0_EncCounts_0_inst_multand_25
    );
  EncoderMonitor0_EncCounts_0_inst_cy_63 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_25,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_62,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_0_32_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_53_229 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_62,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_0_inst_sum_53
    );
  EncoderMonitor0_EncCounts_0_32_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_32_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_32_CYINIT_230 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_30_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_32_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_64_231 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_26,
      IB => EncoderMonitor0_EncCounts_0_34_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_0_inst_cy_64
    );
  EncoderMonitor0_EncCounts_0_inst_sum_54_232 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_34_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_0_inst_sum_54
    );
  EncoderMonitor0_EncCounts_0_inst_multand_26_233 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_34,
      O => EncoderMonitor0_EncCounts_0_inst_multand_26
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_341 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_34,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_34
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_351 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_35,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_35
    );
  EncoderMonitor0_EncCounts_0_inst_multand_27_234 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_35,
      O => EncoderMonitor0_EncCounts_0_inst_multand_27
    );
  EncoderMonitor0_EncCounts_0_inst_cy_65 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_27,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_64,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_0_34_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_55_235 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_64,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_0_inst_sum_55
    );
  EncoderMonitor0_EncCounts_0_34_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_34_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_34_CYINIT_236 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_32_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_34_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_66_237 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_28,
      IB => EncoderMonitor0_EncCounts_0_36_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_0_inst_cy_66
    );
  EncoderMonitor0_EncCounts_0_inst_sum_56_238 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_36_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_0_inst_sum_56
    );
  EncoderMonitor0_EncCounts_0_inst_multand_28_239 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_36,
      O => EncoderMonitor0_EncCounts_0_inst_multand_28
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_361 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_36,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_36
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_371 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_37,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_37
    );
  EncoderMonitor0_EncCounts_0_inst_multand_29_240 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_37,
      O => EncoderMonitor0_EncCounts_0_inst_multand_29
    );
  EncoderMonitor0_EncCounts_0_inst_cy_67 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_29,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_66,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_0_36_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_57_241 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_66,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_0_inst_sum_57
    );
  EncoderMonitor0_EncCounts_0_36_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_36_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_36_CYINIT_242 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_34_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_36_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_68_243 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_30,
      IB => EncoderMonitor0_EncCounts_0_38_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_0_inst_cy_68
    );
  EncoderMonitor0_EncCounts_0_inst_sum_58_244 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_38_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_0_inst_sum_58
    );
  EncoderMonitor0_EncCounts_0_inst_multand_30_245 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_0_38,
      O => EncoderMonitor0_EncCounts_0_inst_multand_30
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_381 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_38,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_0_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_38
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_391 : X_LUT4
    generic map(
      INIT => X"8822"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_inst_lut1_11_1,
      ADR1 => EncoderMonitor0_EncCounts_0_39,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_39
    );
  EncoderMonitor0_EncCounts_0_inst_sum_59_246 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_68,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_39,
      O => EncoderMonitor0_EncCounts_0_inst_sum_59
    );
  EncoderMonitor0_EncCounts_0_38_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_38_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_38_CYINIT_247 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_36_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_38_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_cy_38_248 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_0,
      IB => EncoderMonitor0_EncCounts_0_8_CYINIT,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_0_inst_cy_38
    );
  EncoderMonitor0_EncCounts_0_inst_sum_28_249 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_8_CYINIT,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_28
    );
  EncoderMonitor0_EncCounts_0_inst_multand_0_250 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_8,
      O => EncoderMonitor0_EncCounts_0_inst_multand_0
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_81 : X_LUT4
    generic map(
      INIT => X"4848"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_8,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_81_O
    );
  EncoderMonitor0_EncCounts_0_inst_lut4_91 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_9,
      ADR1 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(0),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut4_91_O
    );
  EncoderMonitor0_EncCounts_0_inst_multand_1_251 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_0_9,
      O => EncoderMonitor0_EncCounts_0_inst_multand_1
    );
  EncoderMonitor0_EncCounts_0_inst_cy_39 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_multand_1,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_38,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_0_8_CYMUXG
    );
  EncoderMonitor0_EncCounts_0_inst_sum_29_252 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_inst_cy_38,
      I1 => EncoderMonitor0_EncCounts_0_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_0_inst_sum_29
    );
  EncoderMonitor0_EncCounts_0_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_0_8_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_0_8_CYINIT_253 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_CYMUXG,
      O => EncoderMonitor0_EncCounts_0_8_CYINIT
    );
  EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ONE_254 : X_ONE
    port map (
      O => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ONE
    );
  EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ZERO_255 : X_ZERO
    port map (
      O => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ZERO
    );
  EncoderMonitor0_EncCounts_0_inst_cy_37 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ZERO,
      IB => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ONE,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut2_19,
      O => EncoderMonitor0_EncCounts_0_inst_cy_37_rt
    );
  EncoderMonitor0_EncCounts_0_inst_lut2_191 : X_LUT4
    generic map(
      INIT => X"0055"
    )
    port map (
      ADR0 => EncoderMonitor0_EncInc(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncoderReset(0),
      O => EncoderMonitor0_EncCounts_0_inst_lut2_19
    );
  EncoderMonitor0_EncCounts_0_inst_lut1_11_1_256 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_GROM
    );
  EncoderMonitor0_EncCounts_0_inst_lut1_11_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_GROM,
      O => EncoderMonitor0_EncCounts_0_inst_lut1_11_1
    );
  EncoderMonitor0_EncCounts_0_inst_cy_37_rt_257 : X_MUX2
    port map (
      IA => NLW_EncoderMonitor0_EncCounts_0_inst_cy_37_rt_IA_UNCONNECTED,
      IB => EncoderMonitor0_EncCounts_0_inst_cy_37_rt,
      SEL => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_LOGIC_ONE,
      O => EncoderMonitor0_EncCounts_0_inst_lut1_11_1_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_cy_40_258 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_2,
      IB => EncoderMonitor0_EncCounts_1_10_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_40
    );
  EncoderMonitor0_EncCounts_1_inst_sum_30_259 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_10_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_30
    );
  EncoderMonitor0_EncCounts_1_inst_multand_2_260 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_10,
      O => EncoderMonitor0_EncCounts_1_inst_multand_2
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_101 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_10,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(1),
      O => EncoderMonitor0_EncCounts_1_inst_lut4_101_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_111 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_11,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_111_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_3_261 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_11,
      O => EncoderMonitor0_EncCounts_1_inst_multand_3
    );
  EncoderMonitor0_EncCounts_1_inst_cy_41 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_3,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_40,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_1_10_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_31_262 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_40,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_31
    );
  EncoderMonitor0_EncCounts_1_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_10_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_10_CYINIT_263 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_8_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_10_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_42_264 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_4,
      IB => EncoderMonitor0_EncCounts_1_12_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_42
    );
  EncoderMonitor0_EncCounts_1_inst_sum_32_265 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_12_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_32
    );
  EncoderMonitor0_EncCounts_1_inst_multand_4_266 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_12,
      O => EncoderMonitor0_EncCounts_1_inst_multand_4
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_121 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_12,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_121_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_131 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_13,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_131_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_5_267 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_13,
      O => EncoderMonitor0_EncCounts_1_inst_multand_5
    );
  EncoderMonitor0_EncCounts_1_inst_cy_43 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_5,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_42,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_1_12_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_33_268 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_42,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_33
    );
  EncoderMonitor0_EncCounts_1_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_12_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_12_CYINIT_269 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_10_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_12_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_44_270 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_6,
      IB => EncoderMonitor0_EncCounts_1_14_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_44
    );
  EncoderMonitor0_EncCounts_1_inst_sum_34_271 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_14_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_34
    );
  EncoderMonitor0_EncCounts_1_inst_multand_6_272 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_14,
      O => EncoderMonitor0_EncCounts_1_inst_multand_6
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_141 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_14,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_141_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_151 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_15,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_151_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_7_273 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_15,
      O => EncoderMonitor0_EncCounts_1_inst_multand_7
    );
  EncoderMonitor0_EncCounts_1_inst_cy_45 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_7,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_44,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_1_14_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_35_274 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_44,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_35
    );
  EncoderMonitor0_EncCounts_1_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_14_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_14_CYINIT_275 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_12_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_14_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_46_276 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_8,
      IB => EncoderMonitor0_EncCounts_1_16_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_46
    );
  EncoderMonitor0_EncCounts_1_inst_sum_36_277 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_16_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_36
    );
  EncoderMonitor0_EncCounts_1_inst_multand_8_278 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_16,
      O => EncoderMonitor0_EncCounts_1_inst_multand_8
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_161 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_16,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_161_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_171 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_17,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_171_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_9_279 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_17,
      O => EncoderMonitor0_EncCounts_1_inst_multand_9
    );
  EncoderMonitor0_EncCounts_1_inst_cy_47 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_9,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_46,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_1_16_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_37_280 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_46,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_37
    );
  EncoderMonitor0_EncCounts_1_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_16_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_16_CYINIT_281 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_14_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_16_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_48_282 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_10,
      IB => EncoderMonitor0_EncCounts_1_18_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_48
    );
  EncoderMonitor0_EncCounts_1_inst_sum_38_283 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_18_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_38
    );
  EncoderMonitor0_EncCounts_1_inst_multand_10_284 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_18,
      O => EncoderMonitor0_EncCounts_1_inst_multand_10
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_181 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_18,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_181_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_191 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_19,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_191_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_11_285 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_19,
      O => EncoderMonitor0_EncCounts_1_inst_multand_11
    );
  EncoderMonitor0_EncCounts_1_inst_cy_49 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_11,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_48,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_1_18_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_39_286 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_48,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_39
    );
  EncoderMonitor0_EncCounts_1_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_18_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_18_CYINIT_287 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_16_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_18_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_50_288 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_12,
      IB => EncoderMonitor0_EncCounts_1_20_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_50
    );
  EncoderMonitor0_EncCounts_1_inst_sum_40_289 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_20_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_40
    );
  EncoderMonitor0_EncCounts_1_inst_multand_12_290 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_20,
      O => EncoderMonitor0_EncCounts_1_inst_multand_12
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_201 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_20,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_201_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_211 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_21,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_211_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_13_291 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_21,
      O => EncoderMonitor0_EncCounts_1_inst_multand_13
    );
  EncoderMonitor0_EncCounts_1_inst_cy_51 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_13,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_50,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_1_20_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_41_292 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_50,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_41
    );
  EncoderMonitor0_EncCounts_1_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_20_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_20_CYINIT_293 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_18_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_20_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_52_294 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_14,
      IB => EncoderMonitor0_EncCounts_1_22_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_52
    );
  EncoderMonitor0_EncCounts_1_inst_sum_42_295 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_22_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_42
    );
  EncoderMonitor0_EncCounts_1_inst_multand_14_296 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_22,
      O => EncoderMonitor0_EncCounts_1_inst_multand_14
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_221 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_22,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_221_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_231 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_23,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_231_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_15_297 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_23,
      O => EncoderMonitor0_EncCounts_1_inst_multand_15
    );
  EncoderMonitor0_EncCounts_1_inst_cy_53 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_15,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_52,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_1_22_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_43_298 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_52,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_43
    );
  EncoderMonitor0_EncCounts_1_22_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_22_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_22_CYINIT_299 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_20_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_22_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_54_300 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_16,
      IB => EncoderMonitor0_EncCounts_1_24_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_54
    );
  EncoderMonitor0_EncCounts_1_inst_sum_44_301 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_24_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_44
    );
  EncoderMonitor0_EncCounts_1_inst_multand_16_302 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_24,
      O => EncoderMonitor0_EncCounts_1_inst_multand_16
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_241 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_24,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_241_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_251 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_25,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_25
    );
  EncoderMonitor0_EncCounts_1_inst_multand_17_303 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_25,
      O => EncoderMonitor0_EncCounts_1_inst_multand_17
    );
  EncoderMonitor0_EncCounts_1_inst_cy_55 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_17,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_54,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_1_24_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_45_304 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_54,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_1_inst_sum_45
    );
  EncoderMonitor0_EncCounts_1_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_24_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_24_CYINIT_305 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_22_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_24_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_56_306 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_18,
      IB => EncoderMonitor0_EncCounts_1_26_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_1_inst_cy_56
    );
  EncoderMonitor0_EncCounts_1_inst_sum_46_307 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_26_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_1_inst_sum_46
    );
  EncoderMonitor0_EncCounts_1_inst_multand_18_308 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_26,
      O => EncoderMonitor0_EncCounts_1_inst_multand_18
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_261 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_26,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_26
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_271 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_27,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_27
    );
  EncoderMonitor0_EncCounts_1_inst_multand_19_309 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_27,
      O => EncoderMonitor0_EncCounts_1_inst_multand_19
    );
  EncoderMonitor0_EncCounts_1_inst_cy_57 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_19,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_56,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_1_26_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_47_310 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_56,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_1_inst_sum_47
    );
  EncoderMonitor0_EncCounts_1_26_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_26_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_26_CYINIT_311 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_24_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_26_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_58_312 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_20,
      IB => EncoderMonitor0_EncCounts_1_28_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_1_inst_cy_58
    );
  EncoderMonitor0_EncCounts_1_inst_sum_48_313 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_28_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_1_inst_sum_48
    );
  EncoderMonitor0_EncCounts_1_inst_multand_20_314 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_28,
      O => EncoderMonitor0_EncCounts_1_inst_multand_20
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_281 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_28,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_28
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_291 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_29,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_29
    );
  EncoderMonitor0_EncCounts_1_inst_multand_21_315 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_29,
      O => EncoderMonitor0_EncCounts_1_inst_multand_21
    );
  EncoderMonitor0_EncCounts_1_inst_cy_59 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_21,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_58,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_1_28_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_49_316 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_58,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_1_inst_sum_49
    );
  EncoderMonitor0_EncCounts_1_28_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_28_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_28_CYINIT_317 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_26_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_28_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_60_318 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_22,
      IB => EncoderMonitor0_EncCounts_1_30_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_1_inst_cy_60
    );
  EncoderMonitor0_EncCounts_1_inst_sum_50_319 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_30_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_1_inst_sum_50
    );
  EncoderMonitor0_EncCounts_1_inst_multand_22_320 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_30,
      O => EncoderMonitor0_EncCounts_1_inst_multand_22
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_301 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_30,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_30
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_311 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_31,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_31
    );
  EncoderMonitor0_EncCounts_1_inst_multand_23_321 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_31,
      O => EncoderMonitor0_EncCounts_1_inst_multand_23
    );
  EncoderMonitor0_EncCounts_1_inst_cy_61 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_23,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_60,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_1_30_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_51_322 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_60,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_1_inst_sum_51
    );
  EncoderMonitor0_EncCounts_1_30_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_30_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_30_CYINIT_323 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_28_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_30_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_62_324 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_24,
      IB => EncoderMonitor0_EncCounts_1_32_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_1_inst_cy_62
    );
  EncoderMonitor0_EncCounts_1_inst_sum_52_325 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_32_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_1_inst_sum_52
    );
  EncoderMonitor0_EncCounts_1_inst_multand_24_326 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_32,
      O => EncoderMonitor0_EncCounts_1_inst_multand_24
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_321 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_32,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_32
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_331 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_33,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_33
    );
  EncoderMonitor0_EncCounts_1_inst_multand_25_327 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_33,
      O => EncoderMonitor0_EncCounts_1_inst_multand_25
    );
  EncoderMonitor0_EncCounts_1_inst_cy_63 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_25,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_62,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_1_32_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_53_328 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_62,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_1_inst_sum_53
    );
  EncoderMonitor0_EncCounts_1_32_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_32_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_32_CYINIT_329 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_30_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_32_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_64_330 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_26,
      IB => EncoderMonitor0_EncCounts_1_34_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_1_inst_cy_64
    );
  EncoderMonitor0_EncCounts_1_inst_sum_54_331 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_34_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_1_inst_sum_54
    );
  EncoderMonitor0_EncCounts_1_inst_multand_26_332 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_34,
      O => EncoderMonitor0_EncCounts_1_inst_multand_26
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_341 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_34,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_34
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_351 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_35,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_35
    );
  EncoderMonitor0_EncCounts_1_inst_multand_27_333 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_35,
      O => EncoderMonitor0_EncCounts_1_inst_multand_27
    );
  EncoderMonitor0_EncCounts_1_inst_cy_65 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_27,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_64,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_1_34_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_55_334 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_64,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_1_inst_sum_55
    );
  EncoderMonitor0_EncCounts_1_34_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_34_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_34_CYINIT_335 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_32_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_34_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_66_336 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_28,
      IB => EncoderMonitor0_EncCounts_1_36_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_1_inst_cy_66
    );
  EncoderMonitor0_EncCounts_1_inst_sum_56_337 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_36_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_1_inst_sum_56
    );
  EncoderMonitor0_EncCounts_1_inst_multand_28_338 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_36,
      O => EncoderMonitor0_EncCounts_1_inst_multand_28
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_361 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_36,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_36
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_371 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_37,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_37
    );
  EncoderMonitor0_EncCounts_1_inst_multand_29_339 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_37,
      O => EncoderMonitor0_EncCounts_1_inst_multand_29
    );
  EncoderMonitor0_EncCounts_1_inst_cy_67 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_29,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_66,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_1_36_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_57_340 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_66,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_1_inst_sum_57
    );
  EncoderMonitor0_EncCounts_1_36_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_36_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_36_CYINIT_341 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_34_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_36_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_68_342 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_30,
      IB => EncoderMonitor0_EncCounts_1_38_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_1_inst_cy_68
    );
  EncoderMonitor0_EncCounts_1_inst_sum_58_343 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_38_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_1_inst_sum_58
    );
  EncoderMonitor0_EncCounts_1_inst_multand_30_344 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_1_38,
      O => EncoderMonitor0_EncCounts_1_inst_multand_30
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_381 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_38,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_38
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_391 : X_LUT4
    generic map(
      INIT => X"8822"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_inst_lut1_11_1,
      ADR1 => EncoderMonitor0_EncCounts_1_39,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_1_1,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_39
    );
  EncoderMonitor0_EncCounts_1_inst_sum_59_345 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_68,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_39,
      O => EncoderMonitor0_EncCounts_1_inst_sum_59
    );
  EncoderMonitor0_EncCounts_1_38_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_38_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_38_CYINIT_346 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_36_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_38_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_cy_38_347 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_0,
      IB => EncoderMonitor0_EncCounts_1_8_CYINIT,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_1_inst_cy_38
    );
  EncoderMonitor0_EncCounts_1_inst_sum_28_348 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_8_CYINIT,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_28
    );
  EncoderMonitor0_EncCounts_1_inst_multand_0_349 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_8,
      O => EncoderMonitor0_EncCounts_1_inst_multand_0
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_81 : X_LUT4
    generic map(
      INIT => X"4848"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_8,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut4_81_O
    );
  EncoderMonitor0_EncCounts_1_inst_lut4_91 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_9,
      ADR1 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(1),
      O => EncoderMonitor0_EncCounts_1_inst_lut4_91_O
    );
  EncoderMonitor0_EncCounts_1_inst_multand_1_350 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_1_9,
      O => EncoderMonitor0_EncCounts_1_inst_multand_1
    );
  EncoderMonitor0_EncCounts_1_inst_cy_39 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_multand_1,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_38,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_1_8_CYMUXG
    );
  EncoderMonitor0_EncCounts_1_inst_sum_29_351 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_inst_cy_38,
      I1 => EncoderMonitor0_EncCounts_1_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_1_inst_sum_29
    );
  EncoderMonitor0_EncCounts_1_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_1_8_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_8_CYINIT_352 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_CYMUXG,
      O => EncoderMonitor0_EncCounts_1_8_CYINIT
    );
  EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ONE_353 : X_ONE
    port map (
      O => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ONE
    );
  EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ZERO_354 : X_ZERO
    port map (
      O => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ZERO
    );
  EncoderMonitor0_EncCounts_1_inst_cy_37 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ZERO,
      IB => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ONE,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut2_19,
      O => EncoderMonitor0_EncCounts_1_inst_cy_37_rt
    );
  EncoderMonitor0_EncCounts_1_inst_lut2_191 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_EncoderReset(1),
      ADR3 => EncoderMonitor0_EncInc(1),
      O => EncoderMonitor0_EncCounts_1_inst_lut2_19
    );
  EncoderMonitor0_EncCounts_1_inst_lut1_11_1_355 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_EncoderReset(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_GROM
    );
  EncoderMonitor0_EncCounts_1_inst_lut1_11_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_GROM,
      O => EncoderMonitor0_EncCounts_1_inst_lut1_11_1
    );
  EncoderMonitor0_EncCounts_1_inst_cy_37_rt_356 : X_MUX2
    port map (
      IA => NLW_EncoderMonitor0_EncCounts_1_inst_cy_37_rt_IA_UNCONNECTED,
      IB => EncoderMonitor0_EncCounts_1_inst_cy_37_rt,
      SEL => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_LOGIC_ONE,
      O => EncoderMonitor0_EncCounts_1_inst_lut1_11_1_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_cy_40_357 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_2,
      IB => EncoderMonitor0_EncCounts_2_10_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_40
    );
  EncoderMonitor0_EncCounts_2_inst_sum_30_358 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_10_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_101_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_30
    );
  EncoderMonitor0_EncCounts_2_inst_multand_2_359 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_10,
      O => EncoderMonitor0_EncCounts_2_inst_multand_2
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_101 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_10,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(2),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_101_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_111 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_11,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(2),
      O => EncoderMonitor0_EncCounts_2_inst_lut4_111_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_3_360 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_11,
      O => EncoderMonitor0_EncCounts_2_inst_multand_3
    );
  EncoderMonitor0_EncCounts_2_inst_cy_41 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_3,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_40,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_2_10_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_31_361 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_40,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_111_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_31
    );
  EncoderMonitor0_EncCounts_2_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_10_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_10_CYINIT_362 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_8_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_10_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_42_363 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_4,
      IB => EncoderMonitor0_EncCounts_2_12_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_42
    );
  EncoderMonitor0_EncCounts_2_inst_sum_32_364 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_12_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_121_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_32
    );
  EncoderMonitor0_EncCounts_2_inst_multand_4_365 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_12,
      O => EncoderMonitor0_EncCounts_2_inst_multand_4
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_121 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_12,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(2),
      O => EncoderMonitor0_EncCounts_2_inst_lut4_121_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_131 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_13,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(2),
      O => EncoderMonitor0_EncCounts_2_inst_lut4_131_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_5_366 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_13,
      O => EncoderMonitor0_EncCounts_2_inst_multand_5
    );
  EncoderMonitor0_EncCounts_2_inst_cy_43 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_5,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_42,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_2_12_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_33_367 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_42,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_131_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_33
    );
  EncoderMonitor0_EncCounts_2_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_12_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_12_CYINIT_368 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_10_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_12_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_44_369 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_6,
      IB => EncoderMonitor0_EncCounts_2_14_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_44
    );
  EncoderMonitor0_EncCounts_2_inst_sum_34_370 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_14_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_141_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_34
    );
  EncoderMonitor0_EncCounts_2_inst_multand_6_371 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_14,
      O => EncoderMonitor0_EncCounts_2_inst_multand_6
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_141 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_14,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_141_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_151 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_15,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_151_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_7_372 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_15,
      O => EncoderMonitor0_EncCounts_2_inst_multand_7
    );
  EncoderMonitor0_EncCounts_2_inst_cy_45 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_7,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_44,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_2_14_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_35_373 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_44,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_151_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_35
    );
  EncoderMonitor0_EncCounts_2_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_14_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_14_CYINIT_374 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_12_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_14_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_46_375 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_8,
      IB => EncoderMonitor0_EncCounts_2_16_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_46
    );
  EncoderMonitor0_EncCounts_2_inst_sum_36_376 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_16_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_161_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_36
    );
  EncoderMonitor0_EncCounts_2_inst_multand_8_377 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_16,
      O => EncoderMonitor0_EncCounts_2_inst_multand_8
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_161 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_16,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_161_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_171 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_17,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_171_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_9_378 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_17,
      O => EncoderMonitor0_EncCounts_2_inst_multand_9
    );
  EncoderMonitor0_EncCounts_2_inst_cy_47 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_9,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_46,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_2_16_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_37_379 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_46,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_171_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_37
    );
  EncoderMonitor0_EncCounts_2_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_16_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_16_CYINIT_380 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_14_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_16_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_48_381 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_10,
      IB => EncoderMonitor0_EncCounts_2_18_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_48
    );
  EncoderMonitor0_EncCounts_2_inst_sum_38_382 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_18_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_181_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_38
    );
  EncoderMonitor0_EncCounts_2_inst_multand_10_383 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_18,
      O => EncoderMonitor0_EncCounts_2_inst_multand_10
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_181 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_18,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_181_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_191 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_19,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_191_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_11_384 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_19,
      O => EncoderMonitor0_EncCounts_2_inst_multand_11
    );
  EncoderMonitor0_EncCounts_2_inst_cy_49 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_11,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_48,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_2_18_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_39_385 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_48,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_191_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_39
    );
  EncoderMonitor0_EncCounts_2_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_18_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_18_CYINIT_386 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_16_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_18_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_50_387 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_12,
      IB => EncoderMonitor0_EncCounts_2_20_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_50
    );
  EncoderMonitor0_EncCounts_2_inst_sum_40_388 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_20_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_201_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_40
    );
  EncoderMonitor0_EncCounts_2_inst_multand_12_389 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_20,
      O => EncoderMonitor0_EncCounts_2_inst_multand_12
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_201 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_20,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_201_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_211 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_21,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_211_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_13_390 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_21,
      O => EncoderMonitor0_EncCounts_2_inst_multand_13
    );
  EncoderMonitor0_EncCounts_2_inst_cy_51 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_13,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_50,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_2_20_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_41_391 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_50,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_211_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_41
    );
  EncoderMonitor0_EncCounts_2_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_20_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_20_CYINIT_392 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_18_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_20_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_52_393 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_14,
      IB => EncoderMonitor0_EncCounts_2_22_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_52
    );
  EncoderMonitor0_EncCounts_2_inst_sum_42_394 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_22_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_221_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_42
    );
  EncoderMonitor0_EncCounts_2_inst_multand_14_395 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_22,
      O => EncoderMonitor0_EncCounts_2_inst_multand_14
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_221 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_22,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_221_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_231 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_23,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_231_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_15_396 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_23,
      O => EncoderMonitor0_EncCounts_2_inst_multand_15
    );
  EncoderMonitor0_EncCounts_2_inst_cy_53 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_15,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_52,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_2_22_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_43_397 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_52,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_231_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_43
    );
  EncoderMonitor0_EncCounts_2_22_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_22_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_22_CYINIT_398 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_20_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_22_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_54_399 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_16,
      IB => EncoderMonitor0_EncCounts_2_24_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_54
    );
  EncoderMonitor0_EncCounts_2_inst_sum_44_400 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_24_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_241_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_44
    );
  EncoderMonitor0_EncCounts_2_inst_multand_16_401 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_24,
      O => EncoderMonitor0_EncCounts_2_inst_multand_16
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_241 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_24,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_241_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_251 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_25,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_25
    );
  EncoderMonitor0_EncCounts_2_inst_multand_17_402 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_25,
      O => EncoderMonitor0_EncCounts_2_inst_multand_17
    );
  EncoderMonitor0_EncCounts_2_inst_cy_55 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_17,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_54,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_2_24_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_45_403 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_54,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_25,
      O => EncoderMonitor0_EncCounts_2_inst_sum_45
    );
  EncoderMonitor0_EncCounts_2_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_24_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_24_CYINIT_404 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_22_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_24_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_56_405 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_18,
      IB => EncoderMonitor0_EncCounts_2_26_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_2_inst_cy_56
    );
  EncoderMonitor0_EncCounts_2_inst_sum_46_406 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_26_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_26,
      O => EncoderMonitor0_EncCounts_2_inst_sum_46
    );
  EncoderMonitor0_EncCounts_2_inst_multand_18_407 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_26,
      O => EncoderMonitor0_EncCounts_2_inst_multand_18
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_261 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_26,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_26
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_271 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_27,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_27
    );
  EncoderMonitor0_EncCounts_2_inst_multand_19_408 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_27,
      O => EncoderMonitor0_EncCounts_2_inst_multand_19
    );
  EncoderMonitor0_EncCounts_2_inst_cy_57 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_19,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_56,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_2_26_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_47_409 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_56,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_27,
      O => EncoderMonitor0_EncCounts_2_inst_sum_47
    );
  EncoderMonitor0_EncCounts_2_26_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_26_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_26_CYINIT_410 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_24_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_26_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_58_411 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_20,
      IB => EncoderMonitor0_EncCounts_2_28_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_2_inst_cy_58
    );
  EncoderMonitor0_EncCounts_2_inst_sum_48_412 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_28_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_28,
      O => EncoderMonitor0_EncCounts_2_inst_sum_48
    );
  EncoderMonitor0_EncCounts_2_inst_multand_20_413 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_28,
      O => EncoderMonitor0_EncCounts_2_inst_multand_20
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_281 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_28,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_28
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_291 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_29,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_29
    );
  EncoderMonitor0_EncCounts_2_inst_multand_21_414 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_29,
      O => EncoderMonitor0_EncCounts_2_inst_multand_21
    );
  EncoderMonitor0_EncCounts_2_inst_cy_59 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_21,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_58,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_2_28_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_49_415 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_58,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_29,
      O => EncoderMonitor0_EncCounts_2_inst_sum_49
    );
  EncoderMonitor0_EncCounts_2_28_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_28_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_28_CYINIT_416 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_26_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_28_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_60_417 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_22,
      IB => EncoderMonitor0_EncCounts_2_30_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_2_inst_cy_60
    );
  EncoderMonitor0_EncCounts_2_inst_sum_50_418 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_30_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_30,
      O => EncoderMonitor0_EncCounts_2_inst_sum_50
    );
  EncoderMonitor0_EncCounts_2_inst_multand_22_419 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_30,
      O => EncoderMonitor0_EncCounts_2_inst_multand_22
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_301 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_30,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_30
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_311 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_31,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_31
    );
  EncoderMonitor0_EncCounts_2_inst_multand_23_420 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_31,
      O => EncoderMonitor0_EncCounts_2_inst_multand_23
    );
  EncoderMonitor0_EncCounts_2_inst_cy_61 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_23,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_60,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_2_30_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_51_421 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_60,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_31,
      O => EncoderMonitor0_EncCounts_2_inst_sum_51
    );
  EncoderMonitor0_EncCounts_2_30_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_30_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_30_CYINIT_422 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_28_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_30_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_62_423 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_24,
      IB => EncoderMonitor0_EncCounts_2_32_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_2_inst_cy_62
    );
  EncoderMonitor0_EncCounts_2_inst_sum_52_424 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_32_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_32,
      O => EncoderMonitor0_EncCounts_2_inst_sum_52
    );
  EncoderMonitor0_EncCounts_2_inst_multand_24_425 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_32,
      O => EncoderMonitor0_EncCounts_2_inst_multand_24
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_321 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_32,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_32
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_331 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_33,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_33
    );
  EncoderMonitor0_EncCounts_2_inst_multand_25_426 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_33,
      O => EncoderMonitor0_EncCounts_2_inst_multand_25
    );
  EncoderMonitor0_EncCounts_2_inst_cy_63 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_25,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_62,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_2_32_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_53_427 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_62,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_33,
      O => EncoderMonitor0_EncCounts_2_inst_sum_53
    );
  EncoderMonitor0_EncCounts_2_32_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_32_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_32_CYINIT_428 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_30_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_32_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_64_429 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_26,
      IB => EncoderMonitor0_EncCounts_2_34_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_2_inst_cy_64
    );
  EncoderMonitor0_EncCounts_2_inst_sum_54_430 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_34_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_34,
      O => EncoderMonitor0_EncCounts_2_inst_sum_54
    );
  EncoderMonitor0_EncCounts_2_inst_multand_26_431 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_34,
      O => EncoderMonitor0_EncCounts_2_inst_multand_26
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_341 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_34,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_34
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_351 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_35,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => EncoderMonitor0_EncInc_2_1,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_35
    );
  EncoderMonitor0_EncCounts_2_inst_multand_27_432 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_35,
      O => EncoderMonitor0_EncCounts_2_inst_multand_27
    );
  EncoderMonitor0_EncCounts_2_inst_cy_65 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_27,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_64,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_2_34_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_55_433 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_64,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_35,
      O => EncoderMonitor0_EncCounts_2_inst_sum_55
    );
  EncoderMonitor0_EncCounts_2_34_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_34_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_34_CYINIT_434 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_32_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_34_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_66_435 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_28,
      IB => EncoderMonitor0_EncCounts_2_36_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_2_inst_cy_66
    );
  EncoderMonitor0_EncCounts_2_inst_sum_56_436 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_36_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_36,
      O => EncoderMonitor0_EncCounts_2_inst_sum_56
    );
  EncoderMonitor0_EncCounts_2_inst_multand_28_437 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_36,
      O => EncoderMonitor0_EncCounts_2_inst_multand_28
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_361 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_36,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_36
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_371 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_37,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_37
    );
  EncoderMonitor0_EncCounts_2_inst_multand_29_438 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_37,
      O => EncoderMonitor0_EncCounts_2_inst_multand_29
    );
  EncoderMonitor0_EncCounts_2_inst_cy_67 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_29,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_66,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_2_36_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_57_439 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_66,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_37,
      O => EncoderMonitor0_EncCounts_2_inst_sum_57
    );
  EncoderMonitor0_EncCounts_2_36_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_36_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_36_CYINIT_440 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_34_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_36_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_68_441 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_30,
      IB => EncoderMonitor0_EncCounts_2_38_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_2_inst_cy_68
    );
  EncoderMonitor0_EncCounts_2_inst_sum_58_442 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_38_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_38,
      O => EncoderMonitor0_EncCounts_2_inst_sum_58
    );
  EncoderMonitor0_EncCounts_2_inst_multand_30_443 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      I1 => EncoderMonitor0_EncCounts_2_38,
      O => EncoderMonitor0_EncCounts_2_inst_multand_30
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_381 : X_LUT4
    generic map(
      INIT => X"8844"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_38,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_38
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_391 : X_LUT4
    generic map(
      INIT => X"8822"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_inst_lut1_11_1,
      ADR1 => EncoderMonitor0_EncCounts_2_39,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc_2_1,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_39
    );
  EncoderMonitor0_EncCounts_2_inst_sum_59_444 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_68,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_39,
      O => EncoderMonitor0_EncCounts_2_inst_sum_59
    );
  EncoderMonitor0_EncCounts_2_38_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_38_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_38_CYINIT_445 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_36_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_38_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_cy_38_446 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_0,
      IB => EncoderMonitor0_EncCounts_2_8_CYINIT,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_2_inst_cy_38
    );
  EncoderMonitor0_EncCounts_2_inst_sum_28_447 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_8_CYINIT,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_81_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_28
    );
  EncoderMonitor0_EncCounts_2_inst_multand_0_448 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_8,
      O => EncoderMonitor0_EncCounts_2_inst_multand_0
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_81 : X_LUT4
    generic map(
      INIT => X"4848"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_8,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(2),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_81_O
    );
  EncoderMonitor0_EncCounts_2_inst_lut4_91 : X_LUT4
    generic map(
      INIT => X"8484"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_9,
      ADR1 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      ADR2 => EncoderMonitor0_EncInc(2),
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut4_91_O
    );
  EncoderMonitor0_EncCounts_2_inst_multand_1_449 : X_AND2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_lut1_1,
      I1 => EncoderMonitor0_EncCounts_2_9,
      O => EncoderMonitor0_EncCounts_2_inst_multand_1
    );
  EncoderMonitor0_EncCounts_2_inst_cy_39 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_multand_1,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_38,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_2_8_CYMUXG
    );
  EncoderMonitor0_EncCounts_2_inst_sum_29_450 : X_XOR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_inst_cy_38,
      I1 => EncoderMonitor0_EncCounts_2_inst_lut4_91_O,
      O => EncoderMonitor0_EncCounts_2_inst_sum_29
    );
  EncoderMonitor0_EncCounts_2_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncCounts_2_8_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_8_CYINIT_451 : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_CYMUXG,
      O => EncoderMonitor0_EncCounts_2_8_CYINIT
    );
  EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ONE_452 : X_ONE
    port map (
      O => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ONE
    );
  EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ZERO_453 : X_ZERO
    port map (
      O => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ZERO
    );
  EncoderMonitor0_EncCounts_2_inst_cy_37 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ZERO,
      IB => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ONE,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut2_19,
      O => EncoderMonitor0_EncCounts_2_inst_cy_37_rt
    );
  EncoderMonitor0_EncCounts_2_inst_lut2_191 : X_LUT4
    generic map(
      INIT => X"0033"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_EncoderReset(2),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(2),
      O => EncoderMonitor0_EncCounts_2_inst_lut2_19
    );
  EncoderMonitor0_EncCounts_2_inst_lut1_11_1_454 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_GROM
    );
  EncoderMonitor0_EncCounts_2_inst_lut1_11_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_GROM,
      O => EncoderMonitor0_EncCounts_2_inst_lut1_11_1
    );
  EncoderMonitor0_EncCounts_2_inst_cy_37_rt_455 : X_MUX2
    port map (
      IA => NLW_EncoderMonitor0_EncCounts_2_inst_cy_37_rt_IA_UNCONNECTED,
      IB => EncoderMonitor0_EncCounts_2_inst_cy_37_rt,
      SEL => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_LOGIC_ONE,
      O => EncoderMonitor0_EncCounts_2_inst_lut1_11_1_CYMUXG
    );
  EncoderMonitor0_n02891 : X_LUT4
    generic map(
      INIT => X"2814"
    )
    port map (
      ADR0 => EncoderMonitor0_LastInputs_1_0,
      ADR1 => EncoderMonitor0_LastInputs_1_1,
      ADR2 => Encoder1In(0),
      ADR3 => Encoder1In(1),
      O => EncoderMonitor0_n0289
    );
  EncoderMonitor0_n02881 : X_LUT4
    generic map(
      INIT => X"2814"
    )
    port map (
      ADR0 => Encoder0In(1),
      ADR1 => Encoder0In(0),
      ADR2 => EncoderMonitor0_LastInputs_0_1,
      ADR3 => EncoderMonitor0_LastInputs_0_0,
      O => EncoderMonitor0_n0288
    );
  EncoderMonitor0_EncDec_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncDec_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n04370 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_EncDec(2),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncInc(2),
      O => EncoderMonitor0_EncDec_2_FROM
    );
  EncoderMonitor0_n02901 : X_LUT4
    generic map(
      INIT => X"6006"
    )
    port map (
      ADR0 => EncoderMonitor0_LastInputs_2_1,
      ADR1 => Encoder2In(0),
      ADR2 => EncoderMonitor0_LastInputs_2_0,
      ADR3 => Encoder2In(1),
      O => EncoderMonitor0_n0290
    );
  EncoderMonitor0_EncDec_2_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncDec_2_FROM,
      O => CHOICE715
    );
  EncoderMonitor0_EncDec_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncDec_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n02821 : X_LUT4
    generic map(
      INIT => X"6006"
    )
    port map (
      ADR0 => EncoderMonitor0_LastInputs_0_0,
      ADR1 => Encoder0In(1),
      ADR2 => Encoder0In(0),
      ADR3 => EncoderMonitor0_LastInputs_0_1,
      O => EncoderMonitor0_EncInc_0_1_GROM
    );
  EncoderMonitor0_EncInc_0_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncInc_0_1_GROM,
      O => EncoderMonitor0_n0282
    );
  EncoderMonitor0_EncInc_0_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncInc_0_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n02831 : X_LUT4
    generic map(
      INIT => X"4182"
    )
    port map (
      ADR0 => Encoder1In(1),
      ADR1 => EncoderMonitor0_LastInputs_1_1,
      ADR2 => Encoder1In(0),
      ADR3 => EncoderMonitor0_LastInputs_1_0,
      O => EncoderMonitor0_EncInc_1_1_GROM
    );
  EncoderMonitor0_EncInc_1_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncInc_1_1_GROM,
      O => EncoderMonitor0_n0283
    );
  EncoderMonitor0_EncInc_1_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncInc_1_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n02841 : X_LUT4
    generic map(
      INIT => X"6006"
    )
    port map (
      ADR0 => Encoder2In(1),
      ADR1 => EncoderMonitor0_LastInputs_2_0,
      ADR2 => Encoder2In(0),
      ADR3 => EncoderMonitor0_LastInputs_2_1,
      O => EncoderMonitor0_EncInc_2_1_GROM
    );
  EncoderMonitor0_EncInc_2_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncInc_2_1_GROM,
      O => EncoderMonitor0_n0284
    );
  EncoderMonitor0_EncInc_2_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncInc_2_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0428130_1_456 : X_LUT4
    generic map(
      INIT => X"C8C0"
    )
    port map (
      ADR0 => CHOICE783,
      ADR1 => EncoderMonitor0_ClkEn2,
      ADR2 => EncoderMonitor0_EncoderReset(0),
      ADR3 => CHOICE751,
      O => EncoderMonitor0_EncoderReset_0_FROM
    );
  EncoderMonitor0_EncCounts_0_inst_lut1_11 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncoderReset(0),
      O => EncoderMonitor0_EncoderReset_0_GROM
    );
  EncoderMonitor0_EncoderReset_0_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncoderReset_0_FROM,
      O => EncoderMonitor0_n0428130_1
    );
  EncoderMonitor0_EncoderReset_0_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncoderReset_0_GROM,
      O => EncoderMonitor0_EncCounts_0_inst_lut1_1
    );
  EncoderMonitor0_EncoderReset_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncoderReset_0_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0433130_1_457 : X_LUT4
    generic map(
      INIT => X"A888"
    )
    port map (
      ADR0 => EncoderMonitor0_ClkEn2,
      ADR1 => EncoderMonitor0_EncoderReset(1),
      ADR2 => CHOICE679,
      ADR3 => CHOICE711,
      O => EncoderMonitor0_EncoderReset_1_FROM
    );
  EncoderMonitor0_EncCounts_1_inst_lut1_11 : X_LUT4
    generic map(
      INIT => X"0F0F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_EncoderReset(1),
      ADR3 => VCC,
      O => EncoderMonitor0_EncoderReset_1_GROM
    );
  EncoderMonitor0_EncoderReset_1_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncoderReset_1_FROM,
      O => EncoderMonitor0_n0433130_1
    );
  EncoderMonitor0_EncoderReset_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncoderReset_1_GROM,
      O => EncoderMonitor0_EncCounts_1_inst_lut1_1
    );
  EncoderMonitor0_EncoderReset_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncoderReset_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_2_inst_lut1_11 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_EncoderReset(2),
      O => EncoderMonitor0_EncoderReset_2_GROM
    );
  EncoderMonitor0_EncoderReset_2_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_EncoderReset_2_GROM,
      O => EncoderMonitor0_EncCounts_2_inst_lut1_1
    );
  EncoderMonitor0_EncoderReset_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_EncoderReset_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n00781 : X_LUT4
    generic map(
      INIT => X"1010"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncInc_1,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_vTrigCountMin,
      ADR3 => VCC,
      O => EncoderMonitor0_n0078
    );
  EncoderMonitor0_n00791 : X_LUT4
    generic map(
      INIT => X"EEAA"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_vTrigCountMax,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_n0079
    );
  EncoderMonitor0_IncHysterisis_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_IncHysterisis_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_LastInputs_0_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LastInputs_0_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_LastInputs_1_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LastInputs_1_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_LastInputs_2_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LastInputs_2_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncDec_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0290,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncDec_2_FFY_RST,
      O => EncoderMonitor0_EncDec(2)
    );
  EncoderMonitor0_EncDec_2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncDec_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncDec_2_FFY_RST
    );
  EncoderMonitor0_n00811 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_N26708,
      ADR2 => EncoderMonitor0_ClkEn2,
      ADR3 => VCC,
      O => EncoderMonitor0_LatchData_1_GROM
    );
  EncoderMonitor0_LatchData_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_LatchData_1_GROM,
      O => EncoderMonitor0_n0081
    );
  EncoderMonitor0_LatchData_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LatchData_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n029675_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(1),
      ADR1 => EncoderMonitor0_TrigCount(0),
      ADR2 => EncoderMonitor0_TrigCount(2),
      ADR3 => EncoderMonitor0_TrigCount(3),
      O => EncoderMonitor0_LatchData_2_FROM
    );
  EncoderMonitor0_n029675 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => CHOICE277,
      ADR1 => CHOICE269,
      ADR2 => CHOICE284,
      ADR3 => N50604,
      O => EncoderMonitor0_n0296
    );
  EncoderMonitor0_LatchData_2_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_LatchData_2_FROM,
      O => N50604
    );
  EncoderMonitor0_LatchData_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LatchData_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_LatchData_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LatchData_4_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_LatchData_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_LatchData_6_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ONE_458 : X_ONE
    port map (
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ONE
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ZERO_459 : X_ZERO
    port map (
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ZERO
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_4_460 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ONE,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_0,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_4
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_01 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(0),
      ADR1 => PerLBusInterface0_RegBank_7_0,
      ADR2 => EncoderMonitor0_TrigCount(1),
      ADR3 => PerLBusInterface0_RegBank_7_1,
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_0
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_11 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_3,
      ADR1 => EncoderMonitor0_TrigCount(3),
      ADR2 => EncoderMonitor0_TrigCount(2),
      ADR3 => PerLBusInterface0_RegBank_7_2,
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_1
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_5 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_5_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_4,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_1,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_5_CYMUXG
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_7_LOGIC_ZERO_461 : X_ZERO
    port map (
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_7_LOGIC_ZERO
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_6_462 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_7_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYINIT,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_2,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_6
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_21 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(5),
      ADR1 => EncoderMonitor0_TrigCount(4),
      ADR2 => PerLBusInterface0_RegBank_7_4,
      ADR3 => PerLBusInterface0_RegBank_7_5,
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_2
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_31 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_7,
      ADR1 => EncoderMonitor0_TrigCount(6),
      ADR2 => PerLBusInterface0_RegBank_7_6,
      ADR3 => EncoderMonitor0_TrigCount(7),
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_3
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_7 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_7_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_6,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_3,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYMUXG
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYINIT_463 : X_BUF
    port map (
      I => EncoderMonitor0_Mcompar_n0295_inst_cy_5_CYMUXG,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYINIT
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_9_LOGIC_ZERO_464 : X_ZERO
    port map (
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_9_LOGIC_ZERO
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_8_465 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_9_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYINIT,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_4,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_8
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_41 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(9),
      ADR1 => EncoderMonitor0_TrigCount(8),
      ADR2 => PerLBusInterface0_RegBank_7_9,
      ADR3 => PerLBusInterface0_RegBank_7_8,
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_4
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_51 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(11),
      ADR1 => PerLBusInterface0_RegBank_7_11,
      ADR2 => PerLBusInterface0_RegBank_7_10,
      ADR3 => EncoderMonitor0_TrigCount(10),
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_5
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_9 : X_MUX2
    port map (
      IA => EncoderMonitor0_Mcompar_n0295_inst_cy_9_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_8,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_5,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYMUXG
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYINIT_466 : X_BUF
    port map (
      I => EncoderMonitor0_Mcompar_n0295_inst_cy_7_CYMUXG,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYINIT
    );
  EncoderMonitor0_n007233 : X_MUX2
    port map (
      IA => N51042,
      IB => N51044,
      SEL => PerLBusInterface0_RegBank_7_17,
      O => EncoderMonitor0_n0072
    );
  EncoderMonitor0_n007233_G : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => EncoderMonitor0_EncDec(2),
      ADR1 => PerLBusInterface0_RegBank_7_16,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_7_18,
      O => N51044
    );
  EncoderMonitor0_n007233_F : X_LUT4
    generic map(
      INIT => X"0B08"
    )
    port map (
      ADR0 => EncoderMonitor0_EncDec(1),
      ADR1 => PerLBusInterface0_RegBank_7_16,
      ADR2 => PerLBusInterface0_RegBank_7_18,
      ADR3 => EncoderMonitor0_EncDec(0),
      O => N51042
    );
  EncoderMonitor0_SelEncDec_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SelEncDec_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n007133 : X_MUX2
    port map (
      IA => N51002,
      IB => N51004,
      SEL => PerLBusInterface0_RegBank_7_17,
      O => EncoderMonitor0_SelEncInc_F5MUX
    );
  EncoderMonitor0_n007133_G : X_LUT4
    generic map(
      INIT => X"0022"
    )
    port map (
      ADR0 => EncoderMonitor0_EncInc_2_1,
      ADR1 => PerLBusInterface0_RegBank_7_16,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_7_18,
      O => N51004
    );
  EncoderMonitor0_n007133_F : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_18,
      ADR1 => PerLBusInterface0_RegBank_7_16,
      ADR2 => EncoderMonitor0_EncInc_1_1,
      ADR3 => EncoderMonitor0_EncInc_0_1,
      O => N51002
    );
  EncoderMonitor0_SelEncInc_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_SelEncInc_F5MUX,
      O => EncoderMonitor0_n0071
    );
  EncoderMonitor0_SelEncInc_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SelEncInc_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n02971 : X_LUT4
    generic map(
      INIT => X"0AAA"
    )
    port map (
      ADR0 => EncoderMonitor0_n0016,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_7_18,
      ADR3 => PerLBusInterface0_RegBank_7_17,
      O => EncoderMonitor0_SelEncReset_1_GROM
    );
  EncoderMonitor0_SelEncReset_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_SelEncReset_1_GROM,
      O => EncoderMonitor0_n0297
    );
  EncoderMonitor0_SelEncReset_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SelEncReset_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0205_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(100),
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0205
    );
  EncoderMonitor0_Mmux_n0206_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(99),
      ADR3 => VCC,
      O => EncoderMonitor0_n0206
    );
  EncoderMonitor0_SerialResults_101_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_101_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0203_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(102),
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0203
    );
  EncoderMonitor0_Mmux_n0204_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(101),
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => VCC,
      O => EncoderMonitor0_n0204
    );
  EncoderMonitor0_SerialResults_103_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_103_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0201_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(104),
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0201
    );
  EncoderMonitor0_Mmux_n0202_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_SerialResults(103),
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => VCC,
      O => EncoderMonitor0_n0202
    );
  EncoderMonitor0_SerialResults_105_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_105_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0199_Result1 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(106),
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0199
    );
  EncoderMonitor0_Mmux_n0200_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_SerialResults(105),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0200
    );
  EncoderMonitor0_SerialResults_107_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_107_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0197_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_4,
      ADR3 => EncoderMonitor0_SerialResults(108),
      O => EncoderMonitor0_n0197
    );
  EncoderMonitor0_Mmux_n0198_Result1 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(107),
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_LatchData_4,
      ADR3 => VCC,
      O => EncoderMonitor0_n0198
    );
  EncoderMonitor0_SerialResults_109_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_109_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0195_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(110),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_4,
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0195
    );
  EncoderMonitor0_Mmux_n0196_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_4,
      ADR3 => EncoderMonitor0_SerialResults(109),
      O => EncoderMonitor0_n0196
    );
  EncoderMonitor0_SerialResults_111_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_111_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0193_Result1 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SerialResults(112),
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0193
    );
  EncoderMonitor0_Mmux_n0194_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(111),
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0194
    );
  EncoderMonitor0_SerialResults_113_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_113_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0191_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_SerialResults(114),
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0191
    );
  EncoderMonitor0_Mmux_n0192_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(113),
      ADR3 => VCC,
      O => EncoderMonitor0_n0192
    );
  EncoderMonitor0_SerialResults_115_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_115_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0189_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(116),
      ADR3 => VCC,
      O => EncoderMonitor0_n0189
    );
  EncoderMonitor0_Mmux_n0190_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_SerialResults(115),
      ADR3 => VCC,
      O => EncoderMonitor0_n0190
    );
  EncoderMonitor0_SerialResults_117_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_117_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0187_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(118),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0187
    );
  EncoderMonitor0_Mmux_n0188_Result1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_LatchData_4,
      ADR3 => EncoderMonitor0_SerialResults(117),
      O => EncoderMonitor0_n0188
    );
  EncoderMonitor0_SerialResults_119_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_119_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0103_Result1 : X_LUT4
    generic map(
      INIT => X"F0B8"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(10),
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_EncCounts_0_19,
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0103
    );
  EncoderMonitor0_Mmux_n0104_Result1 : X_LUT4
    generic map(
      INIT => X"CACC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(9),
      ADR1 => EncoderMonitor0_EncCounts_0_18,
      ADR2 => EncoderMonitor0_LatchData_1,
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0104
    );
  EncoderMonitor0_SerialResults_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_11_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0185_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_SerialResults(120),
      ADR3 => VCC,
      O => EncoderMonitor0_n0185
    );
  EncoderMonitor0_Mmux_n0186_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => EncoderMonitor0_SerialResults(119),
      O => EncoderMonitor0_n0186
    );
  EncoderMonitor0_SerialResults_121_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_121_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0183_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(122),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0183
    );
  EncoderMonitor0_Mmux_n0184_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_SerialResults(121),
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0184
    );
  EncoderMonitor0_SerialResults_123_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_123_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0181_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(124),
      ADR3 => VCC,
      O => EncoderMonitor0_n0181
    );
  EncoderMonitor0_Mmux_n0182_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(123),
      O => EncoderMonitor0_n0182
    );
  EncoderMonitor0_SerialResults_125_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_125_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0179_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(126),
      O => EncoderMonitor0_n0179
    );
  EncoderMonitor0_Mmux_n0180_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SerialResults(125),
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0180
    );
  EncoderMonitor0_SerialResults_127_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_127_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0241_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_SerialResults(128),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0241
    );
  EncoderMonitor0_Mmux_n0242_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(127),
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0242
    );
  EncoderMonitor0_SerialResults_129_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_129_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0239_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_3,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SerialResults(130),
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0239
    );
  EncoderMonitor0_Mmux_n0240_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(129),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0240
    );
  EncoderMonitor0_SerialResults_131_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_131_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0237_Result1 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_SerialResults(132),
      O => EncoderMonitor0_n0237
    );
  EncoderMonitor0_Mmux_n0238_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_SerialResults(131),
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => VCC,
      O => EncoderMonitor0_n0238
    );
  EncoderMonitor0_SerialResults_133_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_133_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0235_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(134),
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0235
    );
  EncoderMonitor0_Mmux_n0236_Result1 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(133),
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => VCC,
      O => EncoderMonitor0_n0236
    );
  EncoderMonitor0_SerialResults_135_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_135_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0233_Result1 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_SerialResults(136),
      O => EncoderMonitor0_n0233
    );
  EncoderMonitor0_Mmux_n0234_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(135),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0234
    );
  EncoderMonitor0_SerialResults_137_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_137_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0231_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => EncoderMonitor0_SerialResults(138),
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0231
    );
  EncoderMonitor0_Mmux_n0232_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => EncoderMonitor0_SerialResults(137),
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0232
    );
  EncoderMonitor0_SerialResults_139_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_139_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0101_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_21,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(12),
      O => EncoderMonitor0_n0101
    );
  EncoderMonitor0_Mmux_n0102_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_20,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(11),
      O => EncoderMonitor0_n0102
    );
  EncoderMonitor0_SerialResults_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_13_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0229_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => EncoderMonitor0_SerialResults(140),
      ADR3 => VCC,
      O => EncoderMonitor0_n0229
    );
  EncoderMonitor0_Mmux_n0230_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => EncoderMonitor0_SerialResults(139),
      ADR3 => VCC,
      O => EncoderMonitor0_n0230
    );
  EncoderMonitor0_SerialResults_141_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_141_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0227_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(142),
      O => EncoderMonitor0_n0227
    );
  EncoderMonitor0_Mmux_n0228_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_3,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(141),
      O => EncoderMonitor0_n0228
    );
  EncoderMonitor0_SerialResults_143_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_143_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0225_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(144),
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0225
    );
  EncoderMonitor0_Mmux_n0226_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(143),
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0226
    );
  EncoderMonitor0_SerialResults_145_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_145_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0223_Result1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(146),
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0223
    );
  EncoderMonitor0_Mmux_n0224_Result1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(145),
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0224
    );
  EncoderMonitor0_SerialResults_147_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_147_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0221_Result1 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_3,
      ADR1 => EncoderMonitor0_SerialResults(148),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0221
    );
  EncoderMonitor0_Mmux_n0222_Result1 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(147),
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0222
    );
  EncoderMonitor0_SerialResults_149_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_149_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_150_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_SerialResults_150_FROM
    );
  EncoderMonitor0_Mmux_n0220_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_SerialResults(149),
      O => EncoderMonitor0_n0220
    );
  EncoderMonitor0_SerialResults_150_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_SerialResults_150_FROM,
      O => EncoderMonitor0_SerialResults_150_X
    );
  EncoderMonitor0_SerialResults_150_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_150_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0219_Result1 : X_LUT4
    generic map(
      INIT => X"0088"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(150),
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0219
    );
  EncoderMonitor0_SerialResults_151_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_151_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0217_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(152),
      O => EncoderMonitor0_n0217
    );
  EncoderMonitor0_Mmux_n0218_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(151),
      O => EncoderMonitor0_n0218
    );
  EncoderMonitor0_SerialResults_153_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_153_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0215_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(154),
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_LatchData_3,
      O => EncoderMonitor0_n0215
    );
  EncoderMonitor0_Mmux_n0216_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => EncoderMonitor0_SerialResults(153),
      O => EncoderMonitor0_n0216
    );
  EncoderMonitor0_SerialResults_155_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_155_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0213_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(156),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => EncoderMonitor0_ShiftResults_3,
      O => EncoderMonitor0_n0213
    );
  EncoderMonitor0_Mmux_n0214_Result1 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(155),
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => EncoderMonitor0_LatchData_3,
      ADR3 => VCC,
      O => EncoderMonitor0_n0214
    );
  EncoderMonitor0_SerialResults_157_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_157_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_159_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_159_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_159_FFX_RST
    );
  EncoderMonitor0_SerialResults_159 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0211,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_159_FFX_RST,
      O => EncoderMonitor0_SerialResults(159)
    );
  EncoderMonitor0_Mmux_n0211_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_4,
      ADR1 => EncoderMonitor0_LatchData_3,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(158),
      O => EncoderMonitor0_n0211
    );
  EncoderMonitor0_Mmux_n0212_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_3,
      ADR1 => EncoderMonitor0_ShiftResults_3,
      ADR2 => EncoderMonitor0_SerialResults(157),
      ADR3 => VCC,
      O => EncoderMonitor0_n0212
    );
  EncoderMonitor0_SerialResults_159_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_159_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_15_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_15_FFX_RST
    );
  EncoderMonitor0_SerialResults_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0099,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_15_FFX_RST,
      O => EncoderMonitor0_SerialResults(15)
    );
  EncoderMonitor0_Mmux_n0099_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_23,
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(14),
      O => EncoderMonitor0_n0099
    );
  EncoderMonitor0_Mmux_n0100_Result1 : X_LUT4
    generic map(
      INIT => X"CCE4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_1,
      ADR1 => EncoderMonitor0_EncCounts_0_22,
      ADR2 => EncoderMonitor0_SerialResults(13),
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0100
    );
  EncoderMonitor0_SerialResults_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_15_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_161_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_161_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_161_FFY_RST
    );
  EncoderMonitor0_SerialResults_160 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0274,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_161_FFY_RST,
      O => EncoderMonitor0_SerialResults(160)
    );
  EncoderMonitor0_SerialResults_161_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_161_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_161_FFX_RST
    );
  EncoderMonitor0_SerialResults_161 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0273,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_161_FFX_RST,
      O => EncoderMonitor0_SerialResults(161)
    );
  EncoderMonitor0_Mmux_n0273_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_SerialResults(160),
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => VCC,
      O => EncoderMonitor0_n0273
    );
  EncoderMonitor0_Mmux_n0274_Result1 : X_LUT4
    generic map(
      INIT => X"5000"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SerialResults(159),
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0274
    );
  EncoderMonitor0_SerialResults_161_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_161_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_163_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_163_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_163_FFX_RST
    );
  EncoderMonitor0_SerialResults_163 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0271,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_163_FFX_RST,
      O => EncoderMonitor0_SerialResults(163)
    );
  EncoderMonitor0_SerialResults_163_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_163_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_163_FFY_RST
    );
  EncoderMonitor0_SerialResults_162 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0272,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_163_FFY_RST,
      O => EncoderMonitor0_SerialResults(162)
    );
  EncoderMonitor0_Mmux_n0271_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(162),
      O => EncoderMonitor0_n0271
    );
  EncoderMonitor0_Mmux_n0272_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(161),
      O => EncoderMonitor0_n0272
    );
  EncoderMonitor0_SerialResults_163_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_163_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_165_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_165_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_165_FFX_RST
    );
  EncoderMonitor0_SerialResults_165 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0269,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_165_FFX_RST,
      O => EncoderMonitor0_SerialResults(165)
    );
  EncoderMonitor0_Mmux_n0269_Result1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_SerialResults(164),
      O => EncoderMonitor0_n0269
    );
  EncoderMonitor0_Mmux_n0270_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_SerialResults(163),
      O => EncoderMonitor0_n0270
    );
  EncoderMonitor0_SerialResults_165_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_165_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_167_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_167_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_167_FFY_RST
    );
  EncoderMonitor0_SerialResults_166 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0268,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_167_FFY_RST,
      O => EncoderMonitor0_SerialResults(166)
    );
  EncoderMonitor0_SerialResults_167_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_167_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_167_FFX_RST
    );
  EncoderMonitor0_SerialResults_167 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0267,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_167_FFX_RST,
      O => EncoderMonitor0_SerialResults(167)
    );
  EncoderMonitor0_Mmux_n0267_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(166),
      O => EncoderMonitor0_n0267
    );
  EncoderMonitor0_Mmux_n0268_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(165),
      O => EncoderMonitor0_n0268
    );
  EncoderMonitor0_SerialResults_167_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_167_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_168_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_168_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_168_FFY_RST
    );
  EncoderMonitor0_SerialResults_168 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0266,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_168_FFY_RST,
      O => EncoderMonitor0_SerialResults(168)
    );
  EncoderMonitor0_Mmux_n0266_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_SerialResults(167),
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => VCC,
      O => EncoderMonitor0_n0266
    );
  EncoderMonitor0_SerialResults_168_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_168_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_169_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_169_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_169_FFY_RST
    );
  EncoderMonitor0_SerialResults_169 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0265,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_169_FFY_RST,
      O => EncoderMonitor0_SerialResults(169)
    );
  EncoderMonitor0_Mmux_n0265_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(168),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0265
    );
  EncoderMonitor0_SerialResults_169_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_169_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0098_Result1 : X_LUT4
    generic map(
      INIT => X"F0B8"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(15),
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_EncCounts_0_24,
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0098
    );
  EncoderMonitor0_SerialResults_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_16_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0263_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SerialResults(170),
      O => EncoderMonitor0_n0263
    );
  EncoderMonitor0_Mmux_n0264_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(169),
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0264
    );
  EncoderMonitor0_SerialResults_171_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_171_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0261_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_SerialResults(172),
      ADR3 => VCC,
      O => EncoderMonitor0_n0261
    );
  EncoderMonitor0_Mmux_n0262_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(171),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0262
    );
  EncoderMonitor0_SerialResults_173_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_173_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0259_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(174),
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_LatchData_2,
      O => EncoderMonitor0_n0259
    );
  EncoderMonitor0_Mmux_n0260_Result1 : X_LUT4
    generic map(
      INIT => X"00C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_SerialResults(173),
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_LatchData_2,
      O => EncoderMonitor0_n0260
    );
  EncoderMonitor0_SerialResults_175_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_175_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0257_Result1 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(176),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0257
    );
  EncoderMonitor0_Mmux_n0258_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_SerialResults(175),
      O => EncoderMonitor0_n0258
    );
  EncoderMonitor0_SerialResults_177_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_177_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0255_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => EncoderMonitor0_SerialResults(178),
      ADR3 => VCC,
      O => EncoderMonitor0_n0255
    );
  EncoderMonitor0_Mmux_n0256_Result1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => EncoderMonitor0_SerialResults(177),
      O => EncoderMonitor0_n0256
    );
  EncoderMonitor0_SerialResults_179_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_179_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0253_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => EncoderMonitor0_SerialResults(180),
      ADR3 => VCC,
      O => EncoderMonitor0_n0253
    );
  EncoderMonitor0_Mmux_n0254_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_ShiftResults_2,
      ADR2 => EncoderMonitor0_SerialResults(179),
      ADR3 => VCC,
      O => EncoderMonitor0_n0254
    );
  EncoderMonitor0_SerialResults_181_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_181_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0251_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_SerialResults(182),
      O => EncoderMonitor0_n0251
    );
  EncoderMonitor0_Mmux_n0252_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(181),
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => VCC,
      O => EncoderMonitor0_n0252
    );
  EncoderMonitor0_SerialResults_183_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_183_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0249_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(184),
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0249
    );
  EncoderMonitor0_Mmux_n0250_Result1 : X_LUT4
    generic map(
      INIT => X"4400"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_2,
      ADR1 => EncoderMonitor0_SerialResults(183),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0250
    );
  EncoderMonitor0_SerialResults_185_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_185_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0247_Result1 : X_LUT4
    generic map(
      INIT => X"0808"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_2,
      ADR1 => EncoderMonitor0_SerialResults(186),
      ADR2 => EncoderMonitor0_LatchData_2,
      ADR3 => VCC,
      O => EncoderMonitor0_n0247
    );
  EncoderMonitor0_Mmux_n0248_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_SerialResults(185),
      O => EncoderMonitor0_n0248
    );
  EncoderMonitor0_SerialResults_187_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_187_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0245_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_2,
      ADR3 => EncoderMonitor0_SerialResults(188),
      O => EncoderMonitor0_n0245
    );
  EncoderMonitor0_Mmux_n0246_Result1 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(187),
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0246
    );
  EncoderMonitor0_SerialResults_189_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_189_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0096_Result1 : X_LUT4
    generic map(
      INIT => X"D8CC"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_26,
      ADR2 => EncoderMonitor0_SerialResults(17),
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0096
    );
  EncoderMonitor0_Mmux_n0097_Result1 : X_LUT4
    generic map(
      INIT => X"D8CC"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_25,
      ADR2 => EncoderMonitor0_SerialResults(16),
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0097
    );
  EncoderMonitor0_SerialResults_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_18_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0243_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(190),
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_ShiftResults_3,
      ADR3 => VCC,
      O => EncoderMonitor0_n0243
    );
  EncoderMonitor0_Mmux_n0244_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_2,
      ADR2 => EncoderMonitor0_SerialResults(189),
      ADR3 => EncoderMonitor0_ShiftResults_2,
      O => EncoderMonitor0_n0244
    );
  EncoderMonitor0_SerialResults_191_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_191_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0095_Result1 : X_LUT4
    generic map(
      INIT => X"AAE2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_27,
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_SerialResults(18),
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0095
    );
  EncoderMonitor0_SerialResults_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_19_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0113_Result1 : X_LUT4
    generic map(
      INIT => X"EF40"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_SerialResults(0),
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_EncCounts_0_9,
      O => EncoderMonitor0_n0113
    );
  EncoderMonitor0_n01141 : X_LUT4
    generic map(
      INIT => X"B0B0"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_EncCounts_0_8,
      ADR3 => VCC,
      O => EncoderMonitor0_n0114
    );
  EncoderMonitor0_SerialResults_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0093_Result1 : X_LUT4
    generic map(
      INIT => X"F0D8"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_1,
      ADR1 => EncoderMonitor0_SerialResults(20),
      ADR2 => EncoderMonitor0_EncCounts_0_29,
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0093
    );
  EncoderMonitor0_Mmux_n0094_Result1 : X_LUT4
    generic map(
      INIT => X"CCE4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_1,
      ADR1 => EncoderMonitor0_EncCounts_0_28,
      ADR2 => EncoderMonitor0_SerialResults(19),
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0094
    );
  EncoderMonitor0_SerialResults_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_21_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0091_Result1 : X_LUT4
    generic map(
      INIT => X"EF40"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_SerialResults(22),
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_EncCounts_0_31,
      O => EncoderMonitor0_n0091
    );
  EncoderMonitor0_Mmux_n0092_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(21),
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_EncCounts_0_30,
      O => EncoderMonitor0_n0092
    );
  EncoderMonitor0_SerialResults_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_23_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0089_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(24),
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_LatchData_1,
      ADR3 => EncoderMonitor0_EncCounts_0_33,
      O => EncoderMonitor0_n0089
    );
  EncoderMonitor0_Mmux_n0090_Result1 : X_LUT4
    generic map(
      INIT => X"F4B0"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_EncCounts_0_32,
      ADR3 => EncoderMonitor0_SerialResults(23),
      O => EncoderMonitor0_n0090
    );
  EncoderMonitor0_SerialResults_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_25_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0087_Result1 : X_LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_1,
      ADR1 => EncoderMonitor0_EncCounts_0_35,
      ADR2 => EncoderMonitor0_LatchData_1,
      ADR3 => EncoderMonitor0_SerialResults(26),
      O => EncoderMonitor0_n0087
    );
  EncoderMonitor0_Mmux_n0088_Result1 : X_LUT4
    generic map(
      INIT => X"EF40"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_SerialResults(25),
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_EncCounts_0_34,
      O => EncoderMonitor0_n0088
    );
  EncoderMonitor0_SerialResults_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_27_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0085_Result1 : X_LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_37,
      ADR1 => EncoderMonitor0_SerialResults(28),
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0085
    );
  EncoderMonitor0_Mmux_n0086_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_36,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(27),
      O => EncoderMonitor0_n0086
    );
  EncoderMonitor0_SerialResults_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_29_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0083_Result1 : X_LUT4
    generic map(
      INIT => X"AAE2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_39,
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_SerialResults(30),
      ADR3 => EncoderMonitor0_LatchData_1,
      O => EncoderMonitor0_n0083
    );
  EncoderMonitor0_Mmux_n0084_Result1 : X_LUT4
    generic map(
      INIT => X"ACAA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_38,
      ADR1 => EncoderMonitor0_SerialResults(29),
      ADR2 => EncoderMonitor0_LatchData_1,
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0084
    );
  EncoderMonitor0_SerialResults_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_31_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0145_Result1 : X_LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_EncCounts_1_9,
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_SerialResults(32),
      O => EncoderMonitor0_n0145
    );
  EncoderMonitor0_Mmux_n0146_Result1 : X_LUT4
    generic map(
      INIT => X"CCE4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_EncCounts_1_8,
      ADR2 => EncoderMonitor0_SerialResults(31),
      ADR3 => EncoderMonitor0_LatchData_6,
      O => EncoderMonitor0_n0146
    );
  EncoderMonitor0_SerialResults_33_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_33_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0143_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(34),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_11,
      O => EncoderMonitor0_n0143
    );
  EncoderMonitor0_Mmux_n0144_Result1 : X_LUT4
    generic map(
      INIT => X"CCAC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(33),
      ADR1 => EncoderMonitor0_EncCounts_1_10,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_LatchData_6,
      O => EncoderMonitor0_n0144
    );
  EncoderMonitor0_SerialResults_35_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_35_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0141_Result1 : X_LUT4
    generic map(
      INIT => X"F0D8"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_SerialResults(36),
      ADR2 => EncoderMonitor0_EncCounts_1_13,
      ADR3 => EncoderMonitor0_LatchData_6,
      O => EncoderMonitor0_n0141
    );
  EncoderMonitor0_Mmux_n0142_Result1 : X_LUT4
    generic map(
      INIT => X"CCAC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(35),
      ADR1 => EncoderMonitor0_EncCounts_1_12,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_LatchData_6,
      O => EncoderMonitor0_n0142
    );
  EncoderMonitor0_SerialResults_37_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_37_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0139_Result1 : X_LUT4
    generic map(
      INIT => X"ACAA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_15,
      ADR1 => EncoderMonitor0_SerialResults(38),
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0139
    );
  EncoderMonitor0_Mmux_n0140_Result1 : X_LUT4
    generic map(
      INIT => X"E4F0"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_6,
      ADR1 => EncoderMonitor0_SerialResults(37),
      ADR2 => EncoderMonitor0_EncCounts_1_14,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0140
    );
  EncoderMonitor0_SerialResults_39_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_39_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_3_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_3_FFX_RST
    );
  EncoderMonitor0_SerialResults_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0111,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_3_FFX_RST,
      O => EncoderMonitor0_SerialResults(3)
    );
  EncoderMonitor0_Mmux_n0111_Result1 : X_LUT4
    generic map(
      INIT => X"D8CC"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_EncCounts_0_11,
      ADR2 => EncoderMonitor0_SerialResults(2),
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0111
    );
  EncoderMonitor0_Mmux_n0112_Result1 : X_LUT4
    generic map(
      INIT => X"AEA2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_10,
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_LatchData_1,
      ADR3 => EncoderMonitor0_SerialResults(1),
      O => EncoderMonitor0_n0112
    );
  EncoderMonitor0_SerialResults_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_3_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_41_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_41_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_41_FFX_RST
    );
  EncoderMonitor0_SerialResults_41 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0137,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_41_FFX_RST,
      O => EncoderMonitor0_SerialResults(41)
    );
  EncoderMonitor0_Mmux_n0137_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_17,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_SerialResults(40),
      O => EncoderMonitor0_n0137
    );
  EncoderMonitor0_Mmux_n0138_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(39),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_16,
      O => EncoderMonitor0_n0138
    );
  EncoderMonitor0_SerialResults_41_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_41_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_43_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_43_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_43_FFX_RST
    );
  EncoderMonitor0_SerialResults_43 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0135,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_43_FFX_RST,
      O => EncoderMonitor0_SerialResults(43)
    );
  EncoderMonitor0_SerialResults_43_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_43_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_43_FFY_RST
    );
  EncoderMonitor0_SerialResults_42 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0136,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_43_FFY_RST,
      O => EncoderMonitor0_SerialResults(42)
    );
  EncoderMonitor0_Mmux_n0135_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(42),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_19,
      O => EncoderMonitor0_n0135
    );
  EncoderMonitor0_Mmux_n0136_Result1 : X_LUT4
    generic map(
      INIT => X"FD20"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_SerialResults(41),
      ADR3 => EncoderMonitor0_EncCounts_1_18,
      O => EncoderMonitor0_n0136
    );
  EncoderMonitor0_SerialResults_43_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_43_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_45_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_45_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_45_FFX_RST
    );
  EncoderMonitor0_SerialResults_45 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0133,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_45_FFX_RST,
      O => EncoderMonitor0_SerialResults(45)
    );
  EncoderMonitor0_SerialResults_45_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_45_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_45_FFY_RST
    );
  EncoderMonitor0_SerialResults_44 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0134,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_45_FFY_RST,
      O => EncoderMonitor0_SerialResults(44)
    );
  EncoderMonitor0_Mmux_n0133_Result1 : X_LUT4
    generic map(
      INIT => X"F2D0"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_EncCounts_1_21,
      ADR3 => EncoderMonitor0_SerialResults(44),
      O => EncoderMonitor0_n0133
    );
  EncoderMonitor0_Mmux_n0134_Result1 : X_LUT4
    generic map(
      INIT => X"FD20"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_SerialResults(43),
      ADR3 => EncoderMonitor0_EncCounts_1_20,
      O => EncoderMonitor0_n0134
    );
  EncoderMonitor0_SerialResults_45_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_45_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_47_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_47_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_47_FFX_RST
    );
  EncoderMonitor0_SerialResults_47 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0131,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_47_FFX_RST,
      O => EncoderMonitor0_SerialResults(47)
    );
  EncoderMonitor0_SerialResults_47_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_47_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_47_FFY_RST
    );
  EncoderMonitor0_SerialResults_46 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0132,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_47_FFY_RST,
      O => EncoderMonitor0_SerialResults(46)
    );
  EncoderMonitor0_Mmux_n0131_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(46),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_23,
      O => EncoderMonitor0_n0131
    );
  EncoderMonitor0_Mmux_n0132_Result1 : X_LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_22,
      ADR1 => EncoderMonitor0_SerialResults(45),
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_LatchData_6,
      O => EncoderMonitor0_n0132
    );
  EncoderMonitor0_SerialResults_47_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_47_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_49_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_49_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_49_FFY_RST
    );
  EncoderMonitor0_SerialResults_48 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0130,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_49_FFY_RST,
      O => EncoderMonitor0_SerialResults(48)
    );
  EncoderMonitor0_Mmux_n0129_Result1 : X_LUT4
    generic map(
      INIT => X"E2F0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(48),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_EncCounts_1_25,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0129
    );
  EncoderMonitor0_Mmux_n0130_Result1 : X_LUT4
    generic map(
      INIT => X"ACAA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_24,
      ADR1 => EncoderMonitor0_SerialResults(47),
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0130
    );
  EncoderMonitor0_SerialResults_49_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_49_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_4_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_4_FFY_RST
    );
  EncoderMonitor0_SerialResults_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0110,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_4_FFY_RST,
      O => EncoderMonitor0_SerialResults(4)
    );
  EncoderMonitor0_n042810 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_15,
      ADR1 => EncoderMonitor0_EncCounts_0_14,
      ADR2 => EncoderMonitor0_EncCounts_0_12,
      ADR3 => EncoderMonitor0_EncCounts_0_13,
      O => EncoderMonitor0_SerialResults_4_FROM
    );
  EncoderMonitor0_Mmux_n0110_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_12,
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(3),
      O => EncoderMonitor0_n0110
    );
  EncoderMonitor0_SerialResults_4_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_SerialResults_4_FROM,
      O => CHOICE757
    );
  EncoderMonitor0_SerialResults_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_4_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0127_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(50),
      ADR1 => EncoderMonitor0_ShiftResults_6,
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_EncCounts_1_27,
      O => EncoderMonitor0_n0127
    );
  EncoderMonitor0_Mmux_n0128_Result1 : X_LUT4
    generic map(
      INIT => X"E4F0"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_6,
      ADR1 => EncoderMonitor0_SerialResults(49),
      ADR2 => EncoderMonitor0_EncCounts_1_26,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0128
    );
  EncoderMonitor0_SerialResults_51_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_51_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0125_Result1 : X_LUT4
    generic map(
      INIT => X"D8CC"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_6,
      ADR1 => EncoderMonitor0_EncCounts_1_29,
      ADR2 => EncoderMonitor0_SerialResults(52),
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0125
    );
  EncoderMonitor0_Mmux_n0126_Result1 : X_LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_EncCounts_1_28,
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_SerialResults(51),
      O => EncoderMonitor0_n0126
    );
  EncoderMonitor0_SerialResults_53_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_53_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0123_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(54),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_31,
      O => EncoderMonitor0_n0123
    );
  EncoderMonitor0_Mmux_n0124_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(53),
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_EncCounts_1_30,
      O => EncoderMonitor0_n0124
    );
  EncoderMonitor0_SerialResults_55_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_55_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0121_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_33,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_SerialResults(56),
      O => EncoderMonitor0_n0121
    );
  EncoderMonitor0_Mmux_n0122_Result1 : X_LUT4
    generic map(
      INIT => X"F2D0"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_6,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_EncCounts_1_32,
      ADR3 => EncoderMonitor0_SerialResults(55),
      O => EncoderMonitor0_n0122
    );
  EncoderMonitor0_SerialResults_57_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_57_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0119_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_35,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_SerialResults(58),
      O => EncoderMonitor0_n0119
    );
  EncoderMonitor0_Mmux_n0120_Result1 : X_LUT4
    generic map(
      INIT => X"CACC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(57),
      ADR1 => EncoderMonitor0_EncCounts_1_34,
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0120
    );
  EncoderMonitor0_SerialResults_59_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_59_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0117_Result1 : X_LUT4
    generic map(
      INIT => X"B8AA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_37,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_SerialResults(60),
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0117
    );
  EncoderMonitor0_Mmux_n0118_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_6,
      ADR1 => EncoderMonitor0_EncCounts_1_36,
      ADR2 => EncoderMonitor0_ShiftResults_6,
      ADR3 => EncoderMonitor0_SerialResults(59),
      O => EncoderMonitor0_n0118
    );
  EncoderMonitor0_SerialResults_61_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_61_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0115_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(62),
      ADR1 => EncoderMonitor0_ShiftResults_1,
      ADR2 => EncoderMonitor0_LatchData_6,
      ADR3 => EncoderMonitor0_EncCounts_1_39,
      O => EncoderMonitor0_n0115
    );
  EncoderMonitor0_Mmux_n0116_Result1 : X_LUT4
    generic map(
      INIT => X"B8AA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_38,
      ADR1 => EncoderMonitor0_LatchData_6,
      ADR2 => EncoderMonitor0_SerialResults(61),
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0116
    );
  EncoderMonitor0_SerialResults_63_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_63_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n04375 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_8,
      ADR1 => EncoderMonitor0_EncCounts_2_11,
      ADR2 => EncoderMonitor0_EncCounts_2_9,
      ADR3 => EncoderMonitor0_EncCounts_2_10,
      O => EncoderMonitor0_SerialResults_64_FROM
    );
  EncoderMonitor0_Mmux_n0178_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(63),
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_8,
      O => EncoderMonitor0_n0178
    );
  EncoderMonitor0_SerialResults_64_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_SerialResults_64_FROM,
      O => CHOICE718
    );
  EncoderMonitor0_SerialResults_64_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_64_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_65_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_SerialResults_65_FROM
    );
  EncoderMonitor0_Mmux_n0177_Result1 : X_LUT4
    generic map(
      INIT => X"FD20"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_SerialResults(64),
      ADR3 => EncoderMonitor0_EncCounts_2_9,
      O => EncoderMonitor0_n0177
    );
  EncoderMonitor0_SerialResults_65_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_SerialResults_65_FROM,
      O => EncoderMonitor0_SerialResults_65_X
    );
  EncoderMonitor0_SerialResults_65_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_65_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_67_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_67_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_67_FFX_RST
    );
  EncoderMonitor0_SerialResults_67 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0175,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_67_FFX_RST,
      O => EncoderMonitor0_SerialResults(67)
    );
  EncoderMonitor0_Mmux_n0175_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(66),
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_11,
      O => EncoderMonitor0_n0175
    );
  EncoderMonitor0_Mmux_n0176_Result1 : X_LUT4
    generic map(
      INIT => X"FD08"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_SerialResults(65),
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_10,
      O => EncoderMonitor0_n0176
    );
  EncoderMonitor0_SerialResults_67_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_67_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_69_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_69_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_69_FFX_RST
    );
  EncoderMonitor0_SerialResults_69 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0173,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_69_FFX_RST,
      O => EncoderMonitor0_SerialResults(69)
    );
  EncoderMonitor0_Mmux_n0173_Result1 : X_LUT4
    generic map(
      INIT => X"CACC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(68),
      ADR1 => EncoderMonitor0_EncCounts_2_13,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0173
    );
  EncoderMonitor0_Mmux_n0174_Result1 : X_LUT4
    generic map(
      INIT => X"ACAA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_12,
      ADR1 => EncoderMonitor0_SerialResults(67),
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0174
    );
  EncoderMonitor0_SerialResults_69_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_69_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_6_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_6_FFX_RST
    );
  EncoderMonitor0_SerialResults_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0108,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_6_FFX_RST,
      O => EncoderMonitor0_SerialResults(6)
    );
  EncoderMonitor0_Mmux_n0108_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_14,
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_SerialResults(5),
      O => EncoderMonitor0_n0108
    );
  EncoderMonitor0_Mmux_n0109_Result1 : X_LUT4
    generic map(
      INIT => X"E4F0"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_SerialResults(4),
      ADR2 => EncoderMonitor0_EncCounts_0_13,
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0109
    );
  EncoderMonitor0_SerialResults_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_6_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_71_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_71_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_71_FFX_RST
    );
  EncoderMonitor0_SerialResults_71 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0171,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_71_FFX_RST,
      O => EncoderMonitor0_SerialResults(71)
    );
  EncoderMonitor0_SerialResults_71_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_71_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_71_FFY_RST
    );
  EncoderMonitor0_SerialResults_70 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0172,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_71_FFY_RST,
      O => EncoderMonitor0_SerialResults(70)
    );
  EncoderMonitor0_Mmux_n0171_Result1 : X_LUT4
    generic map(
      INIT => X"CEC4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_EncCounts_2_15,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_SerialResults(70),
      O => EncoderMonitor0_n0171
    );
  EncoderMonitor0_Mmux_n0172_Result1 : X_LUT4
    generic map(
      INIT => X"AEA2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_14,
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_SerialResults(69),
      O => EncoderMonitor0_n0172
    );
  EncoderMonitor0_SerialResults_71_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_71_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_73_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_73_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_73_FFX_RST
    );
  EncoderMonitor0_SerialResults_73 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0169,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_73_FFX_RST,
      O => EncoderMonitor0_SerialResults(73)
    );
  EncoderMonitor0_SerialResults_73_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_73_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_73_FFY_RST
    );
  EncoderMonitor0_SerialResults_72 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0170,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_73_FFY_RST,
      O => EncoderMonitor0_SerialResults(72)
    );
  EncoderMonitor0_Mmux_n0169_Result1 : X_LUT4
    generic map(
      INIT => X"AAE2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_17,
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_SerialResults(72),
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0169
    );
  EncoderMonitor0_Mmux_n0170_Result1 : X_LUT4
    generic map(
      INIT => X"CCE4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_EncCounts_2_16,
      ADR2 => EncoderMonitor0_SerialResults(71),
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0170
    );
  EncoderMonitor0_SerialResults_73_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_73_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_75_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_75_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_75_FFX_RST
    );
  EncoderMonitor0_SerialResults_75 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0167,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_75_FFX_RST,
      O => EncoderMonitor0_SerialResults(75)
    );
  EncoderMonitor0_SerialResults_75_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_75_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_75_FFY_RST
    );
  EncoderMonitor0_SerialResults_74 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0168,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_75_FFY_RST,
      O => EncoderMonitor0_SerialResults(74)
    );
  EncoderMonitor0_Mmux_n0167_Result1 : X_LUT4
    generic map(
      INIT => X"AAE2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_19,
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_SerialResults(74),
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0167
    );
  EncoderMonitor0_Mmux_n0168_Result1 : X_LUT4
    generic map(
      INIT => X"FB08"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(73),
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_18,
      O => EncoderMonitor0_n0168
    );
  EncoderMonitor0_SerialResults_75_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_75_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_SerialResults_77_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_77_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_77_FFY_RST
    );
  EncoderMonitor0_SerialResults_76 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0166,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_77_FFY_RST,
      O => EncoderMonitor0_SerialResults(76)
    );
  EncoderMonitor0_Mmux_n0165_Result1 : X_LUT4
    generic map(
      INIT => X"E2F0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(76),
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_EncCounts_2_21,
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0165
    );
  EncoderMonitor0_Mmux_n0166_Result1 : X_LUT4
    generic map(
      INIT => X"AAE2"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_20,
      ADR1 => EncoderMonitor0_ShiftResults_5,
      ADR2 => EncoderMonitor0_SerialResults(75),
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0166
    );
  EncoderMonitor0_SerialResults_77_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_77_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0163_Result1 : X_LUT4
    generic map(
      INIT => X"B8AA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_23,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_SerialResults(78),
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0163
    );
  EncoderMonitor0_Mmux_n0164_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_5,
      ADR1 => EncoderMonitor0_EncCounts_2_22,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_SerialResults(77),
      O => EncoderMonitor0_n0164
    );
  EncoderMonitor0_SerialResults_79_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_79_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0161_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_25,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_SerialResults(80),
      O => EncoderMonitor0_n0161
    );
  EncoderMonitor0_Mmux_n0162_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_5,
      ADR1 => EncoderMonitor0_EncCounts_2_24,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_SerialResults(79),
      O => EncoderMonitor0_n0162
    );
  EncoderMonitor0_SerialResults_81_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_81_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0159_Result1 : X_LUT4
    generic map(
      INIT => X"D8CC"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_5,
      ADR1 => EncoderMonitor0_EncCounts_2_27,
      ADR2 => EncoderMonitor0_SerialResults(82),
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0159
    );
  EncoderMonitor0_Mmux_n0160_Result1 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_5,
      ADR1 => EncoderMonitor0_EncCounts_2_26,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_SerialResults(81),
      O => EncoderMonitor0_n0160
    );
  EncoderMonitor0_SerialResults_83_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_83_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0157_Result1 : X_LUT4
    generic map(
      INIT => X"E2F0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(84),
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_EncCounts_2_29,
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0157
    );
  EncoderMonitor0_Mmux_n0158_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(83),
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_EncCounts_2_28,
      O => EncoderMonitor0_n0158
    );
  EncoderMonitor0_SerialResults_85_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_85_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0155_Result1 : X_LUT4
    generic map(
      INIT => X"B8AA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_31,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_SerialResults(86),
      ADR3 => EncoderMonitor0_ShiftResults_5,
      O => EncoderMonitor0_n0155
    );
  EncoderMonitor0_Mmux_n0156_Result1 : X_LUT4
    generic map(
      INIT => X"CCE4"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_EncCounts_2_30,
      ADR2 => EncoderMonitor0_SerialResults(85),
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0156
    );
  EncoderMonitor0_SerialResults_87_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_87_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0153_Result1 : X_LUT4
    generic map(
      INIT => X"EF20"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(88),
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_EncCounts_2_33,
      O => EncoderMonitor0_n0153
    );
  EncoderMonitor0_Mmux_n0154_Result1 : X_LUT4
    generic map(
      INIT => X"FD08"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_SerialResults(87),
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_32,
      O => EncoderMonitor0_n0154
    );
  EncoderMonitor0_SerialResults_89_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_89_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0106_Result1 : X_LUT4
    generic map(
      INIT => X"EF40"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_1,
      ADR1 => EncoderMonitor0_SerialResults(7),
      ADR2 => EncoderMonitor0_ShiftResults_1,
      ADR3 => EncoderMonitor0_EncCounts_0_16,
      O => EncoderMonitor0_n0106
    );
  EncoderMonitor0_Mmux_n0107_Result1 : X_LUT4
    generic map(
      INIT => X"F2D0"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_1,
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_EncCounts_0_15,
      ADR3 => EncoderMonitor0_SerialResults(6),
      O => EncoderMonitor0_n0107
    );
  EncoderMonitor0_SerialResults_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_8_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0151_Result1 : X_LUT4
    generic map(
      INIT => X"EF40"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_5,
      ADR1 => EncoderMonitor0_SerialResults(90),
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_EncCounts_2_35,
      O => EncoderMonitor0_n0151
    );
  EncoderMonitor0_Mmux_n0152_Result1 : X_LUT4
    generic map(
      INIT => X"BA8A"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_34,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_SerialResults(89),
      O => EncoderMonitor0_n0152
    );
  EncoderMonitor0_SerialResults_91_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_91_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0149_Result1 : X_LUT4
    generic map(
      INIT => X"FD20"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_LatchData_5,
      ADR2 => EncoderMonitor0_SerialResults(92),
      ADR3 => EncoderMonitor0_EncCounts_2_37,
      O => EncoderMonitor0_n0149
    );
  EncoderMonitor0_Mmux_n0150_Result1 : X_LUT4
    generic map(
      INIT => X"FD08"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults_5,
      ADR1 => EncoderMonitor0_SerialResults(91),
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_EncCounts_2_36,
      O => EncoderMonitor0_n0150
    );
  EncoderMonitor0_SerialResults_93_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_93_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0147_Result1 : X_LUT4
    generic map(
      INIT => X"CACC"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(94),
      ADR1 => EncoderMonitor0_EncCounts_2_39,
      ADR2 => EncoderMonitor0_LatchData_5,
      ADR3 => EncoderMonitor0_ShiftResults_6,
      O => EncoderMonitor0_n0147
    );
  EncoderMonitor0_Mmux_n0148_Result1 : X_LUT4
    generic map(
      INIT => X"AACA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_38,
      ADR1 => EncoderMonitor0_SerialResults(93),
      ADR2 => EncoderMonitor0_ShiftResults_5,
      ADR3 => EncoderMonitor0_LatchData_5,
      O => EncoderMonitor0_n0148
    );
  EncoderMonitor0_SerialResults_95_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_95_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0209_Result1 : X_LUT4
    generic map(
      INIT => X"2020"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(96),
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => VCC,
      O => EncoderMonitor0_n0209
    );
  EncoderMonitor0_Mmux_n0210_Result1 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_LatchData_4,
      ADR2 => EncoderMonitor0_SerialResults(95),
      ADR3 => EncoderMonitor0_ShiftResults_4,
      O => EncoderMonitor0_n0210
    );
  EncoderMonitor0_SerialResults_97_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_97_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0207_Result1 : X_LUT4
    generic map(
      INIT => X"4040"
    )
    port map (
      ADR0 => EncoderMonitor0_LatchData_4,
      ADR1 => EncoderMonitor0_ShiftResults_4,
      ADR2 => EncoderMonitor0_SerialResults(98),
      ADR3 => VCC,
      O => EncoderMonitor0_n0207
    );
  EncoderMonitor0_Mmux_n0208_Result1 : X_LUT4
    generic map(
      INIT => X"00A0"
    )
    port map (
      ADR0 => EncoderMonitor0_SerialResults(97),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults_4,
      ADR3 => EncoderMonitor0_LatchData_4,
      O => EncoderMonitor0_n0208
    );
  EncoderMonitor0_SerialResults_99_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_99_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0105_Result1 : X_LUT4
    generic map(
      INIT => X"B8AA"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_17,
      ADR1 => EncoderMonitor0_LatchData_1,
      ADR2 => EncoderMonitor0_SerialResults(8),
      ADR3 => EncoderMonitor0_ShiftResults_1,
      O => EncoderMonitor0_n0105
    );
  EncoderMonitor0_SerialResults_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_SerialResults_9_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_0_LOGIC_ONE_467 : X_ONE
    port map (
      O => EncoderMonitor0_ShiftCount_0_LOGIC_ONE
    );
  EncoderMonitor0_ShiftCount_inst_cy_28_468 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => EncoderMonitor0_ShiftCount_0_LOGIC_ONE,
      SEL => EncoderMonitor0_BeginShift_rt,
      O => EncoderMonitor0_ShiftCount_inst_cy_28
    );
  EncoderMonitor0_BeginShift_rt_469 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_BeginShift_rt
    );
  EncoderMonitor0_ShiftCount_inst_lut3_31 : X_LUT4
    generic map(
      INIT => X"0303"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => EncoderMonitor0_ShiftCount(0),
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftCount_inst_lut3_3
    );
  EncoderMonitor0_ShiftCount_inst_cy_29 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => EncoderMonitor0_ShiftCount_inst_cy_28,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_3,
      O => EncoderMonitor0_ShiftCount_0_CYMUXG
    );
  EncoderMonitor0_ShiftCount_inst_sum_20_470 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_inst_cy_28,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_3,
      O => EncoderMonitor0_ShiftCount_inst_sum_20
    );
  EncoderMonitor0_ShiftCount_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftCount_0_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_1_LOGIC_ONE_471 : X_ONE
    port map (
      O => EncoderMonitor0_ShiftCount_1_LOGIC_ONE
    );
  EncoderMonitor0_ShiftCount_inst_cy_30_472 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_1_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_1_CYINIT,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_4,
      O => EncoderMonitor0_ShiftCount_inst_cy_30
    );
  EncoderMonitor0_ShiftCount_inst_sum_21_473 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_1_CYINIT,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_4,
      O => EncoderMonitor0_ShiftCount_inst_sum_21
    );
  EncoderMonitor0_ShiftCount_inst_lut3_41 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_BeginShift,
      ADR3 => EncoderMonitor0_ShiftCount(1),
      O => EncoderMonitor0_ShiftCount_inst_lut3_4
    );
  EncoderMonitor0_ShiftCount_inst_lut3_51 : X_LUT4
    generic map(
      INIT => X"0303"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => EncoderMonitor0_ShiftCount(2),
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftCount_inst_lut3_5
    );
  EncoderMonitor0_ShiftCount_inst_cy_31 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_1_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_inst_cy_30,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_5,
      O => EncoderMonitor0_ShiftCount_1_CYMUXG
    );
  EncoderMonitor0_ShiftCount_inst_sum_22_474 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_inst_cy_30,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_5,
      O => EncoderMonitor0_ShiftCount_inst_sum_22
    );
  EncoderMonitor0_ShiftCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftCount_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_1_CYINIT_475 : X_BUF
    port map (
      I => EncoderMonitor0_ShiftCount_0_CYMUXG,
      O => EncoderMonitor0_ShiftCount_1_CYINIT
    );
  EncoderMonitor0_ShiftCount_3_LOGIC_ONE_476 : X_ONE
    port map (
      O => EncoderMonitor0_ShiftCount_3_LOGIC_ONE
    );
  EncoderMonitor0_ShiftCount_inst_cy_32_477 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_3_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_3_CYINIT,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_6,
      O => EncoderMonitor0_ShiftCount_inst_cy_32
    );
  EncoderMonitor0_ShiftCount_inst_sum_23_478 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_3_CYINIT,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_6,
      O => EncoderMonitor0_ShiftCount_inst_sum_23
    );
  EncoderMonitor0_ShiftCount_inst_lut3_61 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftCount(3),
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftCount_inst_lut3_6
    );
  EncoderMonitor0_ShiftCount_inst_lut3_71 : X_LUT4
    generic map(
      INIT => X"0033"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftCount(4),
      O => EncoderMonitor0_ShiftCount_inst_lut3_7
    );
  EncoderMonitor0_ShiftCount_inst_cy_33 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_3_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_inst_cy_32,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_7,
      O => EncoderMonitor0_ShiftCount_3_CYMUXG
    );
  EncoderMonitor0_ShiftCount_inst_sum_24_479 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_inst_cy_32,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_7,
      O => EncoderMonitor0_ShiftCount_inst_sum_24
    );
  EncoderMonitor0_ShiftCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftCount_3_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_3_CYINIT_480 : X_BUF
    port map (
      I => EncoderMonitor0_ShiftCount_1_CYMUXG,
      O => EncoderMonitor0_ShiftCount_3_CYINIT
    );
  EncoderMonitor0_ShiftCount_5_LOGIC_ONE_481 : X_ONE
    port map (
      O => EncoderMonitor0_ShiftCount_5_LOGIC_ONE
    );
  EncoderMonitor0_ShiftCount_inst_cy_34_482 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_5_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_5_CYINIT,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_8,
      O => EncoderMonitor0_ShiftCount_inst_cy_34
    );
  EncoderMonitor0_ShiftCount_inst_sum_25_483 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_5_CYINIT,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_8,
      O => EncoderMonitor0_ShiftCount_inst_sum_25
    );
  EncoderMonitor0_ShiftCount_inst_lut3_81 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftCount(5),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_BeginShift,
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftCount_inst_lut3_8
    );
  EncoderMonitor0_ShiftCount_inst_lut3_91 : X_LUT4
    generic map(
      INIT => X"F3F3"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftCount(6),
      ADR2 => EncoderMonitor0_BeginShift,
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftCount_inst_lut3_9
    );
  EncoderMonitor0_ShiftCount_inst_cy_35 : X_MUX2
    port map (
      IA => EncoderMonitor0_ShiftCount_5_LOGIC_ONE,
      IB => EncoderMonitor0_ShiftCount_inst_cy_34,
      SEL => EncoderMonitor0_ShiftCount_inst_lut3_9,
      O => EncoderMonitor0_ShiftCount_5_CYMUXG
    );
  EncoderMonitor0_ShiftCount_inst_sum_26_484 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_inst_cy_34,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_9,
      O => EncoderMonitor0_ShiftCount_inst_sum_26
    );
  EncoderMonitor0_ShiftCount_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftCount_5_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_5_CYINIT_485 : X_BUF
    port map (
      I => EncoderMonitor0_ShiftCount_3_CYMUXG,
      O => EncoderMonitor0_ShiftCount_5_CYINIT
    );
  EncoderMonitor0_ShiftCount_inst_sum_27_486 : X_XOR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_7_CYINIT,
      I1 => EncoderMonitor0_ShiftCount_inst_lut3_10,
      O => EncoderMonitor0_ShiftCount_inst_sum_27
    );
  EncoderMonitor0_ShiftCount_inst_lut3_101 : X_LUT4
    generic map(
      INIT => X"0055"
    )
    port map (
      ADR0 => EncoderMonitor0_BeginShift,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftCount(7),
      O => EncoderMonitor0_ShiftCount_inst_lut3_10
    );
  EncoderMonitor0_n06491 : X_LUT4
    generic map(
      INIT => X"FAAA"
    )
    port map (
      ADR0 => EncoderMonitor0_BeginShift,
      ADR1 => VCC,
      ADR2 => CHOICE374,
      ADR3 => CHOICE367,
      O => EncoderMonitor0_ShiftCount_7_GROM
    );
  EncoderMonitor0_ShiftCount_7_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_ShiftCount_7_GROM,
      O => EncoderMonitor0_n0649
    );
  EncoderMonitor0_ShiftCount_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftCount_7_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftCount_7_CYINIT_487 : X_BUF
    port map (
      I => EncoderMonitor0_ShiftCount_5_CYMUXG,
      O => EncoderMonitor0_ShiftCount_7_CYINIT
    );
  EncoderMonitor0_n04541_9_488 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_n0275,
      ADR3 => EncoderMonitor0_ShiftResults,
      O => EncoderMonitor0_ShiftResults_FROM
    );
  EncoderMonitor0_n04541 : X_LUT4
    generic map(
      INIT => X"EEEE"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftResults,
      ADR1 => EncoderMonitor0_n0275,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftResults_GROM
    );
  EncoderMonitor0_ShiftResults_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_ShiftResults_FROM,
      O => EncoderMonitor0_n04541_9
    );
  EncoderMonitor0_ShiftResults_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_ShiftResults_GROM,
      O => EncoderMonitor0_n0454
    );
  EncoderMonitor0_ShiftResults_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftResults_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftResults_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftResults_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftResults_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftResults_4_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_ShiftResults_6_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_ShiftResults_6_GROM
    );
  EncoderMonitor0_ShiftResults_6_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_ShiftResults_6_GROM,
      O => EncoderMonitor0_ShiftResults_6_Y
    );
  EncoderMonitor0_ShiftResults_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_ShiftResults_6_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_0_Q : X_MUX2
    port map (
      IA => N51007,
      IB => N51009,
      SEL => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_n0077(0)
    );
  EncoderMonitor0_n0077_0_G : X_LUT4
    generic map(
      INIT => X"0101"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(0),
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_vTrigCountMax,
      ADR3 => VCC,
      O => N51009
    );
  EncoderMonitor0_n0077_0_F : X_LUT4
    generic map(
      INIT => X"3101"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(0),
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_vTrigCountMin,
      ADR3 => PerLBusInterface0_RegBank_7_0,
      O => N51007
    );
  EncoderMonitor0_TrigCount_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_0_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_10_SW0 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => EncoderMonitor0_vTrigCountMin,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_7_10,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_TrigCount_10_FROM
    );
  EncoderMonitor0_n0077_10_Q : X_LUT4
    generic map(
      INIT => X"4055"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_N26514,
      ADR2 => EncoderMonitor0_n0279(10),
      ADR3 => N46457,
      O => EncoderMonitor0_n0077_10_O
    );
  EncoderMonitor0_TrigCount_10_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_10_FROM,
      O => N46457
    );
  EncoderMonitor0_TrigCount_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_10_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_11_SW0 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => PerLBusInterface0_RegBank_7_11,
      O => EncoderMonitor0_TrigCount_11_FROM
    );
  EncoderMonitor0_n0077_11_Q : X_LUT4
    generic map(
      INIT => X"3111"
    )
    port map (
      ADR0 => N46498,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_n0279(11),
      ADR3 => EncoderMonitor0_N26514,
      O => EncoderMonitor0_n0077_11_O
    );
  EncoderMonitor0_TrigCount_11_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_11_FROM,
      O => N46498
    );
  EncoderMonitor0_TrigCount_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_11_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_12_SW0 : X_LUT4
    generic map(
      INIT => X"BBFF"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncInc_1,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_7_12,
      O => EncoderMonitor0_TrigCount_12_FROM
    );
  EncoderMonitor0_n0077_12_Q : X_LUT4
    generic map(
      INIT => X"2033"
    )
    port map (
      ADR0 => EncoderMonitor0_N26514,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_n0279(12),
      ADR3 => N46539,
      O => EncoderMonitor0_n0077_12_O
    );
  EncoderMonitor0_TrigCount_12_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_12_FROM,
      O => N46539
    );
  EncoderMonitor0_TrigCount_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_12_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_13_SW0 : X_LUT4
    generic map(
      INIT => X"DDFF"
    )
    port map (
      ADR0 => EncoderMonitor0_vTrigCountMin,
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_7_13,
      O => EncoderMonitor0_TrigCount_13_FROM
    );
  EncoderMonitor0_n0077_13_Q : X_LUT4
    generic map(
      INIT => X"2033"
    )
    port map (
      ADR0 => EncoderMonitor0_n0279(13),
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_N26514,
      ADR3 => N46580,
      O => EncoderMonitor0_n0077_13_O
    );
  EncoderMonitor0_TrigCount_13_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_13_FROM,
      O => N46580
    );
  EncoderMonitor0_TrigCount_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_13_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_14_SW0 : X_LUT4
    generic map(
      INIT => X"F7F7"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_14,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_TrigCount_14_FROM
    );
  EncoderMonitor0_n0077_14_Q : X_LUT4
    generic map(
      INIT => X"0D05"
    )
    port map (
      ADR0 => N46621,
      ADR1 => EncoderMonitor0_N26514,
      ADR2 => EncoderMonitor0_SelEncReset_1,
      ADR3 => EncoderMonitor0_n0279(14),
      O => EncoderMonitor0_n0077_14_O
    );
  EncoderMonitor0_TrigCount_14_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_14_FROM,
      O => N46621
    );
  EncoderMonitor0_TrigCount_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_14_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_15_SW0 : X_LUT4
    generic map(
      INIT => X"F7F7"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_15,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_TrigCount_15_FROM
    );
  EncoderMonitor0_n0077_15_Q : X_LUT4
    generic map(
      INIT => X"5111"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => N46664,
      ADR2 => EncoderMonitor0_N26514,
      ADR3 => EncoderMonitor0_n0279(15),
      O => EncoderMonitor0_n0077_15_O
    );
  EncoderMonitor0_TrigCount_15_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_15_FROM,
      O => N46664
    );
  EncoderMonitor0_TrigCount_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_15_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_1_SW0 : X_LUT4
    generic map(
      INIT => X"F5FF"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_1,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => EncoderMonitor0_vTrigCountMin,
      O => EncoderMonitor0_TrigCount_1_FROM
    );
  EncoderMonitor0_n0077_1_Q : X_LUT4
    generic map(
      INIT => X"4055"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_n0279(1),
      ADR2 => EncoderMonitor0_N26514,
      ADR3 => N45934,
      O => EncoderMonitor0_n0077_1_O
    );
  EncoderMonitor0_TrigCount_1_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_1_FROM,
      O => N45934
    );
  EncoderMonitor0_TrigCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_1_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_2_SW0 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => EncoderMonitor0_vTrigCountMin,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_7_2,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_TrigCount_2_FROM
    );
  EncoderMonitor0_n0077_2_Q : X_LUT4
    generic map(
      INIT => X"3111"
    )
    port map (
      ADR0 => N46119,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_n0279(2),
      ADR3 => EncoderMonitor0_N26514,
      O => EncoderMonitor0_n0077_2_O
    );
  EncoderMonitor0_TrigCount_2_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_2_FROM,
      O => N46119
    );
  EncoderMonitor0_TrigCount_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_3_SW0 : X_LUT4
    generic map(
      INIT => X"FF77"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_3,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_TrigCount_3_FROM
    );
  EncoderMonitor0_n0077_3_Q : X_LUT4
    generic map(
      INIT => X"080F"
    )
    port map (
      ADR0 => EncoderMonitor0_N26514,
      ADR1 => EncoderMonitor0_n0279(3),
      ADR2 => EncoderMonitor0_SelEncReset_1,
      ADR3 => N46160,
      O => EncoderMonitor0_n0077_3_O
    );
  EncoderMonitor0_TrigCount_3_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_3_FROM,
      O => N46160
    );
  EncoderMonitor0_TrigCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_3_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_4_SW0 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_7_4,
      ADR2 => EncoderMonitor0_vTrigCountMin,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_TrigCount_4_FROM
    );
  EncoderMonitor0_n0077_4_Q : X_LUT4
    generic map(
      INIT => X"2033"
    )
    port map (
      ADR0 => EncoderMonitor0_n0279(4),
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_N26514,
      ADR3 => N46201,
      O => EncoderMonitor0_n0077_4_O
    );
  EncoderMonitor0_TrigCount_4_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_4_FROM,
      O => N46201
    );
  EncoderMonitor0_TrigCount_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_4_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_5_SW0 : X_LUT4
    generic map(
      INIT => X"BBFF"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncInc_1,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_7_5,
      O => EncoderMonitor0_TrigCount_5_FROM
    );
  EncoderMonitor0_n0077_5_Q : X_LUT4
    generic map(
      INIT => X"4055"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_n0279(5),
      ADR2 => EncoderMonitor0_N26514,
      ADR3 => N46242,
      O => EncoderMonitor0_n0077_5_O
    );
  EncoderMonitor0_TrigCount_5_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_5_FROM,
      O => N46242
    );
  EncoderMonitor0_TrigCount_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_5_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Ker265121 : X_LUT4
    generic map(
      INIT => X"1D1D"
    )
    port map (
      ADR0 => EncoderMonitor0_vTrigCountMin,
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => EncoderMonitor0_vTrigCountMax,
      ADR3 => VCC,
      O => EncoderMonitor0_TrigCount_6_FROM
    );
  EncoderMonitor0_n0077_6_Q : X_LUT4
    generic map(
      INIT => X"5111"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => N46283,
      ADR2 => EncoderMonitor0_n0279(6),
      ADR3 => EncoderMonitor0_N26514,
      O => EncoderMonitor0_n0077_6_O
    );
  EncoderMonitor0_TrigCount_6_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_6_FROM,
      O => EncoderMonitor0_N26514
    );
  EncoderMonitor0_TrigCount_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_6_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_7_SW0 : X_LUT4
    generic map(
      INIT => X"F7F7"
    )
    port map (
      ADR0 => EncoderMonitor0_vTrigCountMin,
      ADR1 => PerLBusInterface0_RegBank_7_7,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_TrigCount_7_FROM
    );
  EncoderMonitor0_n0077_7_Q : X_LUT4
    generic map(
      INIT => X"2033"
    )
    port map (
      ADR0 => EncoderMonitor0_N26514,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => EncoderMonitor0_n0279(7),
      ADR3 => N46324,
      O => EncoderMonitor0_n0077_7_O
    );
  EncoderMonitor0_TrigCount_7_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_7_FROM,
      O => N46324
    );
  EncoderMonitor0_TrigCount_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_7_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_8_SW0 : X_LUT4
    generic map(
      INIT => X"F5FF"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_8,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => EncoderMonitor0_vTrigCountMin,
      O => EncoderMonitor0_TrigCount_8_FROM
    );
  EncoderMonitor0_n0077_8_Q : X_LUT4
    generic map(
      INIT => X"080F"
    )
    port map (
      ADR0 => EncoderMonitor0_n0279(8),
      ADR1 => EncoderMonitor0_N26514,
      ADR2 => EncoderMonitor0_SelEncReset_1,
      ADR3 => N46365,
      O => EncoderMonitor0_n0077_8_O
    );
  EncoderMonitor0_TrigCount_8_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_8_FROM,
      O => N46365
    );
  EncoderMonitor0_TrigCount_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_8_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_9_SW0 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => PerLBusInterface0_RegBank_7_9,
      O => EncoderMonitor0_TrigCount_9_FROM
    );
  EncoderMonitor0_n0077_9_Q : X_LUT4
    generic map(
      INIT => X"4055"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncReset_1,
      ADR1 => EncoderMonitor0_N26514,
      ADR2 => EncoderMonitor0_n0279(9),
      ADR3 => N46406,
      O => EncoderMonitor0_n0077_9_O
    );
  EncoderMonitor0_TrigCount_9_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_TrigCount_9_FROM,
      O => N46406
    );
  EncoderMonitor0_TrigCount_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_TrigCount_9_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_22_489 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(10),
      IB => EncoderMonitor0_n0279_10_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_131_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_22
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_14 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_10_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_131_O,
      O => EncoderMonitor0_n0279_10_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_131 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(10),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_131_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_141 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(11),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_141_O
    );
  EncoderMonitor0_n0279_10_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_10_XORF,
      O => EncoderMonitor0_n0279(10)
    );
  EncoderMonitor0_n0279_10_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_10_XORG,
      O => EncoderMonitor0_n0279(11)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_23 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(11),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_22,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_141_O,
      O => EncoderMonitor0_n0279_10_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_15 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_22,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_141_O,
      O => EncoderMonitor0_n0279_10_XORG
    );
  EncoderMonitor0_n0279_10_CYINIT_490 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_8_CYMUXG,
      O => EncoderMonitor0_n0279_10_CYINIT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_24_491 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(12),
      IB => EncoderMonitor0_n0279_12_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_151_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_24
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_16 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_12_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_151_O,
      O => EncoderMonitor0_n0279_12_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_151 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(12),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_151_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_161 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(13),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_16
    );
  EncoderMonitor0_n0279_12_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_12_XORF,
      O => EncoderMonitor0_n0279(12)
    );
  EncoderMonitor0_n0279_12_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_12_XORG,
      O => EncoderMonitor0_n0279(13)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_25 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(13),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_24,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_16,
      O => EncoderMonitor0_n0279_12_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_17 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_24,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_16,
      O => EncoderMonitor0_n0279_12_XORG
    );
  EncoderMonitor0_n0279_12_CYINIT_492 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_10_CYMUXG,
      O => EncoderMonitor0_n0279_12_CYINIT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_26_493 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(14),
      IB => EncoderMonitor0_n0279_14_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_17,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_26
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_18 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_14_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_17,
      O => EncoderMonitor0_n0279_14_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_171 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(14),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_17
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_181 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(15),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_18
    );
  EncoderMonitor0_n0279_14_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_14_XORF,
      O => EncoderMonitor0_n0279(14)
    );
  EncoderMonitor0_n0279_14_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_14_XORG,
      O => EncoderMonitor0_n0279(15)
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_19 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_26,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_18,
      O => EncoderMonitor0_n0279_14_XORG
    );
  EncoderMonitor0_n0279_14_CYINIT_494 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_12_CYMUXG,
      O => EncoderMonitor0_n0279_14_CYINIT
    );
  EncoderMonitor0_n0279_1_LOGIC_ZERO_495 : X_ZERO
    port map (
      O => EncoderMonitor0_n0279_1_LOGIC_ZERO
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_12_496 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(0),
      IB => EncoderMonitor0_n0279_1_LOGIC_ZERO,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut1_0,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_12
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut1_01 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut1_0
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_41 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(1),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_41_O
    );
  EncoderMonitor0_n0279_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_1_XORG,
      O => EncoderMonitor0_n0279(1)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_13 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(1),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_12,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_41_O,
      O => EncoderMonitor0_n0279_1_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_5 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_12,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_41_O,
      O => EncoderMonitor0_n0279_1_XORG
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_14_497 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(2),
      IB => EncoderMonitor0_n0279_2_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_51_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_14
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_6 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_2_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_51_O,
      O => EncoderMonitor0_n0279_2_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_51 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(2),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_51_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_61 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(3),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_61_O
    );
  EncoderMonitor0_n0279_2_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_2_XORF,
      O => EncoderMonitor0_n0279(2)
    );
  EncoderMonitor0_n0279_2_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_2_XORG,
      O => EncoderMonitor0_n0279(3)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_15 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(3),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_14,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_61_O,
      O => EncoderMonitor0_n0279_2_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_7 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_14,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_61_O,
      O => EncoderMonitor0_n0279_2_XORG
    );
  EncoderMonitor0_n0279_2_CYINIT_498 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_1_CYMUXG,
      O => EncoderMonitor0_n0279_2_CYINIT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_16_499 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(4),
      IB => EncoderMonitor0_n0279_4_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_71_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_16
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_8 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_4_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_71_O,
      O => EncoderMonitor0_n0279_4_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_71 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(4),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_71_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_81 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(5),
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_81_O
    );
  EncoderMonitor0_n0279_4_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_4_XORF,
      O => EncoderMonitor0_n0279(4)
    );
  EncoderMonitor0_n0279_4_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_4_XORG,
      O => EncoderMonitor0_n0279(5)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_17 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(5),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_16,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_81_O,
      O => EncoderMonitor0_n0279_4_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_9 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_16,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_81_O,
      O => EncoderMonitor0_n0279_4_XORG
    );
  EncoderMonitor0_n0279_4_CYINIT_500 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_2_CYMUXG,
      O => EncoderMonitor0_n0279_4_CYINIT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_18_501 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(6),
      IB => EncoderMonitor0_n0279_6_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_91_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_18
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_10 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_6_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_91_O,
      O => EncoderMonitor0_n0279_6_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_91 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(6),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_91_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_101 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(7),
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_SelEncInc_1,
      ADR3 => VCC,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_101_O
    );
  EncoderMonitor0_n0279_6_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_6_XORF,
      O => EncoderMonitor0_n0279(6)
    );
  EncoderMonitor0_n0279_6_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_6_XORG,
      O => EncoderMonitor0_n0279(7)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_19 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(7),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_18,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_101_O,
      O => EncoderMonitor0_n0279_6_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_11 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_18,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_101_O,
      O => EncoderMonitor0_n0279_6_XORG
    );
  EncoderMonitor0_n0279_6_CYINIT_502 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_4_CYMUXG,
      O => EncoderMonitor0_n0279_6_CYINIT
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_20_503 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(8),
      IB => EncoderMonitor0_n0279_8_CYINIT,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_111_O,
      O => EncoderMonitor0_Maddsub_n0279_inst_cy_20
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_12 : X_XOR2
    port map (
      I0 => EncoderMonitor0_n0279_8_CYINIT,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_111_O,
      O => EncoderMonitor0_n0279_8_XORF
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_111 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_111_O
    );
  EncoderMonitor0_Maddsub_n0279_inst_lut2_121 : X_LUT4
    generic map(
      INIT => X"AA55"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => EncoderMonitor0_Maddsub_n0279_inst_lut2_121_O
    );
  EncoderMonitor0_n0279_8_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_8_XORF,
      O => EncoderMonitor0_n0279(8)
    );
  EncoderMonitor0_n0279_8_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0279_8_XORG,
      O => EncoderMonitor0_n0279(9)
    );
  EncoderMonitor0_Maddsub_n0279_inst_cy_21 : X_MUX2
    port map (
      IA => EncoderMonitor0_TrigCount(9),
      IB => EncoderMonitor0_Maddsub_n0279_inst_cy_20,
      SEL => EncoderMonitor0_Maddsub_n0279_inst_lut2_121_O,
      O => EncoderMonitor0_n0279_8_CYMUXG
    );
  EncoderMonitor0_Maddsub_n0279_inst_sum_13 : X_XOR2
    port map (
      I0 => EncoderMonitor0_Maddsub_n0279_inst_cy_20,
      I1 => EncoderMonitor0_Maddsub_n0279_inst_lut2_121_O,
      O => EncoderMonitor0_n0279_8_XORG
    );
  EncoderMonitor0_n0279_8_CYINIT_504 : X_BUF
    port map (
      I => EncoderMonitor0_n0279_6_CYMUXG,
      O => EncoderMonitor0_n0279_8_CYINIT
    );
  EncoderMonitor0_n0295_LOGIC_ZERO_505 : X_ZERO
    port map (
      O => EncoderMonitor0_n0295_LOGIC_ZERO
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_10_506 : X_MUX2
    port map (
      IA => EncoderMonitor0_n0295_LOGIC_ZERO,
      IB => EncoderMonitor0_n0295_CYINIT,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_6,
      O => EncoderMonitor0_Mcompar_n0295_inst_cy_10
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_61 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_12,
      ADR1 => PerLBusInterface0_RegBank_7_13,
      ADR2 => EncoderMonitor0_TrigCount(13),
      ADR3 => EncoderMonitor0_TrigCount(12),
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_6
    );
  EncoderMonitor0_Mcompar_n0295_inst_lut4_71 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_14,
      ADR1 => EncoderMonitor0_TrigCount(14),
      ADR2 => PerLBusInterface0_RegBank_7_15,
      ADR3 => EncoderMonitor0_TrigCount(15),
      O => EncoderMonitor0_Mcompar_n0295_inst_lut4_7
    );
  EncoderMonitor0_n0295_COUTUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0295_CYMUXG,
      O => EncoderMonitor0_n0295
    );
  EncoderMonitor0_Mcompar_n0295_inst_cy_11 : X_MUX2
    port map (
      IA => EncoderMonitor0_n0295_LOGIC_ZERO,
      IB => EncoderMonitor0_Mcompar_n0295_inst_cy_10,
      SEL => EncoderMonitor0_Mcompar_n0295_inst_lut4_7,
      O => EncoderMonitor0_n0295_CYMUXG
    );
  EncoderMonitor0_n0295_CYINIT_507 : X_BUF
    port map (
      I => EncoderMonitor0_Mcompar_n0295_inst_cy_9_CYMUXG,
      O => EncoderMonitor0_n0295_CYINIT
    );
  EncoderMonitor0_n04191 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => PerLBusInterface0_pEncoderReset(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ClkEn2,
      O => EncoderMonitor0_n0419_FROM
    );
  EncoderMonitor0_n04151 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_pEncoderReset(0),
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ClkEn2,
      O => EncoderMonitor0_n0419_GROM
    );
  EncoderMonitor0_n0419_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0419_FROM,
      O => EncoderMonitor0_n0419
    );
  EncoderMonitor0_n0419_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0419_GROM,
      O => EncoderMonitor0_n0415
    );
  EncoderMonitor0_n042822 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_18,
      ADR1 => EncoderMonitor0_EncCounts_0_19,
      ADR2 => EncoderMonitor0_EncCounts_0_17,
      ADR3 => EncoderMonitor0_EncCounts_0_16,
      O => EncoderMonitor0_n042822_O_FROM
    );
  EncoderMonitor0_n042828 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CHOICE764,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_n042822_O,
      O => EncoderMonitor0_n042822_O_GROM
    );
  EncoderMonitor0_n042822_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n042822_O_FROM,
      O => EncoderMonitor0_n042822_O
    );
  EncoderMonitor0_n042822_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n042822_O_GROM,
      O => CHOICE765
    );
  EncoderMonitor0_n042850 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_0_27,
      ADR1 => EncoderMonitor0_EncCounts_0_26,
      ADR2 => EncoderMonitor0_EncCounts_0_25,
      ADR3 => EncoderMonitor0_EncCounts_0_24,
      O => EncoderMonitor0_n042850_O_FROM
    );
  EncoderMonitor0_n042885 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE780,
      ADR1 => CHOICE776,
      ADR2 => CHOICE772,
      ADR3 => EncoderMonitor0_n042850_O,
      O => EncoderMonitor0_n042850_O_GROM
    );
  EncoderMonitor0_n042850_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n042850_O_FROM,
      O => EncoderMonitor0_n042850_O
    );
  EncoderMonitor0_n042850_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n042850_O_GROM,
      O => CHOICE782
    );
  EncoderMonitor0_n043322 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_19,
      ADR1 => EncoderMonitor0_EncCounts_1_17,
      ADR2 => EncoderMonitor0_EncCounts_1_16,
      ADR3 => EncoderMonitor0_EncCounts_1_18,
      O => EncoderMonitor0_n043322_O_FROM
    );
  EncoderMonitor0_n043328 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => CHOICE692,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_n043322_O,
      O => EncoderMonitor0_n043322_O_GROM
    );
  EncoderMonitor0_n043322_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043322_O_FROM,
      O => EncoderMonitor0_n043322_O
    );
  EncoderMonitor0_n043322_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043322_O_GROM,
      O => CHOICE693
    );
  EncoderMonitor0_n043350 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_1_27,
      ADR1 => EncoderMonitor0_EncCounts_1_26,
      ADR2 => EncoderMonitor0_EncCounts_1_24,
      ADR3 => EncoderMonitor0_EncCounts_1_25,
      O => EncoderMonitor0_n043350_O_FROM
    );
  EncoderMonitor0_n043385 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE700,
      ADR1 => CHOICE708,
      ADR2 => CHOICE704,
      ADR3 => EncoderMonitor0_n043350_O,
      O => EncoderMonitor0_n043350_O_GROM
    );
  EncoderMonitor0_n043350_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043350_O_FROM,
      O => EncoderMonitor0_n043350_O
    );
  EncoderMonitor0_n043350_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043350_O_GROM,
      O => CHOICE710
    );
  EncoderMonitor0_n0437130_1_508 : X_LUT4
    generic map(
      INIT => X"EC00"
    )
    port map (
      ADR0 => CHOICE715,
      ADR1 => EncoderMonitor0_EncoderReset(2),
      ADR2 => CHOICE747,
      ADR3 => EncoderMonitor0_ClkEn2,
      O => EncoderMonitor0_n0437130_1_FROM
    );
  EncoderMonitor0_n04521 : X_LUT4
    generic map(
      INIT => X"FF70"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_17,
      ADR1 => PerLBusInterface0_RegBank_7_18,
      ADR2 => EncoderMonitor0_n0016,
      ADR3 => EncoderMonitor0_ClkEn2,
      O => EncoderMonitor0_n0437130_1_GROM
    );
  EncoderMonitor0_n0437130_1_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0437130_1_FROM,
      O => EncoderMonitor0_n0437130_1
    );
  EncoderMonitor0_n0437130_1_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0437130_1_GROM,
      O => EncoderMonitor0_n0452
    );
  EncoderMonitor0_n043722 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_19,
      ADR1 => EncoderMonitor0_EncCounts_2_18,
      ADR2 => EncoderMonitor0_EncCounts_2_17,
      ADR3 => EncoderMonitor0_EncCounts_2_16,
      O => EncoderMonitor0_n043722_O_FROM
    );
  EncoderMonitor0_n043728 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CHOICE728,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_n043722_O,
      O => EncoderMonitor0_n043722_O_GROM
    );
  EncoderMonitor0_n043722_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043722_O_FROM,
      O => EncoderMonitor0_n043722_O
    );
  EncoderMonitor0_n043722_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043722_O_GROM,
      O => CHOICE729
    );
  EncoderMonitor0_n043750 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => EncoderMonitor0_EncCounts_2_24,
      ADR1 => EncoderMonitor0_EncCounts_2_25,
      ADR2 => EncoderMonitor0_EncCounts_2_26,
      ADR3 => EncoderMonitor0_EncCounts_2_27,
      O => EncoderMonitor0_n043750_O_FROM
    );
  EncoderMonitor0_n043785 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => CHOICE740,
      ADR1 => CHOICE736,
      ADR2 => CHOICE744,
      ADR3 => EncoderMonitor0_n043750_O,
      O => EncoderMonitor0_n043750_O_GROM
    );
  EncoderMonitor0_n043750_O_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043750_O_FROM,
      O => EncoderMonitor0_n043750_O
    );
  EncoderMonitor0_n043750_O_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n043750_O_GROM,
      O => CHOICE746
    );
  EncoderMonitor0_n04531 : X_LUT4
    generic map(
      INIT => X"AAA8"
    )
    port map (
      ADR0 => EncoderMonitor0_ClkEn2,
      ADR1 => EncoderMonitor0_SelEncInc_1,
      ADR2 => EncoderMonitor0_SelEncReset_1,
      ADR3 => EncoderMonitor0_SelEncDec,
      O => EncoderMonitor0_n0453_FROM
    );
  EncoderMonitor0_n04171 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ClkEn2,
      ADR3 => PerLBusInterface0_pEncoderReset(1),
      O => EncoderMonitor0_n0453_GROM
    );
  EncoderMonitor0_n0453_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0453_FROM,
      O => EncoderMonitor0_n0453
    );
  EncoderMonitor0_n0453_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n0453_GROM,
      O => EncoderMonitor0_n0417
    );
  EncoderMonitor0_n04541_5_509 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_n0275,
      ADR3 => EncoderMonitor0_ShiftResults,
      O => EncoderMonitor0_n04541_5_FROM
    );
  EncoderMonitor0_n04541_4_510 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults,
      ADR2 => EncoderMonitor0_n0275,
      ADR3 => VCC,
      O => EncoderMonitor0_n04541_5_GROM
    );
  EncoderMonitor0_n04541_5_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_5_FROM,
      O => EncoderMonitor0_n04541_5
    );
  EncoderMonitor0_n04541_5_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_5_GROM,
      O => EncoderMonitor0_n04541_4
    );
  EncoderMonitor0_n04541_6_511 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_n0275,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults,
      O => EncoderMonitor0_n04541_6_FROM
    );
  EncoderMonitor0_n04541_3_512 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_n0275,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_ShiftResults,
      O => EncoderMonitor0_n04541_6_GROM
    );
  EncoderMonitor0_n04541_6_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_6_FROM,
      O => EncoderMonitor0_n04541_6
    );
  EncoderMonitor0_n04541_6_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_6_GROM,
      O => EncoderMonitor0_n04541_3
    );
  EncoderMonitor0_n04541_7_513 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_ShiftResults,
      ADR3 => EncoderMonitor0_n0275,
      O => EncoderMonitor0_n04541_7_FROM
    );
  EncoderMonitor0_n04541_2_514 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_n0275,
      ADR2 => EncoderMonitor0_ShiftResults,
      ADR3 => VCC,
      O => EncoderMonitor0_n04541_7_GROM
    );
  EncoderMonitor0_n04541_7_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_7_FROM,
      O => EncoderMonitor0_n04541_7
    );
  EncoderMonitor0_n04541_7_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_7_GROM,
      O => EncoderMonitor0_n04541_2
    );
  EncoderMonitor0_n04541_8_515 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => EncoderMonitor0_n0275,
      ADR3 => EncoderMonitor0_ShiftResults,
      O => EncoderMonitor0_n04541_8_FROM
    );
  EncoderMonitor0_n04541_1_516 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_ShiftResults,
      ADR2 => EncoderMonitor0_n0275,
      ADR3 => VCC,
      O => EncoderMonitor0_n04541_8_GROM
    );
  EncoderMonitor0_n04541_8_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_8_FROM,
      O => EncoderMonitor0_n04541_8
    );
  EncoderMonitor0_n04541_8_YUSED : X_BUF
    port map (
      I => EncoderMonitor0_n04541_8_GROM,
      O => EncoderMonitor0_n04541_1
    );
  EncoderMonitor0_Ker267061 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => EncoderMonitor0_SelEncInc_1,
      ADR1 => EncoderMonitor0_IncHysterisis,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_vTrigCountMax,
      O => EncoderMonitor0_pBScanTrigger_FROM
    );
  EncoderMonitor0_n00801 : X_LUT4
    generic map(
      INIT => X"3322"
    )
    port map (
      ADR0 => EncoderMonitor0_N26680,
      ADR1 => EncoderMonitor0_SelEncReset_1,
      ADR2 => VCC,
      ADR3 => EncoderMonitor0_N26708,
      O => EncoderMonitor0_n0080
    );
  EncoderMonitor0_pBScanTrigger_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_pBScanTrigger_FROM,
      O => EncoderMonitor0_N26708
    );
  EncoderMonitor0_pBScanTrigger_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_pBScanTrigger_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_pSerialOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_pSerialOut_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_pSerialOutEn_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => EncoderMonitor0_pSerialOutEn_FROM
    );
  EncoderMonitor0_pSerialOutEn_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_pSerialOutEn_FROM,
      O => EncoderMonitor0_pSerialOutEn_X
    );
  EncoderMonitor0_pSerialOutEn_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_pSerialOutEn_SRMUX_OUTPUTNOT
    );
  I71_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_LWnR,
      ADR3 => pnFpgaCs_IBUF,
      O => EncoderMonitor0_vTrigCountMax_FROM
    );
  PerLBusInterface0_n03211 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => PerLBusInterface0_N35448,
      ADR1 => PerLBusInterface0_N35424,
      ADR2 => PerLBusInterface0_LWnR,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_n0321
    );
  EncoderMonitor0_vTrigCountMax_XUSED : X_BUF
    port map (
      I => EncoderMonitor0_vTrigCountMax_FROM,
      O => I71_N4874
    );
  EncoderMonitor0_vTrigCountMax_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => EncoderMonitor0_vTrigCountMax_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd10_In1 : X_LUT4
    generic map(
      INIT => X"F222"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28939,
      ADR1 => FocusUnitCtrl0_N28907,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd4,
      ADR3 => FocusUnitCtrl0_DelayDone,
      O => FocusUnitCtrl0_CtrlState_FFd10_In
    );
  FocusUnitCtrl0_CtrlState_FFd9_In1 : X_LUT4
    generic map(
      INIT => X"F0E4"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StartDelay,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd9,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      O => FocusUnitCtrl0_CtrlState_FFd9_In
    );
  FocusUnitCtrl0_CtrlState_FFd10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd10_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd11_In5 : X_LUT4
    generic map(
      INIT => X"F0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_N28939,
      ADR2 => PerLBusInterface0_RegBank_5_11,
      ADR3 => FocusUnitCtrl0_N28945,
      O => FocusUnitCtrl0_CtrlState_FFd11_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd11_In25 : X_LUT4
    generic map(
      INIT => X"F3F2"
    )
    port map (
      ADR0 => CHOICE634,
      ADR1 => PerLBusInterface0_RegBank_5_10,
      ADR2 => CHOICE630,
      ADR3 => CHOICE632,
      O => FocusUnitCtrl0_CtrlState_FFd11_In
    );
  FocusUnitCtrl0_CtrlState_FFd11_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd11_FROM,
      O => CHOICE632
    );
  FocusUnitCtrl0_CtrlState_FFd11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd11_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd3_In1 : X_LUT4
    generic map(
      INIT => X"F0E2"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR1 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd3,
      ADR3 => FocusUnitCtrl0_StartDelay,
      O => FocusUnitCtrl0_CtrlState_FFd3_In
    );
  FocusUnitCtrl0_CtrlState_FFd2_In1 : X_LUT4
    generic map(
      INIT => X"F0E4"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd3,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR3 => FocusUnitCtrl0_StartDelay,
      O => FocusUnitCtrl0_CtrlState_FFd2_In
    );
  FocusUnitCtrl0_CtrlState_FFd3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker288911 : X_LUT4
    generic map(
      INIT => X"ECCC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_10,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd5,
      ADR3 => FocusUnitCtrl0_DelayDataDone,
      O => FocusUnitCtrl0_CtrlState_FFd4_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd4_In11 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_Rx_nTx,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_N28893,
      O => N50048
    );
  FocusUnitCtrl0_CtrlState_FFd4_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd4_FROM,
      O => FocusUnitCtrl0_N28893
    );
  FocusUnitCtrl0_CtrlState_FFd4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd4_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_EncCounts_1_11_517 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_31,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_10_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_11
    );
  EncoderMonitor0_EncCounts_1_10_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_10_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd6_In1 : X_LUT4
    generic map(
      INIT => X"FE04"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StartDelay,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR2 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd6,
      O => FocusUnitCtrl0_CtrlState_FFd6_In
    );
  FocusUnitCtrl0_CtrlState_FFd5_In1 : X_LUT4
    generic map(
      INIT => X"FE02"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd6,
      ADR1 => FocusUnitCtrl0_StartDelay,
      ADR2 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd5,
      O => FocusUnitCtrl0_CtrlState_FFd5_In
    );
  FocusUnitCtrl0_CtrlState_FFd6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd6_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd8_In1 : X_LUT4
    generic map(
      INIT => X"F0E2"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd9,
      ADR1 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd8,
      ADR3 => FocusUnitCtrl0_StartDelay,
      O => FocusUnitCtrl0_CtrlState_FFd8_In
    );
  FocusUnitCtrl0_CtrlState_FFd7_In1 : X_LUT4
    generic map(
      INIT => X"AAB8"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR1 => FocusUnitCtrl0_StartDelay,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd8,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      O => FocusUnitCtrl0_CtrlState_FFd7_In
    );
  FocusUnitCtrl0_CtrlState_FFd8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_CtrlState_FFd8_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0060_SW0 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(3),
      ADR1 => FocusUnitCtrl0_DelayValAddr(2),
      ADR2 => PerLBusInterface0_RegBank_5_8,
      ADR3 => PerLBusInterface0_RegBank_5_9,
      O => FocusUnitCtrl0_DelayDataDone_FROM
    );
  FocusUnitCtrl0_n00521 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(3),
      ADR1 => FocusUnitCtrl0_DelayValAddr(0),
      ADR2 => FocusUnitCtrl0_DelayValAddr(1),
      ADR3 => FocusUnitCtrl0_DelayValAddr(2),
      O => FocusUnitCtrl0_n0052
    );
  FocusUnitCtrl0_DelayDataDone_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayDataDone_FROM,
      O => N48649
    );
  FocusUnitCtrl0_DelayDataDone_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayDataDone_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n00511 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR3 => FocusUnitCtrl0_StartDelay,
      O => FocusUnitCtrl0_DelayDone_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd12_In_SW0 : X_LUT4
    generic map(
      INIT => X"F533"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd5,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR2 => FocusUnitCtrl0_DelayDataDone,
      ADR3 => FocusUnitCtrl0_DelayDone,
      O => FocusUnitCtrl0_DelayDone_GROM
    );
  FocusUnitCtrl0_DelayDone_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayDone_FROM,
      O => FocusUnitCtrl0_DelayDone
    );
  FocusUnitCtrl0_DelayDone_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayDone_GROM,
      O => N47138
    );
  FocusUnitCtrl0_n00651 : X_LUT4
    generic map(
      INIT => X"FFCC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_DelayValRst,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_DelayValInc,
      O => FocusUnitCtrl0_DelayValAddr_0_FROM
    );
  FocusUnitCtrl0_n0050_0_1 : X_LUT4
    generic map(
      INIT => X"0303"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_DelayValRst,
      ADR2 => FocusUnitCtrl0_DelayValAddr(0),
      ADR3 => VCC,
      O => FocusUnitCtrl0_n0050(0)
    );
  FocusUnitCtrl0_DelayValAddr_0_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayValAddr_0_FROM,
      O => FocusUnitCtrl0_n0065
    );
  FocusUnitCtrl0_DelayValAddr_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayValAddr_0_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0060_518 : X_LUT4
    generic map(
      INIT => X"070F"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayValAddr(1),
      ADR1 => FocusUnitCtrl0_DelayValAddr(0),
      ADR2 => FocusUnitCtrl0_DelayValRst,
      ADR3 => N48649,
      O => FocusUnitCtrl0_DelayValAddr_1_FROM
    );
  FocusUnitCtrl0_n0050_1_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_n0059(1),
      ADR3 => FocusUnitCtrl0_n0060,
      O => FocusUnitCtrl0_n0050(1)
    );
  FocusUnitCtrl0_DelayValAddr_1_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayValAddr_1_FROM,
      O => FocusUnitCtrl0_n0060
    );
  FocusUnitCtrl0_DelayValAddr_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayValAddr_1_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0050_3_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => FocusUnitCtrl0_n0060,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_n0059(3),
      O => FocusUnitCtrl0_n0050(3)
    );
  FocusUnitCtrl0_n0050_2_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => FocusUnitCtrl0_n0060,
      ADR1 => FocusUnitCtrl0_n0059(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => FocusUnitCtrl0_n0050(2)
    );
  FocusUnitCtrl0_DelayValAddr_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayValAddr_3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd11_In2 : X_LUT4
    generic map(
      INIT => X"EE00"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StartDelay,
      ADR1 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd11,
      O => FocusUnitCtrl0_DelayValInc_FROM
    );
  FocusUnitCtrl0_n00451 : X_LUT4
    generic map(
      INIT => X"0500"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StartDelay,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd6,
      O => FocusUnitCtrl0_n0045
    );
  FocusUnitCtrl0_DelayValInc_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayValInc_FROM,
      O => CHOICE630
    );
  FocusUnitCtrl0_DelayValInc_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayValInc_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd13_In29 : X_LUT4
    generic map(
      INIT => X"FFDC"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28907,
      ADR1 => CHOICE347,
      ADR2 => FocusUnitCtrl0_N28945,
      ADR3 => CHOICE351,
      O => FocusUnitCtrl0_DelayValRst_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd13_In38 : X_LUT4
    generic map(
      INIT => X"FF80"
    )
    port map (
      ADR0 => FocusUnitCtrl0_DelayDone,
      ADR1 => FocusUnitCtrl0_Rx_nTx,
      ADR2 => FocusUnitCtrl0_N28893,
      ADR3 => CHOICE353,
      O => FocusUnitCtrl0_CtrlState_FFd13_In
    );
  FocusUnitCtrl0_DelayValRst_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_DelayValRst_FROM,
      O => CHOICE353
    );
  FocusUnitCtrl0_DelayValRst_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_DelayValRst_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker289321 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd5,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd3,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd6,
      O => FocusUnitCtrl0_N28934_FROM
    );
  FocusUnitCtrl0_Ker288581 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd8,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd9,
      ADR3 => FocusUnitCtrl0_N28934,
      O => FocusUnitCtrl0_N28934_GROM
    );
  FocusUnitCtrl0_N28934_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_N28934_FROM,
      O => FocusUnitCtrl0_N28934
    );
  FocusUnitCtrl0_N28934_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_N28934_GROM,
      O => FocusUnitCtrl0_N28860
    );
  FocusUnitCtrl0_CtrlState_FFd1_In_SW0 : X_LUT4
    generic map(
      INIT => X"AA88"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd10,
      ADR1 => PerLBusInterface0_RegBank_4_20,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_21,
      O => FocusUnitCtrl0_ProbeTx_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd1_In_519 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender0_pStrobeOut,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd1,
      ADR2 => FocusUnitCtrl0_ProbeTx,
      ADR3 => CHOICE607,
      O => FocusUnitCtrl0_CtrlState_FFd1_In
    );
  FocusUnitCtrl0_ProbeTx_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_ProbeTx_FROM,
      O => CHOICE607
    );
  FocusUnitCtrl0_ProbeTx_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_ProbeTx_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker28900_SW17 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => N50619,
      ADR1 => FocusUnitCtrl0_N28934,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd12,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd11,
      O => FocusUnitCtrl0_Rx_nTx_FROM
    );
  FocusUnitCtrl0_n004711 : X_LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      ADR0 => CHOICE608,
      ADR1 => FocusUnitCtrl0_Rx_nTx,
      ADR2 => CHOICE607,
      ADR3 => FocusUnitCtrl0_N28902,
      O => FocusUnitCtrl0_n0047
    );
  FocusUnitCtrl0_Rx_nTx_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_Rx_nTx_FROM,
      O => FocusUnitCtrl0_N28902
    );
  FocusUnitCtrl0_Rx_nTx_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_Rx_nTx_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender0_n0006_SW0 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(2),
      ADR1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(3),
      ADR2 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(5),
      ADR3 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(4),
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FROM
    );
  FocusUnitCtrl0_StrobeExtender0_Mxor_FeedbackBit_Result1 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(6),
      ADR2 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(5),
      ADR3 => VCC,
      O => FocusUnitCtrl0_StrobeExtender0_FeedbackBit
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FROM,
      O => N47274
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender0_n0006_520 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => N47274,
      ADR1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(1),
      ADR2 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(0),
      ADR3 => FocusUnitCtrl0_StrobeExtender0_CountLFSR(6),
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FROM
    );
  FocusUnitCtrl0_StrobeExtender0_n00071 : X_LUT4
    generic map(
      INIT => X"AAFF"
    )
    port map (
      ADR0 => FocusUnitCtrl0_ProbeTx,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_StrobeExtender0_n0006,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_GROM
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FROM,
      O => FocusUnitCtrl0_StrobeExtender0_n0006
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_GROM,
      O => FocusUnitCtrl0_StrobeExtender0_n0007
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender0_n00211 : X_LUT4
    generic map(
      INIT => X"FFAA"
    )
    port map (
      ADR0 => FocusUnitCtrl0_ProbeTx,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_StrobeExtender0_n0006,
      O => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FROM
    );
  FocusUnitCtrl0_Ker289431 : X_LUT4
    generic map(
      INIT => X"0044"
    )
    port map (
      ADR0 => FocusUnitCtrl0_ProbeTx,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd1,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_StrobeExtender0_pStrobeOut,
      O => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_GROM
    );
  FocusUnitCtrl0_StrobeExtender0_pStrobeOut_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FROM,
      O => FocusUnitCtrl0_StrobeExtender0_n0021
    );
  FocusUnitCtrl0_StrobeExtender0_pStrobeOut_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_GROM,
      O => FocusUnitCtrl0_N28945
    );
  FocusUnitCtrl0_StrobeExtender0_pStrobeOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_n00064 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(8),
      ADR1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(7),
      ADR2 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(6),
      ADR3 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(0),
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FROM
    );
  FocusUnitCtrl0_StrobeExtender1_Mxor_FeedbackBit_Result1 : X_LUT4
    generic map(
      INIT => X"33CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(8),
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(4),
      O => FocusUnitCtrl0_StrobeExtender1_FeedbackBit
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FROM,
      O => CHOICE469
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_n000614_SW0 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(3),
      ADR1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(4),
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(5),
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_GROM
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_GROM,
      O => N50615
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FROM
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FROM,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_X
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_StrobeExtender1_n000614 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(2),
      ADR1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR(1),
      ADR2 => N50615,
      ADR3 => CHOICE469,
      O => FocusUnitCtrl0_StrobeExtender1_n0006_FROM
    );
  FocusUnitCtrl0_StrobeExtender1_n00071 : X_LUT4
    generic map(
      INIT => X"F0FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_StartDelay,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_n0006,
      O => FocusUnitCtrl0_StrobeExtender1_n0006_GROM
    );
  FocusUnitCtrl0_StrobeExtender1_n0006_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_n0006_FROM,
      O => FocusUnitCtrl0_StrobeExtender1_n0006
    );
  FocusUnitCtrl0_StrobeExtender1_n0006_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_n0006_GROM,
      O => FocusUnitCtrl0_StrobeExtender1_n0007
    );
  FocusUnitCtrl0_StrobeExtender1_n00251 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_StrobeExtender1_n0006,
      ADR3 => FocusUnitCtrl0_StartDelay,
      O => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd11_In8 : X_LUT4
    generic map(
      INIT => X"0040"
    )
    port map (
      ADR0 => FocusUnitCtrl0_StartDelay,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd5,
      ADR2 => FocusUnitCtrl0_DelayDataDone,
      ADR3 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut,
      O => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_GROM
    );
  FocusUnitCtrl0_StrobeExtender1_pStrobeOut_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FROM,
      O => FocusUnitCtrl0_StrobeExtender1_n0025
    );
  FocusUnitCtrl0_StrobeExtender1_pStrobeOut_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_GROM,
      O => CHOICE634
    );
  FocusUnitCtrl0_StrobeExtender1_pStrobeOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0059_1_LOGIC_ZERO_521 : X_ZERO
    port map (
      O => FocusUnitCtrl0_n0059_1_LOGIC_ZERO
    );
  FocusUnitCtrl0_Madd_n0059_inst_cy_0_522 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => FocusUnitCtrl0_n0059_1_LOGIC_ZERO,
      SEL => FocusUnitCtrl0_Madd_n0059_inst_lut2_0,
      O => FocusUnitCtrl0_Madd_n0059_inst_cy_0
    );
  FocusUnitCtrl0_Madd_n0059_inst_lut2_01 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => FocusUnitCtrl0_DelayValAddr(0),
      ADR2 => VCC,
      ADR3 => VCC,
      O => FocusUnitCtrl0_Madd_n0059_inst_lut2_0
    );
  FocusUnitCtrl0_n0059_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_DelayValAddr(1),
      ADR3 => VCC,
      O => FocusUnitCtrl0_n0059_1_GROM
    );
  FocusUnitCtrl0_n0059_1_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_n0059_1_XORG,
      O => FocusUnitCtrl0_n0059(1)
    );
  FocusUnitCtrl0_Madd_n0059_inst_cy_1 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => FocusUnitCtrl0_Madd_n0059_inst_cy_0,
      SEL => FocusUnitCtrl0_n0059_1_GROM,
      O => FocusUnitCtrl0_n0059_1_CYMUXG
    );
  FocusUnitCtrl0_Madd_n0059_inst_sum_1 : X_XOR2
    port map (
      I0 => FocusUnitCtrl0_Madd_n0059_inst_cy_0,
      I1 => FocusUnitCtrl0_n0059_1_GROM,
      O => FocusUnitCtrl0_n0059_1_XORG
    );
  FocusUnitCtrl0_n0059_2_LOGIC_ZERO_523 : X_ZERO
    port map (
      O => FocusUnitCtrl0_n0059_2_LOGIC_ZERO
    );
  FocusUnitCtrl0_Madd_n0059_inst_cy_2_524 : X_MUX2
    port map (
      IA => FocusUnitCtrl0_n0059_2_LOGIC_ZERO,
      IB => FocusUnitCtrl0_n0059_2_CYINIT,
      SEL => FocusUnitCtrl0_n0059_2_FROM,
      O => FocusUnitCtrl0_Madd_n0059_inst_cy_2
    );
  FocusUnitCtrl0_Madd_n0059_inst_sum_2 : X_XOR2
    port map (
      I0 => FocusUnitCtrl0_n0059_2_CYINIT,
      I1 => FocusUnitCtrl0_n0059_2_FROM,
      O => FocusUnitCtrl0_n0059_2_XORF
    );
  FocusUnitCtrl0_n0059_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_DelayValAddr(2),
      ADR3 => VCC,
      O => FocusUnitCtrl0_n0059_2_FROM
    );
  FocusUnitCtrl0_DelayValAddr_3_rt_525 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_DelayValAddr(3),
      ADR3 => VCC,
      O => FocusUnitCtrl0_DelayValAddr_3_rt
    );
  FocusUnitCtrl0_n0059_2_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_n0059_2_XORF,
      O => FocusUnitCtrl0_n0059(2)
    );
  FocusUnitCtrl0_n0059_2_YUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_n0059_2_XORG,
      O => FocusUnitCtrl0_n0059(3)
    );
  FocusUnitCtrl0_Madd_n0059_inst_sum_3 : X_XOR2
    port map (
      I0 => FocusUnitCtrl0_Madd_n0059_inst_cy_2,
      I1 => FocusUnitCtrl0_DelayValAddr_3_rt,
      O => FocusUnitCtrl0_n0059_2_XORG
    );
  FocusUnitCtrl0_n0059_2_CYINIT_526 : X_BUF
    port map (
      I => FocusUnitCtrl0_n0059_1_CYMUXG,
      O => FocusUnitCtrl0_n0059_2_CYINIT
    );
  FocusUnitCtrl0_n0044_0_SW0 : X_LUT4
    generic map(
      INIT => X"FCF8"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd13,
      ADR1 => FocusUnitCtrl0_pProbeCtrl_0_Q,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR3 => FocusUnitCtrl0_N28924,
      O => FocusUnitCtrl0_pProbeCtrl_0_FROM
    );
  FocusUnitCtrl0_n0044_0_Q_527 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR2 => FocusUnitCtrl0_N28934,
      ADR3 => N47104,
      O => FocusUnitCtrl0_n0044_0_Q
    );
  FocusUnitCtrl0_pProbeCtrl_0_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeCtrl_0_FROM,
      O => N47104
    );
  FocusUnitCtrl0_pProbeCtrl_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeCtrl_0_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0044_2_SW0 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd2,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd3,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd11,
      O => FocusUnitCtrl0_pProbeCtrl_2_FROM
    );
  FocusUnitCtrl0_n0044_2_Q_528 : X_LUT4
    generic map(
      INIT => X"FFC8"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28924,
      ADR1 => FocusUnitCtrl0_pProbeCtrl_2_Q,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd13,
      ADR3 => N45601,
      O => FocusUnitCtrl0_n0044_2_Q
    );
  FocusUnitCtrl0_pProbeCtrl_2_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeCtrl_2_FROM,
      O => N45601
    );
  FocusUnitCtrl0_pProbeCtrl_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeCtrl_2_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker28900_SW17_SW0 : X_LUT4
    generic map(
      INIT => X"FFEE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd8,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd9,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd7,
      O => FocusUnitCtrl0_pProbeDClock_FROM
    );
  FocusUnitCtrl0_CtrlState_Out131 : X_LUT4
    generic map(
      INIT => X"FFFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd3,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd9,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd6,
      O => FocusUnitCtrl0_n0041
    );
  FocusUnitCtrl0_pProbeDClock_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeDClock_FROM,
      O => N50619
    );
  FocusUnitCtrl0_pProbeDClock_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeDClock_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_0_8 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_N28860,
      ADR2 => FocusUnitCtrl0_pProbeData(0),
      ADR3 => CHOICE830,
      O => FocusUnitCtrl0_pProbeData_0_FROM
    );
  FocusUnitCtrl0_n0046_0_13 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR2 => ElementNumOut(0),
      ADR3 => FocusUnitCtrl0_n0046_0_8_O,
      O => FocusUnitCtrl0_n0046_0_13_O
    );
  FocusUnitCtrl0_pProbeData_0_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_0_FROM,
      O => FocusUnitCtrl0_n0046_0_8_O
    );
  FocusUnitCtrl0_pProbeData_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_0_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_1_8 : X_LUT4
    generic map(
      INIT => X"ECEC"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28860,
      ADR1 => CHOICE823,
      ADR2 => FocusUnitCtrl0_pProbeData(1),
      ADR3 => VCC,
      O => FocusUnitCtrl0_pProbeData_1_FROM
    );
  FocusUnitCtrl0_n0046_1_13 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => ElementNumOut(1),
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR3 => FocusUnitCtrl0_n0046_1_8_O,
      O => FocusUnitCtrl0_n0046_1_13_O
    );
  FocusUnitCtrl0_pProbeData_1_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_1_FROM,
      O => FocusUnitCtrl0_n0046_1_8_O
    );
  FocusUnitCtrl0_pProbeData_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_1_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_2_8 : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28860,
      ADR1 => VCC,
      ADR2 => FocusUnitCtrl0_pProbeData(2),
      ADR3 => CHOICE837,
      O => FocusUnitCtrl0_pProbeData_2_FROM
    );
  FocusUnitCtrl0_n0046_2_13 : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => ElementNumOut(2),
      ADR2 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR3 => FocusUnitCtrl0_n0046_2_8_O,
      O => FocusUnitCtrl0_n0046_2_13_O
    );
  FocusUnitCtrl0_pProbeData_2_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_2_FROM,
      O => FocusUnitCtrl0_n0046_2_8_O
    );
  FocusUnitCtrl0_pProbeData_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_2_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_3_8 : X_LUT4
    generic map(
      INIT => X"EAEA"
    )
    port map (
      ADR0 => CHOICE844,
      ADR1 => FocusUnitCtrl0_pProbeData(3),
      ADR2 => FocusUnitCtrl0_N28860,
      ADR3 => VCC,
      O => FocusUnitCtrl0_pProbeData_3_FROM
    );
  FocusUnitCtrl0_n0046_3_13 : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => ElementNumOut(3),
      ADR1 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_n0046_3_8_O,
      O => FocusUnitCtrl0_n0046_3_13_O
    );
  FocusUnitCtrl0_pProbeData_3_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_3_FROM,
      O => FocusUnitCtrl0_n0046_3_8_O
    );
  FocusUnitCtrl0_pProbeData_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_4_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeData(4),
      ADR1 => DelayValData(4),
      ADR2 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR3 => FocusUnitCtrl0_N28860,
      O => FocusUnitCtrl0_pProbeData_4_FROM
    );
  FocusUnitCtrl0_n0046_4_Q : X_LUT4
    generic map(
      INIT => X"FFA0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR1 => VCC,
      ADR2 => ElementNumOut(4),
      ADR3 => FocusUnitCtrl0_n0046_4_SW0_O,
      O => FocusUnitCtrl0_n0046_4_O
    );
  FocusUnitCtrl0_pProbeData_4_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_4_FROM,
      O => FocusUnitCtrl0_n0046_4_SW0_O
    );
  FocusUnitCtrl0_pProbeData_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_4_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_5_SW0 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28860,
      ADR1 => FocusUnitCtrl0_pProbeData(5),
      ADR2 => DelayValData(5),
      ADR3 => FocusUnitCtrl0_CtrlState_FFd7,
      O => FocusUnitCtrl0_pProbeData_5_FROM
    );
  FocusUnitCtrl0_n0046_5_Q : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR1 => ElementNumOut(5),
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_n0046_5_SW0_O,
      O => FocusUnitCtrl0_n0046_5_O
    );
  FocusUnitCtrl0_pProbeData_5_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_5_FROM,
      O => FocusUnitCtrl0_n0046_5_SW0_O
    );
  FocusUnitCtrl0_pProbeData_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_5_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_6_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR1 => FocusUnitCtrl0_N28860,
      ADR2 => FocusUnitCtrl0_pProbeData(6),
      ADR3 => DelayValData(6),
      O => FocusUnitCtrl0_pProbeData_6_FROM
    );
  FocusUnitCtrl0_n0046_6_Q : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR1 => ElementNumOut(6),
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_n0046_6_SW0_O,
      O => FocusUnitCtrl0_n0046_6_O
    );
  FocusUnitCtrl0_pProbeData_6_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_6_FROM,
      O => FocusUnitCtrl0_n0046_6_SW0_O
    );
  FocusUnitCtrl0_pProbeData_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_6_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_n0046_7_SW0 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeData(7),
      ADR1 => DelayValData(7),
      ADR2 => FocusUnitCtrl0_CtrlState_FFd7,
      ADR3 => FocusUnitCtrl0_N28860,
      O => FocusUnitCtrl0_pProbeData_7_FROM
    );
  FocusUnitCtrl0_n0046_7_Q : X_LUT4
    generic map(
      INIT => X"FFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => ElementNumOut(7),
      ADR2 => FocusUnitCtrl0_CtrlState_FFd11,
      ADR3 => FocusUnitCtrl0_n0046_7_SW0_O,
      O => FocusUnitCtrl0_n0046_7_O
    );
  FocusUnitCtrl0_pProbeData_7_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_pProbeData_7_FROM,
      O => FocusUnitCtrl0_n0046_7_SW0_O
    );
  FocusUnitCtrl0_pProbeData_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_pProbeData_7_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker289371 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_vLastTrigger,
      ADR2 => BScanCtrl0_pTriggerOut,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd13,
      O => FocusUnitCtrl0_vLastTrigger_FROM
    );
  FocusUnitCtrl0_CtrlState_FFd12_In_529 : X_LUT4
    generic map(
      INIT => X"54FF"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_11,
      ADR1 => FocusUnitCtrl0_N28945,
      ADR2 => FocusUnitCtrl0_N28939,
      ADR3 => N47138,
      O => FocusUnitCtrl0_CtrlState_FFd12_In
    );
  FocusUnitCtrl0_vLastTrigger_XUSED : X_BUF
    port map (
      I => FocusUnitCtrl0_vLastTrigger_FROM,
      O => FocusUnitCtrl0_N28939
    );
  FocusUnitCtrl0_vLastTrigger_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => FocusUnitCtrl0_vLastTrigger_SRMUX_OUTPUTNOT
    );
  I69_0_PULLUP : X_PU
    port map (
      O => TxCountMux(6)
    );
  I69_0 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(6),
      CTL => I69_0_TINV,
      O => TxCountMux(6)
    );
  I69_0_TINV_530 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_0_TINV
    );
  I69_1_PULLUP : X_PU
    port map (
      O => TxCountMux(5)
    );
  I69_1 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(5),
      CTL => I69_1_TINV,
      O => TxCountMux(5)
    );
  I69_1_TINV_531 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_1_TINV
    );
  I69_2_PULLUP : X_PU
    port map (
      O => TxCountMux(4)
    );
  I69_2 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(4),
      CTL => I69_2_TINV,
      O => TxCountMux(4)
    );
  I69_2_TINV_532 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_2_TINV
    );
  I69_3_PULLUP : X_PU
    port map (
      O => TxCountMux(3)
    );
  I69_3 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(3),
      CTL => I69_3_TINV,
      O => TxCountMux(3)
    );
  I69_3_TINV_533 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_3_TINV
    );
  I69_4_PULLUP : X_PU
    port map (
      O => TxCountMux(2)
    );
  I69_4 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(2),
      CTL => I69_4_TINV,
      O => TxCountMux(2)
    );
  I69_4_TINV_534 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_4_TINV
    );
  I69_5_PULLUP : X_PU
    port map (
      O => TxCountMux(1)
    );
  I69_5 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(1),
      CTL => I69_5_TINV,
      O => TxCountMux(1)
    );
  I69_5_TINV_535 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_5_TINV
    );
  I69_6_PULLUP : X_PU
    port map (
      O => TxCountMux(0)
    );
  I69_6 : X_TRI
    port map (
      I => BScanCtrl0_pTxCount(0),
      CTL => I69_6_TINV,
      O => TxCountMux(0)
    );
  I69_6_TINV_536 : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I69_6_TINV
    );
  I70_0_PULLUP : X_PU
    port map (
      O => TxCountMux(6)
    );
  I70_0 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(6),
      CTL => I70_0_TINV,
      O => TxCountMux(6)
    );
  I70_0_TINV_537 : X_INV
    port map (
      I => I70_0_TMUXNOT,
      O => I70_0_TINV
    );
  I70_0_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_0_TMUXNOT
    );
  I70_1_PULLUP : X_PU
    port map (
      O => TxCountMux(5)
    );
  I70_1 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(5),
      CTL => I70_1_TINV,
      O => TxCountMux(5)
    );
  I70_1_TINV_538 : X_INV
    port map (
      I => I70_1_TMUXNOT,
      O => I70_1_TINV
    );
  I70_1_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_1_TMUXNOT
    );
  I70_2_PULLUP : X_PU
    port map (
      O => TxCountMux(4)
    );
  I70_2 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(4),
      CTL => I70_2_TINV,
      O => TxCountMux(4)
    );
  I70_2_TINV_539 : X_INV
    port map (
      I => I70_2_TMUXNOT,
      O => I70_2_TINV
    );
  I70_2_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_2_TMUXNOT
    );
  I70_3_PULLUP : X_PU
    port map (
      O => TxCountMux(3)
    );
  I70_3 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(3),
      CTL => I70_3_TINV,
      O => TxCountMux(3)
    );
  I70_3_TINV_540 : X_INV
    port map (
      I => I70_3_TMUXNOT,
      O => I70_3_TINV
    );
  I70_3_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_3_TMUXNOT
    );
  I70_4_PULLUP : X_PU
    port map (
      O => TxCountMux(2)
    );
  I70_4 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(2),
      CTL => I70_4_TINV,
      O => TxCountMux(2)
    );
  I70_4_TINV_541 : X_INV
    port map (
      I => I70_4_TMUXNOT,
      O => I70_4_TINV
    );
  I70_4_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_4_TMUXNOT
    );
  I70_5_PULLUP : X_PU
    port map (
      O => TxCountMux(1)
    );
  I70_5 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(1),
      CTL => I70_5_TINV,
      O => TxCountMux(1)
    );
  I70_5_TINV_542 : X_INV
    port map (
      I => I70_5_TMUXNOT,
      O => I70_5_TINV
    );
  I70_5_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_5_TMUXNOT
    );
  I70_6_PULLUP : X_PU
    port map (
      O => TxCountMux(0)
    );
  I70_6 : X_TRI
    port map (
      I => BScanCtrl0_RxCount(0),
      CTL => I70_6_TINV,
      O => TxCountMux(0)
    );
  I70_6_TINV_543 : X_INV
    port map (
      I => I70_6_TMUXNOT,
      O => I70_6_TINV
    );
  I70_6_TMUX : X_INV
    port map (
      I => FocusUnitCtrl0_Rx_nTx,
      O => I70_6_TMUXNOT
    );
  PerLBusInterface0_pLDout_11_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_ReadRegData(11),
      O => LD_Out_11_GROM
    );
  PerLBusInterface0_pLDout_13_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(13),
      ADR3 => PerLBusInterface0_ReadRegMask(13),
      O => LD_Out_13_GROM
    );
  PerLBusInterface0_pLDout_15_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(15),
      ADR3 => PerLBusInterface0_ReadRegMask(15),
      O => LD_Out_15_GROM
    );
  PerLBusInterface0_pLDout_17_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(17),
      ADR3 => PerLBusInterface0_ReadRegData(17),
      O => LD_Out_17_GROM
    );
  PerLBusInterface0_pLDout_19_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(19),
      ADR3 => PerLBusInterface0_ReadRegData(19),
      O => LD_Out_19_GROM
    );
  PerLBusInterface0_pLDout_1_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_ReadRegData(1),
      O => LD_Out_1_GROM
    );
  PerLBusInterface0_pLDout_21_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegMask(21),
      ADR2 => PerLBusInterface0_ReadRegData(21),
      ADR3 => VCC,
      O => LD_Out_21_GROM
    );
  PerLBusInterface0_pLDout_23_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegData(23),
      ADR1 => PerLBusInterface0_ReadRegMask(23),
      ADR2 => VCC,
      ADR3 => VCC,
      O => LD_Out_23_GROM
    );
  PerLBusInterface0_pLDout_25_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(25),
      ADR1 => PerLBusInterface0_ReadRegData(25),
      ADR2 => VCC,
      ADR3 => VCC,
      O => LD_Out_25_GROM
    );
  PerLBusInterface0_pLDout_27_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(27),
      ADR3 => PerLBusInterface0_ReadRegMask(27),
      O => LD_Out_27_GROM
    );
  PerLBusInterface0_pLDout_29_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(29),
      ADR3 => PerLBusInterface0_ReadRegMask(29),
      O => LD_Out_29_GROM
    );
  PerLBusInterface0_pLDout_31_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(31),
      ADR3 => PerLBusInterface0_ReadRegData(31),
      O => LD_Out_31_GROM
    );
  LD_Out_3_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => LD_Out_3_FROM
    );
  PerLBusInterface0_pLDout_3_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegData(3),
      ADR2 => PerLBusInterface0_ReadRegMask(3),
      ADR3 => VCC,
      O => LD_Out_3_GROM
    );
  LD_Out_3_XUSED : X_BUF
    port map (
      I => LD_Out_3_FROM,
      O => LD_Out_3_X
    );
  LD_Out_5_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => LD_Out_5_FROM
    );
  PerLBusInterface0_pLDout_5_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(5),
      ADR3 => PerLBusInterface0_ReadRegData(5),
      O => LD_Out_5_GROM
    );
  LD_Out_5_XUSED : X_BUF
    port map (
      I => LD_Out_5_FROM,
      O => LD_Out_5_X
    );
  PerLBusInterface0_pLDout_7_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(7),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(7),
      ADR3 => VCC,
      O => LD_Out_7_GROM
    );
  PerLBusInterface0_pLDout_9_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(9),
      ADR3 => PerLBusInterface0_ReadRegData(9),
      O => LD_Out_9_GROM
    );
  PerLBusInterface0_n0535_SW0 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(2),
      ADR1 => PerLBusInterface0_CalDacCount(3),
      ADR2 => PerLBusInterface0_CalClkEn1,
      ADR3 => PerLBusInterface0_CalDacCount(4),
      O => N46985_FROM
    );
  PerLBusInterface0_n0535_544 : X_LUT4
    generic map(
      INIT => X"BAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacStart,
      ADR1 => PerLBusInterface0_CalDacCount(0),
      ADR2 => PerLBusInterface0_CalDacCount(1),
      ADR3 => N46985,
      O => N46985_GROM
    );
  N46985_XUSED : X_BUF
    port map (
      I => N46985_FROM,
      O => N46985
    );
  N46985_YUSED : X_BUF
    port map (
      I => N46985_GROM,
      O => PerLBusInterface0_n0535
    );
  PerLBusInterface0_n0501_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataCount_50,
      ADR1 => PerLBusInterface0_GateDataCount_51,
      ADR2 => PerLBusInterface0_GateDataCount_52,
      ADR3 => PerLBusInterface0_GateDataCount_49,
      O => N47040_FROM
    );
  PerLBusInterface0_n0499_545 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataCount_47,
      ADR1 => PerLBusInterface0_GateDataStart,
      ADR2 => PerLBusInterface0_GateDataCount_48,
      ADR3 => N47040,
      O => N47040_GROM
    );
  N47040_XUSED : X_BUF
    port map (
      I => N47040_FROM,
      O => N47040
    );
  N47040_YUSED : X_BUF
    port map (
      I => N47040_GROM,
      O => PerLBusInterface0_n0499
    );
  TriggerDelay0_DelayCount_2_inst_lut3_331_SW0 : X_LUT4
    generic map(
      INIT => X"FFFD"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_TriggerRegs(2),
      ADR2 => TriggerDelay0_ActiveCount(0),
      ADR3 => TriggerDelay0_DelayActive(2),
      O => N50528_FROM
    );
  TriggerDelay0_DelayCount_1_inst_lut3_331_SW0 : X_LUT4
    generic map(
      INIT => X"FFEF"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(1),
      ADR1 => TriggerDelay0_ActiveCount(1),
      ADR2 => TriggerDelay0_ActiveCount(0),
      ADR3 => TriggerDelay0_TriggerRegs(2),
      O => N50528_GROM
    );
  N50528_XUSED : X_BUF
    port map (
      I => N50528_FROM,
      O => N50528
    );
  N50528_YUSED : X_BUF
    port map (
      I => N50528_GROM,
      O => N50524
    );
  TriggerDelay0_DelayCount_3_inst_lut3_341_SW0 : X_LUT4
    generic map(
      INIT => X"EFFF"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs(2),
      ADR1 => TriggerDelay0_DelayActive(3),
      ADR2 => TriggerDelay0_ActiveCount(1),
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => N50552_FROM
    );
  TriggerDelay0_DelayCount_3_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"0F27"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_0,
      ADR2 => TriggerDelay0_DelayCount_3_57,
      ADR3 => N50552,
      O => N50552_GROM
    );
  N50552_XUSED : X_BUF
    port map (
      I => N50552_FROM,
      O => N50552
    );
  N50552_YUSED : X_BUF
    port map (
      I => N50552_GROM,
      O => TriggerDelay0_DelayCount_3_inst_lut3_281_O
    );
  N50588_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N50588_FROM
    );
  TriggerDelay0_n004975_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_60,
      ADR1 => TriggerDelay0_DelayCount_2_59,
      ADR2 => TriggerDelay0_DelayCount_2_58,
      ADR3 => TriggerDelay0_DelayCount_2_57,
      O => N50588_GROM
    );
  N50588_XUSED : X_BUF
    port map (
      I => N50588_FROM,
      O => N50588_X
    );
  N50588_YUSED : X_BUF
    port map (
      I => N50588_GROM,
      O => N50588
    );
  TriggerDelay0_n004875_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_3_60,
      ADR1 => TriggerDelay0_DelayCount_3_59,
      ADR2 => TriggerDelay0_DelayCount_3_57,
      ADR3 => TriggerDelay0_DelayCount_3_58,
      O => N50592_GROM
    );
  N50592_YUSED : X_BUF
    port map (
      I => N50592_GROM,
      O => N50592
    );
  TriggerDelay0_n005175_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_59,
      ADR1 => TriggerDelay0_DelayCount_0_58,
      ADR2 => TriggerDelay0_DelayCount_0_57,
      ADR3 => TriggerDelay0_DelayCount_0_60,
      O => N50596_GROM
    );
  N50596_YUSED : X_BUF
    port map (
      I => N50596_GROM,
      O => N50596
    );
  N50600_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => N50600_FROM
    );
  TriggerDelay0_n005075_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_58,
      ADR1 => TriggerDelay0_DelayCount_1_57,
      ADR2 => TriggerDelay0_DelayCount_1_60,
      ADR3 => TriggerDelay0_DelayCount_1_59,
      O => N50600_GROM
    );
  N50600_XUSED : X_BUF
    port map (
      I => N50600_FROM,
      O => N50600_X
    );
  N50600_YUSED : X_BUF
    port map (
      I => N50600_GROM,
      O => N50600
    );
  TriggerDelay0_DelayCount_2_inst_lut3_371_SW0 : X_LUT4
    generic map(
      INIT => X"FFFD"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(1),
      ADR1 => TriggerDelay0_TriggerRegs(2),
      ADR2 => TriggerDelay0_DelayActive(2),
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => N50903_FROM
    );
  TriggerDelay0_DelayCount_2_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"5535"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_57,
      ADR1 => PerLBusInterface0_RegBank_1_0,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => N50903,
      O => N50903_GROM
    );
  N50903_XUSED : X_BUF
    port map (
      I => N50903_FROM,
      O => N50903
    );
  N50903_YUSED : X_BUF
    port map (
      I => N50903_GROM,
      O => TriggerDelay0_DelayCount_2_inst_lut3_281_O
    );
  PerLBusInterface0_n04761 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_6_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_BlkRamWrite_GROM
    );
  PerLBusInterface0_BlkRamWrite_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_BlkRamWrite_GROM,
      O => PerLBusInterface0_n0476
    );
  PerLBusInterface0_BlkRamWrite_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_BlkRamWrite_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Ker354041 : X_LUT4
    generic map(
      INIT => X"3000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_vCount(2),
      ADR2 => PerLBusInterface0_vCount(0),
      ADR3 => PerLBusInterface0_vCount(1),
      O => PerLBusInterface0_N35406
    );
  PerLBusInterface0_n03101 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => PerLBusInterface0_vCount(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_vCount(0),
      ADR3 => PerLBusInterface0_vCount(1),
      O => PerLBusInterface0_n0310
    );
  PerLBusInterface0_CalClkEn2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalClkEn2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_CalDacActive_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalDacActive_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0275_1_1 : X_LUT4
    generic map(
      INIT => X"8800"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacActive,
      ADR1 => PerLBusInterface0_CalClkEn1,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0376(1),
      O => PerLBusInterface0_n0275(1)
    );
  PerLBusInterface0_n0275_0_1 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_CalDacActive,
      ADR2 => PerLBusInterface0_CalDacCount(0),
      ADR3 => PerLBusInterface0_CalClkEn1,
      O => PerLBusInterface0_n0275(0)
    );
  PerLBusInterface0_CalDacCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalDacCount_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0275_3_1 : X_LUT4
    generic map(
      INIT => X"C000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_n0376(3),
      ADR2 => PerLBusInterface0_CalClkEn1,
      ADR3 => PerLBusInterface0_CalDacActive,
      O => PerLBusInterface0_n0275(3)
    );
  PerLBusInterface0_n0275_2_1 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacActive,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_n0376(2),
      ADR3 => PerLBusInterface0_CalClkEn1,
      O => PerLBusInterface0_n0275(2)
    );
  PerLBusInterface0_CalDacCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalDacCount_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n05361 : X_LUT4
    generic map(
      INIT => X"FAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacStart,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_CalClkEn1,
      ADR3 => PerLBusInterface0_CalDacActive,
      O => PerLBusInterface0_CalDacCount_4_FROM
    );
  PerLBusInterface0_n0275_4_1 : X_LUT4
    generic map(
      INIT => X"8080"
    )
    port map (
      ADR0 => PerLBusInterface0_n0376(4),
      ADR1 => PerLBusInterface0_CalDacActive,
      ADR2 => PerLBusInterface0_CalClkEn1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0275(4)
    );
  PerLBusInterface0_CalDacCount_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacCount_4_FROM,
      O => PerLBusInterface0_n0536
    );
  PerLBusInterface0_CalDacCount_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalDacCount_4_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0280_Result_0_SW1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_3_0,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_n0372,
      ADR3 => VCC,
      O => PerLBusInterface0_CalDacShiftReg_0_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_0_Q : X_LUT4
    generic map(
      INIT => X"AFA8"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(0),
      ADR1 => N45718,
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50851,
      O => PerLBusInterface0_n0280(0)
    );
  PerLBusInterface0_CalDacShiftReg_0_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_0_FROM,
      O => N50851
    );
  PerLBusInterface0_Mmux_n0280_Result_10_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_3_10,
      ADR1 => PerLBusInterface0_n0372,
      ADR2 => PerLBusInterface0_CalDacShiftReg(9),
      ADR3 => PerLBusInterface0_n0409,
      O => PerLBusInterface0_CalDacShiftReg_10_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_10_Q : X_LUT4
    generic map(
      INIT => X"CFC8"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacShiftReg(10),
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50863,
      O => PerLBusInterface0_n0280(10)
    );
  PerLBusInterface0_CalDacShiftReg_10_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_10_FROM,
      O => N50863
    );
  PerLBusInterface0_Mmux_n0280_Result_11_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(10),
      ADR1 => PerLBusInterface0_n0409,
      ADR2 => PerLBusInterface0_RegBank_3_11,
      ADR3 => PerLBusInterface0_n0372,
      O => PerLBusInterface0_CalDacShiftReg_11_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_11_Q : X_LUT4
    generic map(
      INIT => X"CFC8"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacShiftReg(11),
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50847,
      O => PerLBusInterface0_n0280(11)
    );
  PerLBusInterface0_CalDacShiftReg_11_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_11_FROM,
      O => N50847
    );
  PerLBusInterface0_Mmux_n0280_Result_12_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_n0372,
      ADR1 => PerLBusInterface0_RegBank_3_12,
      ADR2 => PerLBusInterface0_n0409,
      ADR3 => PerLBusInterface0_CalDacShiftReg(11),
      O => PerLBusInterface0_CalDacShiftReg_12_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_12_Q : X_LUT4
    generic map(
      INIT => X"CFC8"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacShiftReg(12),
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50871,
      O => PerLBusInterface0_n0280(12)
    );
  PerLBusInterface0_CalDacShiftReg_12_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_12_FROM,
      O => N50871
    );
  PerLBusInterface0_Mmux_n0280_Result_13_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(12),
      ADR1 => PerLBusInterface0_n0409,
      ADR2 => PerLBusInterface0_n0372,
      ADR3 => PerLBusInterface0_RegBank_3_13,
      O => PerLBusInterface0_CalDacShiftReg_13_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_13_Q : X_LUT4
    generic map(
      INIT => X"CFC8"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacShiftReg(13),
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50843,
      O => PerLBusInterface0_n0280(13)
    );
  PerLBusInterface0_CalDacShiftReg_13_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_13_FROM,
      O => N50843
    );
  PerLBusInterface0_Mmux_n0280_Result_1_SW1 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => PerLBusInterface0_n0409,
      ADR1 => PerLBusInterface0_RegBank_3_1,
      ADR2 => PerLBusInterface0_CalDacShiftReg(0),
      ADR3 => PerLBusInterface0_n0372,
      O => PerLBusInterface0_CalDacShiftReg_1_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_1_Q : X_LUT4
    generic map(
      INIT => X"CFC8"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacShiftReg(1),
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50887,
      O => PerLBusInterface0_n0280(1)
    );
  PerLBusInterface0_CalDacShiftReg_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_1_FROM,
      O => N50887
    );
  PerLBusInterface0_Mmux_n0280_Result_2_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_3_2,
      ADR1 => PerLBusInterface0_n0372,
      ADR2 => PerLBusInterface0_n0409,
      ADR3 => PerLBusInterface0_CalDacShiftReg(1),
      O => PerLBusInterface0_CalDacShiftReg_2_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_2_Q : X_LUT4
    generic map(
      INIT => X"BBA8"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(2),
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => N45718,
      ADR3 => N50891,
      O => PerLBusInterface0_n0280(2)
    );
  PerLBusInterface0_CalDacShiftReg_2_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_2_FROM,
      O => N50891
    );
  PerLBusInterface0_Mmux_n0280_Result_3_SW1 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => PerLBusInterface0_n0372,
      ADR1 => PerLBusInterface0_CalDacShiftReg(2),
      ADR2 => PerLBusInterface0_n0409,
      ADR3 => PerLBusInterface0_RegBank_3_3,
      O => PerLBusInterface0_CalDacShiftReg_3_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_3_Q : X_LUT4
    generic map(
      INIT => X"AFA8"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(3),
      ADR1 => N45718,
      ADR2 => PerLBusInterface0_CalDacCount(4),
      ADR3 => N50883,
      O => PerLBusInterface0_n0280(3)
    );
  PerLBusInterface0_CalDacShiftReg_3_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_3_FROM,
      O => N50883
    );
  PerLBusInterface0_Mmux_n0280_Result_4_SW1 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => PerLBusInterface0_n0409,
      ADR1 => PerLBusInterface0_RegBank_3_4,
      ADR2 => PerLBusInterface0_n0372,
      ADR3 => PerLBusInterface0_CalDacShiftReg(3),
      O => PerLBusInterface0_CalDacShiftReg_4_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_4_Q : X_LUT4
    generic map(
      INIT => X"F3E0"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => PerLBusInterface0_CalDacShiftReg(4),
      ADR3 => N50859,
      O => PerLBusInterface0_n0280(4)
    );
  PerLBusInterface0_CalDacShiftReg_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_4_FROM,
      O => N50859
    );
  PerLBusInterface0_Mmux_n0280_Result_5_SW1 : X_LUT4
    generic map(
      INIT => X"EAC0"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(4),
      ADR1 => PerLBusInterface0_RegBank_3_5,
      ADR2 => PerLBusInterface0_n0372,
      ADR3 => PerLBusInterface0_n0409,
      O => PerLBusInterface0_CalDacShiftReg_5_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_5_Q : X_LUT4
    generic map(
      INIT => X"F5E0"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(4),
      ADR1 => N45718,
      ADR2 => PerLBusInterface0_CalDacShiftReg(5),
      ADR3 => N50855,
      O => PerLBusInterface0_n0280(5)
    );
  PerLBusInterface0_CalDacShiftReg_5_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_5_FROM,
      O => N50855
    );
  PerLBusInterface0_Mmux_n0280_Result_6_SW1 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => PerLBusInterface0_n0372,
      ADR1 => PerLBusInterface0_CalDacShiftReg(5),
      ADR2 => PerLBusInterface0_RegBank_3_6,
      ADR3 => PerLBusInterface0_n0409,
      O => PerLBusInterface0_CalDacShiftReg_6_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_6_Q : X_LUT4
    generic map(
      INIT => X"F5E0"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(4),
      ADR1 => N45718,
      ADR2 => PerLBusInterface0_CalDacShiftReg(6),
      ADR3 => N50879,
      O => PerLBusInterface0_n0280(6)
    );
  PerLBusInterface0_CalDacShiftReg_6_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_6_FROM,
      O => N50879
    );
  PerLBusInterface0_Mmux_n0280_Result_7_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_3_7,
      ADR1 => PerLBusInterface0_n0372,
      ADR2 => PerLBusInterface0_CalDacShiftReg(6),
      ADR3 => PerLBusInterface0_n0409,
      O => PerLBusInterface0_CalDacShiftReg_7_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_7_Q : X_LUT4
    generic map(
      INIT => X"F3E0"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => PerLBusInterface0_CalDacShiftReg(7),
      ADR3 => N50839,
      O => PerLBusInterface0_n0280(7)
    );
  PerLBusInterface0_CalDacShiftReg_7_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_7_FROM,
      O => N50839
    );
  PerLBusInterface0_Mmux_n0280_Result_8_SW1 : X_LUT4
    generic map(
      INIT => X"ECA0"
    )
    port map (
      ADR0 => PerLBusInterface0_n0372,
      ADR1 => PerLBusInterface0_n0409,
      ADR2 => PerLBusInterface0_RegBank_3_8,
      ADR3 => PerLBusInterface0_CalDacShiftReg(7),
      O => PerLBusInterface0_CalDacShiftReg_8_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_8_Q : X_LUT4
    generic map(
      INIT => X"DDC8"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacCount(4),
      ADR1 => PerLBusInterface0_CalDacShiftReg(8),
      ADR2 => N45718,
      ADR3 => N50875,
      O => PerLBusInterface0_n0280(8)
    );
  PerLBusInterface0_CalDacShiftReg_8_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_8_FROM,
      O => N50875
    );
  PerLBusInterface0_Mmux_n0280_Result_9_SW1 : X_LUT4
    generic map(
      INIT => X"F888"
    )
    port map (
      ADR0 => PerLBusInterface0_CalDacShiftReg(8),
      ADR1 => PerLBusInterface0_n0409,
      ADR2 => PerLBusInterface0_RegBank_3_9,
      ADR3 => PerLBusInterface0_n0372,
      O => PerLBusInterface0_CalDacShiftReg_9_FROM
    );
  PerLBusInterface0_Mmux_n0280_Result_9_Q : X_LUT4
    generic map(
      INIT => X"F3E0"
    )
    port map (
      ADR0 => N45718,
      ADR1 => PerLBusInterface0_CalDacCount(4),
      ADR2 => PerLBusInterface0_CalDacShiftReg(9),
      ADR3 => N50867,
      O => PerLBusInterface0_n0280(9)
    );
  PerLBusInterface0_CalDacShiftReg_9_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg_9_FROM,
      O => N50867
    );
  PerLBusInterface0_n04671 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_3_Q,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_CalDacStart_GROM
    );
  PerLBusInterface0_CalDacStart_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_CalDacStart_GROM,
      O => PerLBusInterface0_n0467
    );
  PerLBusInterface0_CalDacStart_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_CalDacStart_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n04501 : X_LUT4
    generic map(
      INIT => X"FF50"
    )
    port map (
      ADR0 => PerLBusInterface0_n0347,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_vIncAddr,
      ADR3 => PerLBusInterface0_DelayValAddrRst,
      O => PerLBusInterface0_DelayValAddr_0_FROM
    );
  PerLBusInterface0_n02491 : X_LUT4
    generic map(
      INIT => X"000A"
    )
    port map (
      ADR0 => PerLBusInterface0_n0347,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_DelayValAddrRst,
      ADR3 => PerLBusInterface0_DelayValAddr(0),
      O => PerLBusInterface0_n0249
    );
  PerLBusInterface0_DelayValAddr_0_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_DelayValAddr_0_FROM,
      O => PerLBusInterface0_n0450
    );
  PerLBusInterface0_DelayValAddr_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_0_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03471 : X_LUT4
    generic map(
      INIT => X"7DBE"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_8,
      ADR1 => PerLBusInterface0_DelayValAddr(1),
      ADR2 => PerLBusInterface0_RegBank_5_9,
      ADR3 => PerLBusInterface0_DelayValAddr(0),
      O => PerLBusInterface0_DelayValAddr_1_FROM
    );
  PerLBusInterface0_n02481 : X_LUT4
    generic map(
      INIT => X"0600"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddr(0),
      ADR1 => PerLBusInterface0_DelayValAddr(1),
      ADR2 => PerLBusInterface0_DelayValAddrRst,
      ADR3 => PerLBusInterface0_n0347,
      O => PerLBusInterface0_n0248
    );
  PerLBusInterface0_DelayValAddr_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_DelayValAddr_1_FROM,
      O => PerLBusInterface0_n0347
    );
  PerLBusInterface0_DelayValAddr_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n02451 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_n0152(1),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_DelayValAddrRst,
      O => PerLBusInterface0_n0245
    );
  PerLBusInterface0_n02461 : X_LUT4
    generic map(
      INIT => X"0033"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_DelayValAddrRst,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_DelayValAddr(2),
      O => PerLBusInterface0_n0246
    );
  PerLBusInterface0_DelayValAddr_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n02431 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_n0152(3),
      ADR3 => PerLBusInterface0_DelayValAddrRst,
      O => PerLBusInterface0_n0243
    );
  PerLBusInterface0_n02441 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_DelayValAddrRst,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0152(2),
      O => PerLBusInterface0_n0244
    );
  PerLBusInterface0_DelayValAddr_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n02411 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddrRst,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0152(5),
      O => PerLBusInterface0_n0241
    );
  PerLBusInterface0_n02421 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => PerLBusInterface0_n0152(4),
      ADR1 => PerLBusInterface0_DelayValAddrRst,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0242
    );
  PerLBusInterface0_DelayValAddr_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n04581 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_DelayValAddrRst,
      ADR3 => PerLBusInterface0_vIncAddr,
      O => PerLBusInterface0_DelayValAddr_8_FROM
    );
  PerLBusInterface0_n02401 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddrRst,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0152(6),
      O => PerLBusInterface0_n0240
    );
  PerLBusInterface0_DelayValAddr_8_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_DelayValAddr_8_FROM,
      O => PerLBusInterface0_n0458
    );
  PerLBusInterface0_DelayValAddr_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddr_8_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n04731 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_5_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_DelayValAddrRst_GROM
    );
  PerLBusInterface0_DelayValAddrRst_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_DelayValAddrRst_GROM,
      O => PerLBusInterface0_n0473
    );
  PerLBusInterface0_DelayValAddrRst_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DelayValAddrRst_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n05101 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegWriteEn_19_Q,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_DoFocus_FROM
    );
  PerLBusInterface0_n0508_546 : X_LUT4
    generic map(
      INIT => X"FFEC"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusCount_53,
      ADR1 => PerLBusInterface0_DoFocus,
      ADR2 => PerLBusInterface0_N35411,
      ADR3 => PerLBusInterface0_n0510,
      O => PerLBusInterface0_DoFocus_GROM
    );
  PerLBusInterface0_DoFocus_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_DoFocus_FROM,
      O => PerLBusInterface0_n0510
    );
  PerLBusInterface0_DoFocus_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_DoFocus_GROM,
      O => PerLBusInterface0_n0508
    );
  PerLBusInterface0_DoFocus_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_DoFocus_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_FocusCount_53_LOGIC_ONE_547 : X_ONE
    port map (
      O => PerLBusInterface0_FocusCount_53_LOGIC_ONE
    );
  PerLBusInterface0_FocusCount_inst_cy_140_548 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => PerLBusInterface0_FocusCount_53_LOGIC_ONE,
      SEL => PerLBusInterface0_DoFocus_rt,
      O => PerLBusInterface0_FocusCount_inst_cy_140
    );
  PerLBusInterface0_DoFocus_rt_549 : X_LUT4
    generic map(
      INIT => X"CCCC"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => PerLBusInterface0_DoFocus,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_DoFocus_rt
    );
  PerLBusInterface0_FocusCount_inst_lut3_241 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_DoFocus,
      ADR3 => PerLBusInterface0_FocusCount_53,
      O => PerLBusInterface0_FocusCount_inst_lut3_24
    );
  PerLBusInterface0_FocusCount_inst_cy_141 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => PerLBusInterface0_FocusCount_inst_cy_140,
      SEL => PerLBusInterface0_FocusCount_inst_lut3_24,
      O => PerLBusInterface0_FocusCount_53_CYMUXG
    );
  PerLBusInterface0_FocusCount_inst_sum_124_550 : X_XOR2
    port map (
      I0 => PerLBusInterface0_FocusCount_inst_cy_140,
      I1 => PerLBusInterface0_FocusCount_inst_lut3_24,
      O => PerLBusInterface0_FocusCount_inst_sum_124
    );
  PerLBusInterface0_FocusCount_53_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_FocusCount_53_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_FocusCount_54_LOGIC_ONE_551 : X_ONE
    port map (
      O => PerLBusInterface0_FocusCount_54_LOGIC_ONE
    );
  PerLBusInterface0_FocusCount_inst_cy_142_552 : X_MUX2
    port map (
      IA => PerLBusInterface0_FocusCount_54_LOGIC_ONE,
      IB => PerLBusInterface0_FocusCount_54_CYINIT,
      SEL => PerLBusInterface0_FocusCount_inst_lut3_25,
      O => PerLBusInterface0_FocusCount_inst_cy_142
    );
  PerLBusInterface0_FocusCount_inst_sum_125_553 : X_XOR2
    port map (
      I0 => PerLBusInterface0_FocusCount_54_CYINIT,
      I1 => PerLBusInterface0_FocusCount_inst_lut3_25,
      O => PerLBusInterface0_FocusCount_inst_sum_125
    );
  PerLBusInterface0_FocusCount_inst_lut3_251 : X_LUT4
    generic map(
      INIT => X"0055"
    )
    port map (
      ADR0 => PerLBusInterface0_DoFocus,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_FocusCount_54,
      O => PerLBusInterface0_FocusCount_inst_lut3_25
    );
  PerLBusInterface0_FocusCount_inst_lut3_261 : X_LUT4
    generic map(
      INIT => X"0505"
    )
    port map (
      ADR0 => PerLBusInterface0_DoFocus,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_FocusCount_55,
      ADR3 => VCC,
      O => PerLBusInterface0_FocusCount_inst_lut3_26
    );
  PerLBusInterface0_FocusCount_inst_cy_143 : X_MUX2
    port map (
      IA => PerLBusInterface0_FocusCount_54_LOGIC_ONE,
      IB => PerLBusInterface0_FocusCount_inst_cy_142,
      SEL => PerLBusInterface0_FocusCount_inst_lut3_26,
      O => PerLBusInterface0_FocusCount_54_CYMUXG
    );
  PerLBusInterface0_FocusCount_inst_sum_126_554 : X_XOR2
    port map (
      I0 => PerLBusInterface0_FocusCount_inst_cy_142,
      I1 => PerLBusInterface0_FocusCount_inst_lut3_26,
      O => PerLBusInterface0_FocusCount_inst_sum_126
    );
  PerLBusInterface0_FocusCount_54_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_FocusCount_54_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_FocusCount_54_CYINIT_555 : X_BUF
    port map (
      I => PerLBusInterface0_FocusCount_53_CYMUXG,
      O => PerLBusInterface0_FocusCount_54_CYINIT
    );
  PerLBusInterface0_FocusCount_inst_sum_127_556 : X_XOR2
    port map (
      I0 => PerLBusInterface0_FocusCount_56_CYINIT,
      I1 => PerLBusInterface0_FocusCount_inst_lut3_27,
      O => PerLBusInterface0_FocusCount_inst_sum_127
    );
  PerLBusInterface0_FocusCount_inst_lut3_271 : X_LUT4
    generic map(
      INIT => X"0055"
    )
    port map (
      ADR0 => PerLBusInterface0_DoFocus,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_FocusCount_56,
      O => PerLBusInterface0_FocusCount_inst_lut3_27
    );
  PerLBusInterface0_n05041 : X_LUT4
    generic map(
      INIT => X"DCDC"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusCount_53,
      ADR1 => PerLBusInterface0_DoFocus,
      ADR2 => PerLBusInterface0_N35411,
      ADR3 => VCC,
      O => PerLBusInterface0_FocusCount_56_GROM
    );
  PerLBusInterface0_FocusCount_56_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_FocusCount_56_GROM,
      O => PerLBusInterface0_n0504
    );
  PerLBusInterface0_FocusCount_56_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_FocusCount_56_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_FocusCount_56_CYINIT_557 : X_BUF
    port map (
      I => PerLBusInterface0_FocusCount_54_CYMUXG,
      O => PerLBusInterface0_FocusCount_56_CYINIT
    );
  PerLBusInterface0_n0264_SW0 : X_LUT4
    generic map(
      INIT => X"DD44"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusCount_54,
      ADR1 => PerLBusInterface0_FocusCount_56,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_FocusCtrl,
      O => PerLBusInterface0_FocusCtrl_FROM
    );
  PerLBusInterface0_n0264_558 : X_LUT4
    generic map(
      INIT => X"DC8C"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusCount_53,
      ADR1 => PerLBusInterface0_FocusCtrl,
      ADR2 => PerLBusInterface0_FocusCount_55,
      ADR3 => N44611,
      O => PerLBusInterface0_n0264
    );
  PerLBusInterface0_FocusCtrl_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_FocusCtrl_FROM,
      O => N44611
    );
  PerLBusInterface0_FocusCtrl_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_FocusCtrl_SRMUX_OUTPUTNOT
    );
  Mmux_ProbeDClk_Result1 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeDClock,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_FocusCtrl,
      ADR3 => PerLBusInterface0_FocusWrite,
      O => PerLBusInterface0_FocusWrite_FROM
    );
  Mmux_ProbeDSel_Result1 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeCtrl_2_Q,
      ADR1 => PerLBusInterface0_FocusWrite,
      ADR2 => PerLBusInterface0_RegBank_19_10_Q,
      ADR3 => VCC,
      O => PerLBusInterface0_FocusWrite_GROM
    );
  PerLBusInterface0_FocusWrite_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_FocusWrite_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n04791 : X_LUT4
    generic map(
      INIT => X"0C0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegWriteEn_7_Q,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_ForceBScan_FROM
    );
  PerLBusInterface0_n03371 : X_LUT4
    generic map(
      INIT => X"0A00"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_7_Q,
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => N49946,
      O => PerLBusInterface0_n0337
    );
  PerLBusInterface0_ForceBScan_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ForceBScan_FROM,
      O => PerLBusInterface0_n0479
    );
  PerLBusInterface0_ForceBScan_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ForceBScan_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataCount_47_LOGIC_ZERO_559 : X_ZERO
    port map (
      O => PerLBusInterface0_GateDataCount_47_LOGIC_ZERO
    );
  PerLBusInterface0_GateDataCount_inst_cy_133_560 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => PerLBusInterface0_GateDataCount_47_LOGIC_ZERO,
      SEL => PerLBusInterface0_GateDataStart_rt,
      O => PerLBusInterface0_GateDataCount_inst_cy_133
    );
  PerLBusInterface0_GateDataStart_rt_561 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataStart,
      O => PerLBusInterface0_GateDataStart_rt
    );
  PerLBusInterface0_GateDataCount_inst_lut3_181 : X_LUT4
    generic map(
      INIT => X"FFF0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataCount_47,
      ADR3 => PerLBusInterface0_GateDataStart,
      O => PerLBusInterface0_GateDataCount_inst_lut3_18
    );
  PerLBusInterface0_GateDataCount_inst_cy_134 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => PerLBusInterface0_GateDataCount_inst_cy_133,
      SEL => PerLBusInterface0_GateDataCount_inst_lut3_18,
      O => PerLBusInterface0_GateDataCount_47_CYMUXG
    );
  PerLBusInterface0_GateDataCount_inst_sum_118_562 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_inst_cy_133,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_18,
      O => PerLBusInterface0_GateDataCount_inst_sum_118
    );
  PerLBusInterface0_GateDataCount_47_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataCount_47_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataCount_48_LOGIC_ZERO_563 : X_ZERO
    port map (
      O => PerLBusInterface0_GateDataCount_48_LOGIC_ZERO
    );
  PerLBusInterface0_GateDataCount_inst_cy_135_564 : X_MUX2
    port map (
      IA => PerLBusInterface0_GateDataCount_48_LOGIC_ZERO,
      IB => PerLBusInterface0_GateDataCount_48_CYINIT,
      SEL => PerLBusInterface0_GateDataCount_inst_lut3_19,
      O => PerLBusInterface0_GateDataCount_inst_cy_135
    );
  PerLBusInterface0_GateDataCount_inst_sum_119_565 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_48_CYINIT,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_19,
      O => PerLBusInterface0_GateDataCount_inst_sum_119
    );
  PerLBusInterface0_GateDataCount_inst_lut3_191 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataStart,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataCount_48,
      O => PerLBusInterface0_GateDataCount_inst_lut3_19
    );
  PerLBusInterface0_GateDataCount_inst_lut3_201 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataCount_49,
      ADR3 => PerLBusInterface0_GateDataStart,
      O => PerLBusInterface0_GateDataCount_inst_lut3_20
    );
  PerLBusInterface0_GateDataCount_inst_cy_136 : X_MUX2
    port map (
      IA => PerLBusInterface0_GateDataCount_48_LOGIC_ZERO,
      IB => PerLBusInterface0_GateDataCount_inst_cy_135,
      SEL => PerLBusInterface0_GateDataCount_inst_lut3_20,
      O => PerLBusInterface0_GateDataCount_48_CYMUXG
    );
  PerLBusInterface0_GateDataCount_inst_sum_120_566 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_inst_cy_135,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_20,
      O => PerLBusInterface0_GateDataCount_inst_sum_120
    );
  PerLBusInterface0_GateDataCount_48_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataCount_48_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataCount_48_CYINIT_567 : X_BUF
    port map (
      I => PerLBusInterface0_GateDataCount_47_CYMUXG,
      O => PerLBusInterface0_GateDataCount_48_CYINIT
    );
  PerLBusInterface0_GateDataCount_50_LOGIC_ZERO_568 : X_ZERO
    port map (
      O => PerLBusInterface0_GateDataCount_50_LOGIC_ZERO
    );
  PerLBusInterface0_GateDataCount_inst_cy_137_569 : X_MUX2
    port map (
      IA => PerLBusInterface0_GateDataCount_50_LOGIC_ZERO,
      IB => PerLBusInterface0_GateDataCount_50_CYINIT,
      SEL => PerLBusInterface0_GateDataCount_inst_lut3_21,
      O => PerLBusInterface0_GateDataCount_inst_cy_137
    );
  PerLBusInterface0_GateDataCount_inst_sum_121_570 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_50_CYINIT,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_21,
      O => PerLBusInterface0_GateDataCount_inst_sum_121
    );
  PerLBusInterface0_GateDataCount_inst_lut3_211 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataStart,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataCount_50,
      O => PerLBusInterface0_GateDataCount_inst_lut3_21
    );
  PerLBusInterface0_GateDataCount_inst_lut3_221 : X_LUT4
    generic map(
      INIT => X"2222"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataCount_51,
      ADR1 => PerLBusInterface0_GateDataStart,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_GateDataCount_inst_lut3_22
    );
  PerLBusInterface0_GateDataCount_inst_cy_138 : X_MUX2
    port map (
      IA => PerLBusInterface0_GateDataCount_50_LOGIC_ZERO,
      IB => PerLBusInterface0_GateDataCount_inst_cy_137,
      SEL => PerLBusInterface0_GateDataCount_inst_lut3_22,
      O => PerLBusInterface0_GateDataCount_50_CYMUXG
    );
  PerLBusInterface0_GateDataCount_inst_sum_122_571 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_inst_cy_137,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_22,
      O => PerLBusInterface0_GateDataCount_inst_sum_122
    );
  PerLBusInterface0_GateDataCount_50_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataCount_50_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataCount_50_CYINIT_572 : X_BUF
    port map (
      I => PerLBusInterface0_GateDataCount_48_CYMUXG,
      O => PerLBusInterface0_GateDataCount_50_CYINIT
    );
  PerLBusInterface0_GateDataCount_inst_sum_123_573 : X_XOR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_52_CYINIT,
      I1 => PerLBusInterface0_GateDataCount_inst_lut3_23,
      O => PerLBusInterface0_GateDataCount_inst_sum_123
    );
  PerLBusInterface0_GateDataCount_inst_lut3_231 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataStart,
      ADR1 => PerLBusInterface0_GateDataCount_52,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_GateDataCount_inst_lut3_23
    );
  PerLBusInterface0_n0501_574 : X_LUT4
    generic map(
      INIT => X"AAAB"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataStart,
      ADR1 => PerLBusInterface0_GateDataCount_47,
      ADR2 => PerLBusInterface0_GateDataCount_48,
      ADR3 => N47040,
      O => PerLBusInterface0_GateDataCount_52_GROM
    );
  PerLBusInterface0_GateDataCount_52_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_GateDataCount_52_GROM,
      O => PerLBusInterface0_n0501
    );
  PerLBusInterface0_GateDataCount_52_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataCount_52_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataCount_52_CYINIT_575 : X_BUF
    port map (
      I => PerLBusInterface0_GateDataCount_50_CYMUXG,
      O => PerLBusInterface0_GateDataCount_52_CYINIT
    );
  PerLBusInterface0_n04821 : X_LUT4
    generic map(
      INIT => X"AEAE"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut,
      ADR1 => PerLBusInterface0_RegWriteEn_14_Q,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_GateDataOut_FROM
    );
  PerLBusInterface0_n04821_1_576 : X_LUT4
    generic map(
      INIT => X"CECE"
    )
    port map (
      ADR0 => PerLBusInterface0_RegWriteEn_14_Q,
      ADR1 => PerLBusInterface0_GateDataOut,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_GateDataOut_GROM
    );
  PerLBusInterface0_GateDataOut_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_GateDataOut_FROM,
      O => PerLBusInterface0_n0482
    );
  PerLBusInterface0_GateDataOut_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_GateDataOut_GROM,
      O => PerLBusInterface0_n04821_1
    );
  PerLBusInterface0_GateDataOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataOut_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_GateDataOut_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataOut_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n04861 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegWriteEn_16_Q,
      O => PerLBusInterface0_GateDataStart_GROM
    );
  PerLBusInterface0_GateDataStart_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_GateDataStart_GROM,
      O => PerLBusInterface0_n0486
    );
  PerLBusInterface0_GateDataStart_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_GateDataStart_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_I108_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I108_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_0,
      CTL => PerLBusInterface0_I108_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I108_0_TINV_577 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I108_0_TINV
    );
  PerLBusInterface0_I109_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I109_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_1,
      CTL => PerLBusInterface0_I109_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I109_0_TINV_578 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I109_0_TINV
    );
  PerLBusInterface0_I110_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I110_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_2,
      CTL => PerLBusInterface0_I110_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I110_0_TINV_579 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I110_0_TINV
    );
  PerLBusInterface0_I111_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I111_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_3,
      CTL => PerLBusInterface0_I111_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I111_0_TINV_580 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I111_0_TINV
    );
  PerLBusInterface0_I112_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I112_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_4,
      CTL => PerLBusInterface0_I112_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I112_0_TINV_581 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I112_0_TINV
    );
  PerLBusInterface0_I113_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I113_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_5,
      CTL => PerLBusInterface0_I113_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I113_0_TINV_582 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I113_0_TINV
    );
  PerLBusInterface0_I114_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I114_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_6,
      CTL => PerLBusInterface0_I114_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I114_0_TINV_583 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I114_0_TINV
    );
  PerLBusInterface0_I115_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I115_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_7,
      CTL => PerLBusInterface0_I115_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I115_0_TINV_584 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I115_0_TINV
    );
  PerLBusInterface0_I116_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I116_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_8,
      CTL => PerLBusInterface0_I116_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I116_0_TINV_585 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I116_0_TINV
    );
  PerLBusInterface0_I117_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I117_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_9,
      CTL => PerLBusInterface0_I117_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I117_0_TINV_586 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I117_0_TINV
    );
  PerLBusInterface0_I118_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I118_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_10,
      CTL => PerLBusInterface0_I118_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I118_0_TINV_587 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I118_0_TINV
    );
  PerLBusInterface0_I119_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I119_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_11,
      CTL => PerLBusInterface0_I119_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I119_0_TINV_588 : X_INV
    port map (
      I => PerLBusInterface0_I132_N4995,
      O => PerLBusInterface0_I119_0_TINV
    );
  PerLBusInterface0_I120_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I120_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_12,
      CTL => PerLBusInterface0_I120_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I120_0_TINV_589 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I120_0_TINV
    );
  PerLBusInterface0_I121_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I121_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_13,
      CTL => PerLBusInterface0_I121_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I121_0_TINV_590 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I121_0_TINV
    );
  PerLBusInterface0_I122_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I122_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_14,
      CTL => PerLBusInterface0_I122_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I122_0_TINV_591 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I122_0_TINV
    );
  PerLBusInterface0_I243_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I243_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_20,
      CTL => PerLBusInterface0_I243_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I243_0_TINV_592 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I243_0_TINV
    );
  PerLBusInterface0_I244_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I244_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_21,
      CTL => PerLBusInterface0_I244_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I244_0_TINV_593 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I244_0_TINV
    );
  PerLBusInterface0_I245_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I245_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_22,
      CTL => PerLBusInterface0_I245_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I245_0_TINV_594 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I245_0_TINV
    );
  PerLBusInterface0_I246_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I246_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_23,
      CTL => PerLBusInterface0_I246_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I246_0_TINV_595 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I246_0_TINV
    );
  PerLBusInterface0_I247_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I247_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_24,
      CTL => PerLBusInterface0_I247_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I247_0_TINV_596 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I247_0_TINV
    );
  PerLBusInterface0_I248_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I248_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_25,
      CTL => PerLBusInterface0_I248_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I248_0_TINV_597 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I248_0_TINV
    );
  PerLBusInterface0_I249_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I249_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_26,
      CTL => PerLBusInterface0_I249_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I249_0_TINV_598 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I249_0_TINV
    );
  PerLBusInterface0_I250_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I250_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_27,
      CTL => PerLBusInterface0_I250_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I250_0_TINV_599 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I250_0_TINV
    );
  PerLBusInterface0_I251_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I251_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_28,
      CTL => PerLBusInterface0_I251_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I251_0_TINV_600 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I251_0_TINV
    );
  PerLBusInterface0_I252_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I252_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_29,
      CTL => PerLBusInterface0_I252_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I252_0_TINV_601 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I252_0_TINV
    );
  PerLBusInterface0_I253_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I253_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_30,
      CTL => PerLBusInterface0_I253_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I253_0_TINV_602 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I253_0_TINV
    );
  PerLBusInterface0_I254_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I254_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_31,
      CTL => PerLBusInterface0_I254_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I254_0_TINV_603 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I254_0_TINV
    );
  PerLBusInterface0_I255_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I255_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_32,
      CTL => PerLBusInterface0_I255_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I255_0_TINV_604 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I255_0_TINV
    );
  PerLBusInterface0_I256_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I256_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_33,
      CTL => PerLBusInterface0_I256_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I256_0_TINV_605 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I256_0_TINV
    );
  PerLBusInterface0_I257_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I257_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_34,
      CTL => PerLBusInterface0_I257_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I257_0_TINV_606 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I257_0_TINV
    );
  PerLBusInterface0_I258_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I258_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_35,
      CTL => PerLBusInterface0_I258_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I258_0_TINV_607 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I258_0_TINV
    );
  PerLBusInterface0_I259_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I259_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_36,
      CTL => PerLBusInterface0_I259_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I259_0_TINV_608 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I259_0_TINV
    );
  PerLBusInterface0_I260_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I260_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_37,
      CTL => PerLBusInterface0_I260_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I260_0_TINV_609 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I260_0_TINV
    );
  PerLBusInterface0_I261_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I261_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_38,
      CTL => PerLBusInterface0_I261_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I261_0_TINV_610 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I261_0_TINV
    );
  PerLBusInterface0_I262_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I262_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_39,
      CTL => PerLBusInterface0_I262_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I262_0_TINV_611 : X_INV
    port map (
      I => PerLBusInterface0_I262_N49951_1,
      O => PerLBusInterface0_I262_0_TINV
    );
  PerLBusInterface0_I263_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I263_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_8,
      CTL => PerLBusInterface0_I263_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I263_0_TINV_612 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I263_0_TINV
    );
  PerLBusInterface0_I264_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I264_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_9,
      CTL => PerLBusInterface0_I264_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I264_0_TINV_613 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I264_0_TINV
    );
  PerLBusInterface0_I265_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I265_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_10,
      CTL => PerLBusInterface0_I265_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I265_0_TINV_614 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I265_0_TINV
    );
  PerLBusInterface0_I266_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I266_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_11,
      CTL => PerLBusInterface0_I266_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I266_0_TINV_615 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I266_0_TINV
    );
  PerLBusInterface0_I267_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I267_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_12,
      CTL => PerLBusInterface0_I267_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I267_0_TINV_616 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I267_0_TINV
    );
  PerLBusInterface0_I268_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I268_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_13,
      CTL => PerLBusInterface0_I268_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I268_0_TINV_617 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I268_0_TINV
    );
  PerLBusInterface0_I269_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I269_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_14,
      CTL => PerLBusInterface0_I269_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I269_0_TINV_618 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I269_0_TINV
    );
  PerLBusInterface0_I270_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I270_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_15,
      CTL => PerLBusInterface0_I270_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I270_0_TINV_619 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I270_0_TINV
    );
  PerLBusInterface0_I271_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I271_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_16,
      CTL => PerLBusInterface0_I271_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I271_0_TINV_620 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I271_0_TINV
    );
  PerLBusInterface0_I272_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I272_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_17,
      CTL => PerLBusInterface0_I272_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I272_0_TINV_621 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I272_0_TINV
    );
  PerLBusInterface0_I273_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I273_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_18,
      CTL => PerLBusInterface0_I273_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I273_0_TINV_622 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I273_0_TINV
    );
  PerLBusInterface0_I274_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I274_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_19,
      CTL => PerLBusInterface0_I274_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I274_0_TINV_623 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I274_0_TINV
    );
  PerLBusInterface0_I275_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I275_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_20,
      CTL => PerLBusInterface0_I275_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I275_0_TINV_624 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I275_0_TINV
    );
  PerLBusInterface0_I276_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I276_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_21,
      CTL => PerLBusInterface0_I276_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I276_0_TINV_625 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I276_0_TINV
    );
  PerLBusInterface0_I277_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I277_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_22,
      CTL => PerLBusInterface0_I277_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I277_0_TINV_626 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I277_0_TINV
    );
  PerLBusInterface0_I278_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I278_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_23,
      CTL => PerLBusInterface0_I278_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I278_0_TINV_627 : X_INV
    port map (
      I => PerLBusInterface0_I294_N4995,
      O => PerLBusInterface0_I278_0_TINV
    );
  PerLBusInterface0_I279_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I279_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_24,
      CTL => PerLBusInterface0_I279_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I279_0_TINV_628 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I279_0_TINV
    );
  PerLBusInterface0_I280_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I280_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_25,
      CTL => PerLBusInterface0_I280_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I280_0_TINV_629 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I280_0_TINV
    );
  PerLBusInterface0_I281_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I281_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_26,
      CTL => PerLBusInterface0_I281_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I281_0_TINV_630 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I281_0_TINV
    );
  PerLBusInterface0_I282_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I282_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_27,
      CTL => PerLBusInterface0_I282_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I282_0_TINV_631 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I282_0_TINV
    );
  PerLBusInterface0_I283_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I283_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_28,
      CTL => PerLBusInterface0_I283_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I283_0_TINV_632 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I283_0_TINV
    );
  PerLBusInterface0_I284_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I284_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_29,
      CTL => PerLBusInterface0_I284_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I284_0_TINV_633 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I284_0_TINV
    );
  PerLBusInterface0_I285_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I285_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_30,
      CTL => PerLBusInterface0_I285_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I285_0_TINV_634 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I285_0_TINV
    );
  PerLBusInterface0_I286_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I286_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_31,
      CTL => PerLBusInterface0_I286_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I286_0_TINV_635 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I286_0_TINV
    );
  PerLBusInterface0_I287_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I287_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_32,
      CTL => PerLBusInterface0_I287_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I287_0_TINV_636 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I287_0_TINV
    );
  PerLBusInterface0_I288_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I288_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_33,
      CTL => PerLBusInterface0_I288_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I288_0_TINV_637 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I288_0_TINV
    );
  PerLBusInterface0_I289_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I289_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_34,
      CTL => PerLBusInterface0_I289_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I289_0_TINV_638 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I289_0_TINV
    );
  PerLBusInterface0_I290_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I290_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_35,
      CTL => PerLBusInterface0_I290_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I290_0_TINV_639 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I290_0_TINV
    );
  PerLBusInterface0_I291_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I291_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_36,
      CTL => PerLBusInterface0_I291_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I291_0_TINV_640 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I291_0_TINV
    );
  PerLBusInterface0_I292_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I292_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_37,
      CTL => PerLBusInterface0_I292_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I292_0_TINV_641 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I292_0_TINV
    );
  PerLBusInterface0_I293_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I293_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_38,
      CTL => PerLBusInterface0_I293_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I293_0_TINV_642 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I293_0_TINV
    );
  PerLBusInterface0_I294_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I294_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_1_39,
      CTL => PerLBusInterface0_I294_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I294_0_TINV_643 : X_INV
    port map (
      I => PerLBusInterface0_I294_N49951_1,
      O => PerLBusInterface0_I294_0_TINV
    );
  PerLBusInterface0_I294_N49951_1_644 : X_LUT4
    generic map(
      INIT => X"FF77"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => PerLBusInterface0_N35395,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_IntAddr(3),
      O => PerLBusInterface0_I294_N49951_1_FROM
    );
  PerLBusInterface0_I294_N49951 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_N35395,
      ADR3 => PerLBusInterface0_IntAddr(3),
      O => PerLBusInterface0_I294_N49951_1_GROM
    );
  PerLBusInterface0_I294_N49951_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I294_N49951_1_FROM,
      O => PerLBusInterface0_I294_N49951_1
    );
  PerLBusInterface0_I294_N49951_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I294_N49951_1_GROM,
      O => PerLBusInterface0_I294_N4995
    );
  PerLBusInterface0_I295_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I295_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_8,
      CTL => PerLBusInterface0_I295_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I295_0_TINV_645 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I295_0_TINV
    );
  PerLBusInterface0_I296_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I296_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_9,
      CTL => PerLBusInterface0_I296_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I296_0_TINV_646 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I296_0_TINV
    );
  PerLBusInterface0_I297_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I297_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_10,
      CTL => PerLBusInterface0_I297_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I297_0_TINV_647 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I297_0_TINV
    );
  PerLBusInterface0_I298_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I298_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_11,
      CTL => PerLBusInterface0_I298_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I298_0_TINV_648 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I298_0_TINV
    );
  PerLBusInterface0_I299_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I299_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_12,
      CTL => PerLBusInterface0_I299_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I299_0_TINV_649 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I299_0_TINV
    );
  PerLBusInterface0_I300_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I300_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_13,
      CTL => PerLBusInterface0_I300_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I300_0_TINV_650 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I300_0_TINV
    );
  PerLBusInterface0_I301_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I301_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_14,
      CTL => PerLBusInterface0_I301_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I301_0_TINV_651 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I301_0_TINV
    );
  PerLBusInterface0_I302_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I302_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_15,
      CTL => PerLBusInterface0_I302_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I302_0_TINV_652 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I302_0_TINV
    );
  PerLBusInterface0_I303_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I303_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_16,
      CTL => PerLBusInterface0_I303_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I303_0_TINV_653 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I303_0_TINV
    );
  PerLBusInterface0_I304_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I304_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_17,
      CTL => PerLBusInterface0_I304_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I304_0_TINV_654 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I304_0_TINV
    );
  PerLBusInterface0_I305_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I305_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_18,
      CTL => PerLBusInterface0_I305_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I305_0_TINV_655 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I305_0_TINV
    );
  PerLBusInterface0_I306_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I306_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_19,
      CTL => PerLBusInterface0_I306_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I306_0_TINV_656 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I306_0_TINV
    );
  PerLBusInterface0_I307_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I307_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_20,
      CTL => PerLBusInterface0_I307_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I307_0_TINV_657 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I307_0_TINV
    );
  PerLBusInterface0_I308_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I308_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_21,
      CTL => PerLBusInterface0_I308_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I308_0_TINV_658 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I308_0_TINV
    );
  PerLBusInterface0_I309_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I309_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_22,
      CTL => PerLBusInterface0_I309_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I309_0_TINV_659 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I309_0_TINV
    );
  PerLBusInterface0_I310_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I310_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_23,
      CTL => PerLBusInterface0_I310_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I310_0_TINV_660 : X_INV
    port map (
      I => PerLBusInterface0_I326_N4995,
      O => PerLBusInterface0_I310_0_TINV
    );
  PerLBusInterface0_I311_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I311_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_24,
      CTL => PerLBusInterface0_I311_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I311_0_TINV_661 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I311_0_TINV
    );
  PerLBusInterface0_I312_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I312_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_25,
      CTL => PerLBusInterface0_I312_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I312_0_TINV_662 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I312_0_TINV
    );
  PerLBusInterface0_I313_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I313_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_26,
      CTL => PerLBusInterface0_I313_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I313_0_TINV_663 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I313_0_TINV
    );
  PerLBusInterface0_I314_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I314_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_27,
      CTL => PerLBusInterface0_I314_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I314_0_TINV_664 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I314_0_TINV
    );
  PerLBusInterface0_I315_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I315_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_28,
      CTL => PerLBusInterface0_I315_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I315_0_TINV_665 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I315_0_TINV
    );
  PerLBusInterface0_I316_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I316_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_29,
      CTL => PerLBusInterface0_I316_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I316_0_TINV_666 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I316_0_TINV
    );
  PerLBusInterface0_I317_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I317_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_30,
      CTL => PerLBusInterface0_I317_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I317_0_TINV_667 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I317_0_TINV
    );
  PerLBusInterface0_I318_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I318_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_31,
      CTL => PerLBusInterface0_I318_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I318_0_TINV_668 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I318_0_TINV
    );
  PerLBusInterface0_I319_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I319_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_32,
      CTL => PerLBusInterface0_I319_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I319_0_TINV_669 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I319_0_TINV
    );
  PerLBusInterface0_I320_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I320_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_33,
      CTL => PerLBusInterface0_I320_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I320_0_TINV_670 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I320_0_TINV
    );
  PerLBusInterface0_I321_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I321_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_34,
      CTL => PerLBusInterface0_I321_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I321_0_TINV_671 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I321_0_TINV
    );
  PerLBusInterface0_I322_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I322_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_35,
      CTL => PerLBusInterface0_I322_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I322_0_TINV_672 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I322_0_TINV
    );
  PerLBusInterface0_I323_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I323_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_36,
      CTL => PerLBusInterface0_I323_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I323_0_TINV_673 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I323_0_TINV
    );
  PerLBusInterface0_I324_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I324_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_37,
      CTL => PerLBusInterface0_I324_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I324_0_TINV_674 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I324_0_TINV
    );
  PerLBusInterface0_I325_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I325_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_38,
      CTL => PerLBusInterface0_I325_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I325_0_TINV_675 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I325_0_TINV
    );
  PerLBusInterface0_I326_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I326_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_2_39,
      CTL => PerLBusInterface0_I326_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I326_0_TINV_676 : X_INV
    port map (
      I => PerLBusInterface0_I326_N49951_1,
      O => PerLBusInterface0_I326_0_TINV
    );
  PerLBusInterface0_I326_N49951_1_677 : X_LUT4
    generic map(
      INIT => X"AFFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35395,
      O => PerLBusInterface0_I326_N49951_1_FROM
    );
  PerLBusInterface0_I326_N49951 : X_LUT4
    generic map(
      INIT => X"CFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35395,
      O => PerLBusInterface0_I326_N49951_1_GROM
    );
  PerLBusInterface0_I326_N49951_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I326_N49951_1_FROM,
      O => PerLBusInterface0_I326_N49951_1
    );
  PerLBusInterface0_I326_N49951_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I326_N49951_1_GROM,
      O => PerLBusInterface0_I326_N4995
    );
  PerLBusInterface0_I327_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I327_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_16_0,
      CTL => PerLBusInterface0_I327_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I327_0_TINV_678 : X_INV
    port map (
      I => PerLBusInterface0_I331_N4995,
      O => PerLBusInterface0_I327_0_TINV
    );
  PerLBusInterface0_I328_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I328_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_16_1,
      CTL => PerLBusInterface0_I328_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I328_0_TINV_679 : X_INV
    port map (
      I => PerLBusInterface0_I331_N4995,
      O => PerLBusInterface0_I328_0_TINV
    );
  PerLBusInterface0_I329_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I329_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_16_2,
      CTL => PerLBusInterface0_I329_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I329_0_TINV_680 : X_INV
    port map (
      I => PerLBusInterface0_I331_N4995,
      O => PerLBusInterface0_I329_0_TINV
    );
  PerLBusInterface0_I330_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I330_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I330_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I330_0_TINV_681 : X_INV
    port map (
      I => PerLBusInterface0_I331_N4995,
      O => PerLBusInterface0_I330_0_TINV
    );
  PerLBusInterface0_I123_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I123_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_15,
      CTL => PerLBusInterface0_I123_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I123_0_TINV_682 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I123_0_TINV
    );
  PerLBusInterface0_I126_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I126_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_18,
      CTL => PerLBusInterface0_I126_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I126_0_TINV_683 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I126_0_TINV
    );
  PerLBusInterface0_I127_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I127_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_19,
      CTL => PerLBusInterface0_I127_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I127_0_TINV_684 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I127_0_TINV
    );
  PerLBusInterface0_I128_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I128_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_20,
      CTL => PerLBusInterface0_I128_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I128_0_TINV_685 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I128_0_TINV
    );
  PerLBusInterface0_I129_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I129_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_21,
      CTL => PerLBusInterface0_I129_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I129_0_TINV_686 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I129_0_TINV
    );
  PerLBusInterface0_I130_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I130_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_22,
      CTL => PerLBusInterface0_I130_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I130_0_TINV_687 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I130_0_TINV
    );
  PerLBusInterface0_I131_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I131_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_23,
      CTL => PerLBusInterface0_I131_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I131_0_TINV_688 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I131_0_TINV
    );
  PerLBusInterface0_I132_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I132_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_0_24,
      CTL => PerLBusInterface0_I132_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I132_0_TINV_689 : X_INV
    port map (
      I => PerLBusInterface0_I132_N49951_1,
      O => PerLBusInterface0_I132_0_TINV
    );
  PerLBusInterface0_I140_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I140_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_0,
      CTL => PerLBusInterface0_I140_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I140_0_TINV_690 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I140_0_TINV
    );
  PerLBusInterface0_I141_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I141_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_1,
      CTL => PerLBusInterface0_I141_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I141_0_TINV_691 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I141_0_TINV
    );
  PerLBusInterface0_I142_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I142_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_2,
      CTL => PerLBusInterface0_I142_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I142_0_TINV_692 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I142_0_TINV
    );
  PerLBusInterface0_I143_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I143_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_3,
      CTL => PerLBusInterface0_I143_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I143_0_TINV_693 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I143_0_TINV
    );
  PerLBusInterface0_I144_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I144_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_4,
      CTL => PerLBusInterface0_I144_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I144_0_TINV_694 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I144_0_TINV
    );
  PerLBusInterface0_I145_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I145_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_5,
      CTL => PerLBusInterface0_I145_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I145_0_TINV_695 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I145_0_TINV
    );
  PerLBusInterface0_I146_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I146_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_6,
      CTL => PerLBusInterface0_I146_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I146_0_TINV_696 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I146_0_TINV
    );
  PerLBusInterface0_I147_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I147_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_7,
      CTL => PerLBusInterface0_I147_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I147_0_TINV_697 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I147_0_TINV
    );
  PerLBusInterface0_I148_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I148_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_8,
      CTL => PerLBusInterface0_I148_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I148_0_TINV_698 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I148_0_TINV
    );
  PerLBusInterface0_I149_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I149_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_9,
      CTL => PerLBusInterface0_I149_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I149_0_TINV_699 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I149_0_TINV
    );
  PerLBusInterface0_I150_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I150_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_10,
      CTL => PerLBusInterface0_I150_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I150_0_TINV_700 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I150_0_TINV
    );
  PerLBusInterface0_I151_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I151_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_11,
      CTL => PerLBusInterface0_I151_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I151_0_TINV_701 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I151_0_TINV
    );
  PerLBusInterface0_I152_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I152_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_12,
      CTL => PerLBusInterface0_I152_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I152_0_TINV_702 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I152_0_TINV
    );
  PerLBusInterface0_I153_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I153_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_13,
      CTL => PerLBusInterface0_I153_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I153_0_TINV_703 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I153_0_TINV
    );
  PerLBusInterface0_I154_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I154_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_14,
      CTL => PerLBusInterface0_I154_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I154_0_TINV_704 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I154_0_TINV
    );
  PerLBusInterface0_I155_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I155_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_15,
      CTL => PerLBusInterface0_I155_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I155_0_TINV_705 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I155_0_TINV
    );
  PerLBusInterface0_I156_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I156_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_1_16,
      CTL => PerLBusInterface0_I156_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I156_0_TINV_706 : X_INV
    port map (
      I => PerLBusInterface0_I156_N4995,
      O => PerLBusInterface0_I156_0_TINV
    );
  PerLBusInterface0_I180_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I180_0 : X_TRI
    port map (
      I => PerLBusInterface0_CalDacActive,
      CTL => PerLBusInterface0_I180_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I180_0_TINV_707 : X_INV
    port map (
      I => PerLBusInterface0_I180_N4995,
      O => PerLBusInterface0_I180_0_TINV
    );
  PerLBusInterface0_I180_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"5FFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35462,
      O => PerLBusInterface0_I180_N4995_FROM
    );
  PerLBusInterface0_I132_N49951_1_708 : X_LUT4
    generic map(
      INIT => X"FFF5"
    )
    port map (
      ADR0 => PerLBusInterface0_N35462,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_IntAddr(2),
      O => PerLBusInterface0_I180_N4995_GROM
    );
  PerLBusInterface0_I180_N4995_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I180_N4995_FROM,
      O => PerLBusInterface0_I180_N4995
    );
  PerLBusInterface0_I180_N4995_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I180_N4995_GROM,
      O => PerLBusInterface0_I132_N49951_1
    );
  PerLBusInterface0_I181_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I181_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_0,
      CTL => PerLBusInterface0_I181_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I181_0_TINV_709 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I181_0_TINV
    );
  PerLBusInterface0_I182_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I182_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_1,
      CTL => PerLBusInterface0_I182_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I182_0_TINV_710 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I182_0_TINV
    );
  PerLBusInterface0_I183_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I183_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_2,
      CTL => PerLBusInterface0_I183_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I183_0_TINV_711 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I183_0_TINV
    );
  PerLBusInterface0_I184_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I184_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_3,
      CTL => PerLBusInterface0_I184_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I184_0_TINV_712 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I184_0_TINV
    );
  PerLBusInterface0_I185_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I185_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_4,
      CTL => PerLBusInterface0_I185_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I185_0_TINV_713 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I185_0_TINV
    );
  PerLBusInterface0_I186_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I186_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_5,
      CTL => PerLBusInterface0_I186_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I186_0_TINV_714 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I186_0_TINV
    );
  PerLBusInterface0_I187_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I187_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_6,
      CTL => PerLBusInterface0_I187_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I187_0_TINV_715 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I187_0_TINV
    );
  PerLBusInterface0_I188_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I188_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_7,
      CTL => PerLBusInterface0_I188_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I188_0_TINV_716 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I188_0_TINV
    );
  PerLBusInterface0_I189_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I189_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_8,
      CTL => PerLBusInterface0_I189_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I189_0_TINV_717 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I189_0_TINV
    );
  PerLBusInterface0_I190_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I190_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_9,
      CTL => PerLBusInterface0_I190_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I190_0_TINV_718 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I190_0_TINV
    );
  PerLBusInterface0_I191_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I191_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_10,
      CTL => PerLBusInterface0_I191_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I191_0_TINV_719 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I191_0_TINV
    );
  PerLBusInterface0_I192_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I192_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_11,
      CTL => PerLBusInterface0_I192_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I192_0_TINV_720 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I192_0_TINV
    );
  PerLBusInterface0_I193_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I193_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_12,
      CTL => PerLBusInterface0_I193_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I193_0_TINV_721 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I193_0_TINV
    );
  PerLBusInterface0_I194_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I194_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_13,
      CTL => PerLBusInterface0_I194_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I194_0_TINV_722 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I194_0_TINV
    );
  PerLBusInterface0_I195_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I195_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_14,
      CTL => PerLBusInterface0_I195_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I195_0_TINV_723 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I195_0_TINV
    );
  PerLBusInterface0_I196_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I196_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_15,
      CTL => PerLBusInterface0_I196_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I196_0_TINV_724 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I196_0_TINV
    );
  PerLBusInterface0_I197_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I197_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_16,
      CTL => PerLBusInterface0_I197_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I197_0_TINV_725 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I197_0_TINV
    );
  PerLBusInterface0_I198_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I198_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_20,
      CTL => PerLBusInterface0_I198_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I198_0_TINV_726 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I198_0_TINV
    );
  PerLBusInterface0_I199_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I199_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_4_21,
      CTL => PerLBusInterface0_I199_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I199_0_TINV_727 : X_INV
    port map (
      I => PerLBusInterface0_I199_N4995,
      O => PerLBusInterface0_I199_0_TINV
    );
  PerLBusInterface0_I200_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I200_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_0,
      CTL => PerLBusInterface0_I200_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I200_0_TINV_728 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I200_0_TINV
    );
  PerLBusInterface0_I201_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I201_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_1,
      CTL => PerLBusInterface0_I201_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I201_0_TINV_729 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I201_0_TINV
    );
  PerLBusInterface0_I202_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I202_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_2,
      CTL => PerLBusInterface0_I202_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I202_0_TINV_730 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I202_0_TINV
    );
  PerLBusInterface0_I203_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I203_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_3,
      CTL => PerLBusInterface0_I203_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I203_0_TINV_731 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I203_0_TINV
    );
  PerLBusInterface0_I204_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I204_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_4,
      CTL => PerLBusInterface0_I204_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I204_0_TINV_732 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I204_0_TINV
    );
  PerLBusInterface0_I205_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I205_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_5,
      CTL => PerLBusInterface0_I205_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I205_0_TINV_733 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I205_0_TINV
    );
  PerLBusInterface0_I206_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I206_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_6,
      CTL => PerLBusInterface0_I206_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I206_0_TINV_734 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I206_0_TINV
    );
  PerLBusInterface0_I207_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I207_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_8,
      CTL => PerLBusInterface0_I207_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I207_0_TINV_735 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I207_0_TINV
    );
  PerLBusInterface0_I208_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I208_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_9,
      CTL => PerLBusInterface0_I208_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I208_0_TINV_736 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I208_0_TINV
    );
  PerLBusInterface0_I209_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I209_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_10,
      CTL => PerLBusInterface0_I209_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I209_0_TINV_737 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I209_0_TINV
    );
  PerLBusInterface0_I210_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I210_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_5_11,
      CTL => PerLBusInterface0_I210_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I210_0_TINV_738 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I210_0_TINV
    );
  PerLBusInterface0_I211_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I211_0 : X_TRI
    port map (
      I => PerLBusInterface0_I211_0_IMUXNOT,
      CTL => PerLBusInterface0_I211_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I211_0_TINV_739 : X_INV
    port map (
      I => PerLBusInterface0_I211_N4995,
      O => PerLBusInterface0_I211_0_TINV
    );
  PerLBusInterface0_I211_0_IMUX : X_INV
    port map (
      I => pProbeSense_IBUF,
      O => PerLBusInterface0_I211_0_IMUXNOT
    );
  PerLBusInterface0_I211_N49951 : X_LUT4
    generic map(
      INIT => X"FF5F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_N35455,
      ADR3 => PerLBusInterface0_IntAddr(3),
      O => PerLBusInterface0_I211_N4995_FROM
    );
  PerLBusInterface0_I199_N49951 : X_LUT4
    generic map(
      INIT => X"FFAF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_N35455,
      ADR3 => PerLBusInterface0_IntAddr(3),
      O => PerLBusInterface0_I211_N4995_GROM
    );
  PerLBusInterface0_I211_N4995_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I211_N4995_FROM,
      O => PerLBusInterface0_I211_N4995
    );
  PerLBusInterface0_I211_N4995_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I211_N4995_GROM,
      O => PerLBusInterface0_I199_N4995
    );
  PerLBusInterface0_I212_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I212_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_0,
      CTL => PerLBusInterface0_I212_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I212_0_TINV_740 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I212_0_TINV
    );
  PerLBusInterface0_I213_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I213_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_1,
      CTL => PerLBusInterface0_I213_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I213_0_TINV_741 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I213_0_TINV
    );
  PerLBusInterface0_I214_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I214_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_2,
      CTL => PerLBusInterface0_I214_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I214_0_TINV_742 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I214_0_TINV
    );
  PerLBusInterface0_I215_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I215_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_3,
      CTL => PerLBusInterface0_I215_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I215_0_TINV_743 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I215_0_TINV
    );
  PerLBusInterface0_I216_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I216_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_4,
      CTL => PerLBusInterface0_I216_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I216_0_TINV_744 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I216_0_TINV
    );
  PerLBusInterface0_I217_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I217_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_5,
      CTL => PerLBusInterface0_I217_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I217_0_TINV_745 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I217_0_TINV
    );
  PerLBusInterface0_I218_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I218_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_6,
      CTL => PerLBusInterface0_I218_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I218_0_TINV_746 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I218_0_TINV
    );
  PerLBusInterface0_I219_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I219_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_7,
      CTL => PerLBusInterface0_I219_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I219_0_TINV_747 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I219_0_TINV
    );
  PerLBusInterface0_I220_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I220_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_8,
      CTL => PerLBusInterface0_I220_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I220_0_TINV_748 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I220_0_TINV
    );
  PerLBusInterface0_I221_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I221_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_9,
      CTL => PerLBusInterface0_I221_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I221_0_TINV_749 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I221_0_TINV
    );
  PerLBusInterface0_I222_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I222_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_10,
      CTL => PerLBusInterface0_I222_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I222_0_TINV_750 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I222_0_TINV
    );
  PerLBusInterface0_I223_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I223_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_11,
      CTL => PerLBusInterface0_I223_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I223_0_TINV_751 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I223_0_TINV
    );
  PerLBusInterface0_I224_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I224_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_12,
      CTL => PerLBusInterface0_I224_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I224_0_TINV_752 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I224_0_TINV
    );
  PerLBusInterface0_I225_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I225_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_13,
      CTL => PerLBusInterface0_I225_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I225_0_TINV_753 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I225_0_TINV
    );
  PerLBusInterface0_I226_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I226_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_14,
      CTL => PerLBusInterface0_I226_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I226_0_TINV_754 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I226_0_TINV
    );
  PerLBusInterface0_I227_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I227_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_15,
      CTL => PerLBusInterface0_I227_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I227_0_TINV_755 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I227_0_TINV
    );
  PerLBusInterface0_I228_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I228_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_16,
      CTL => PerLBusInterface0_I228_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I228_0_TINV_756 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I228_0_TINV
    );
  PerLBusInterface0_I229_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I229_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_17,
      CTL => PerLBusInterface0_I229_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I229_0_TINV_757 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I229_0_TINV
    );
  PerLBusInterface0_I230_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I230_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_7_18,
      CTL => PerLBusInterface0_I230_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I230_0_TINV_758 : X_INV
    port map (
      I => PerLBusInterface0_I230_N4995,
      O => PerLBusInterface0_I230_0_TINV
    );
  PerLBusInterface0_I231_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I231_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_8,
      CTL => PerLBusInterface0_I231_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I231_0_TINV_759 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I231_0_TINV
    );
  PerLBusInterface0_I232_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I232_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_9,
      CTL => PerLBusInterface0_I232_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I232_0_TINV_760 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I232_0_TINV
    );
  PerLBusInterface0_I233_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I233_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_10,
      CTL => PerLBusInterface0_I233_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I233_0_TINV_761 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I233_0_TINV
    );
  PerLBusInterface0_I234_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I234_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_11,
      CTL => PerLBusInterface0_I234_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I234_0_TINV_762 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I234_0_TINV
    );
  PerLBusInterface0_I235_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I235_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_12,
      CTL => PerLBusInterface0_I235_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I235_0_TINV_763 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I235_0_TINV
    );
  PerLBusInterface0_I236_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I236_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_13,
      CTL => PerLBusInterface0_I236_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I236_0_TINV_764 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I236_0_TINV
    );
  PerLBusInterface0_I237_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I237_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_14,
      CTL => PerLBusInterface0_I237_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I237_0_TINV_765 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I237_0_TINV
    );
  PerLBusInterface0_I238_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I238_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_15,
      CTL => PerLBusInterface0_I238_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I238_0_TINV_766 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I238_0_TINV
    );
  PerLBusInterface0_I239_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I239_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_16,
      CTL => PerLBusInterface0_I239_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I239_0_TINV_767 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I239_0_TINV
    );
  PerLBusInterface0_I240_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I240_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_17,
      CTL => PerLBusInterface0_I240_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I240_0_TINV_768 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I240_0_TINV
    );
  PerLBusInterface0_I241_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I241_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_18,
      CTL => PerLBusInterface0_I241_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I241_0_TINV_769 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I241_0_TINV
    );
  PerLBusInterface0_I242_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I242_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncCounts_0_19,
      CTL => PerLBusInterface0_I242_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I242_0_TINV_770 : X_INV
    port map (
      I => PerLBusInterface0_I262_N4995,
      O => PerLBusInterface0_I242_0_TINV
    );
  PerLBusInterface0_I331_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I331_0 : X_TRI
    port map (
      I => PerLBusInterface0_GateDataOut_1,
      CTL => PerLBusInterface0_I331_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I331_0_TINV_771 : X_INV
    port map (
      I => PerLBusInterface0_I331_N4995,
      O => PerLBusInterface0_I331_0_TINV
    );
  PerLBusInterface0_I331_N49951 : X_LUT4
    generic map(
      INIT => X"FAFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(3),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(2),
      ADR3 => PerLBusInterface0_N35448,
      O => PerLBusInterface0_I331_N4995_FROM
    );
  PerLBusInterface0_I361_N49951 : X_LUT4
    generic map(
      INIT => X"AFFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(3),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(2),
      ADR3 => PerLBusInterface0_N35448,
      O => PerLBusInterface0_I331_N4995_GROM
    );
  PerLBusInterface0_I331_N4995_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I331_N4995_FROM,
      O => PerLBusInterface0_I331_N4995
    );
  PerLBusInterface0_I331_N4995_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I331_N4995_GROM,
      O => PerLBusInterface0_I361_N4995
    );
  PerLBusInterface0_I332_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I332_0 : X_TRI
    port map (
      I => N50000,
      CTL => PerLBusInterface0_I332_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I332_0_TINV_772 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I332_0_TINV
    );
  PerLBusInterface0_I333_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I333_0 : X_TRI
    port map (
      I => N49884,
      CTL => PerLBusInterface0_I333_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I333_0_TINV_773 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I333_0_TINV
    );
  PerLBusInterface0_I334_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I334_0 : X_TRI
    port map (
      I => N49890,
      CTL => PerLBusInterface0_I334_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I334_0_TINV_774 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I334_0_TINV
    );
  PerLBusInterface0_I335_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I335_0 : X_TRI
    port map (
      I => N49896,
      CTL => PerLBusInterface0_I335_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I335_0_TINV_775 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I335_0_TINV
    );
  PerLBusInterface0_I336_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I336_0 : X_TRI
    port map (
      I => N49902,
      CTL => PerLBusInterface0_I336_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I336_0_TINV_776 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I336_0_TINV
    );
  PerLBusInterface0_I337_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I337_0 : X_TRI
    port map (
      I => N49904,
      CTL => PerLBusInterface0_I337_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I337_0_TINV_777 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I337_0_TINV
    );
  PerLBusInterface0_I338_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I338_0 : X_TRI
    port map (
      I => N49906,
      CTL => PerLBusInterface0_I338_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I338_0_TINV_778 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I338_0_TINV
    );
  PerLBusInterface0_I339_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I339_0 : X_TRI
    port map (
      I => N49908,
      CTL => PerLBusInterface0_I339_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I339_0_TINV_779 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I339_0_TINV
    );
  PerLBusInterface0_I340_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I340_0 : X_TRI
    port map (
      I => N49954,
      CTL => PerLBusInterface0_I340_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I340_0_TINV_780 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I340_0_TINV
    );
  PerLBusInterface0_I341_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I341_0 : X_TRI
    port map (
      I => N49956,
      CTL => PerLBusInterface0_I341_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I341_0_TINV_781 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I341_0_TINV
    );
  PerLBusInterface0_I342_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I342_0 : X_TRI
    port map (
      I => N49958,
      CTL => PerLBusInterface0_I342_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I342_0_TINV_782 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I342_0_TINV
    );
  PerLBusInterface0_I343_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I343_0 : X_TRI
    port map (
      I => N49960,
      CTL => PerLBusInterface0_I343_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I343_0_TINV_783 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I343_0_TINV
    );
  PerLBusInterface0_I344_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I344_0 : X_TRI
    port map (
      I => N49962,
      CTL => PerLBusInterface0_I344_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I344_0_TINV_784 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I344_0_TINV
    );
  PerLBusInterface0_I345_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I345_0 : X_TRI
    port map (
      I => N49966,
      CTL => PerLBusInterface0_I345_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I345_0_TINV_785 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I345_0_TINV
    );
  PerLBusInterface0_I346_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I346_0 : X_TRI
    port map (
      I => N49972,
      CTL => PerLBusInterface0_I346_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I346_0_TINV_786 : X_INV
    port map (
      I => PerLBusInterface0_I361_N4995,
      O => PerLBusInterface0_I346_0_TINV
    );
  PerLBusInterface0_I347_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I347_0 : X_TRI
    port map (
      I => N49978,
      CTL => PerLBusInterface0_I347_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I347_0_TINV_787 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I347_0_TINV
    );
  PerLBusInterface0_I348_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I348_0 : X_TRI
    port map (
      I => N49984,
      CTL => PerLBusInterface0_I348_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I348_0_TINV_788 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I348_0_TINV
    );
  PerLBusInterface0_I349_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I349_0 : X_TRI
    port map (
      I => N49990,
      CTL => PerLBusInterface0_I349_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I349_0_TINV_789 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I349_0_TINV
    );
  PerLBusInterface0_I350_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I350_0 : X_TRI
    port map (
      I => N49968,
      CTL => PerLBusInterface0_I350_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I350_0_TINV_790 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I350_0_TINV
    );
  PerLBusInterface0_I351_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I351_0 : X_TRI
    port map (
      I => N49974,
      CTL => PerLBusInterface0_I351_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I351_0_TINV_791 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I351_0_TINV
    );
  PerLBusInterface0_I352_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I352_0 : X_TRI
    port map (
      I => N49980,
      CTL => PerLBusInterface0_I352_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I352_0_TINV_792 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I352_0_TINV
    );
  PerLBusInterface0_I353_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I353_0 : X_TRI
    port map (
      I => N49986,
      CTL => PerLBusInterface0_I353_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I353_0_TINV_793 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I353_0_TINV
    );
  PerLBusInterface0_I354_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I354_0 : X_TRI
    port map (
      I => N49992,
      CTL => PerLBusInterface0_I354_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I354_0_TINV_794 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I354_0_TINV
    );
  PerLBusInterface0_I355_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I355_0 : X_TRI
    port map (
      I => N49996,
      CTL => PerLBusInterface0_I355_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I355_0_TINV_795 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I355_0_TINV
    );
  PerLBusInterface0_I356_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I356_0 : X_TRI
    port map (
      I => N50004,
      CTL => PerLBusInterface0_I356_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I356_0_TINV_796 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I356_0_TINV
    );
  PerLBusInterface0_I357_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I357_0 : X_TRI
    port map (
      I => N49888,
      CTL => PerLBusInterface0_I357_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I357_0_TINV_797 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I357_0_TINV
    );
  PerLBusInterface0_I358_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I358_0 : X_TRI
    port map (
      I => N49894,
      CTL => PerLBusInterface0_I358_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I358_0_TINV_798 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I358_0_TINV
    );
  PerLBusInterface0_I359_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I359_0 : X_TRI
    port map (
      I => N49900,
      CTL => PerLBusInterface0_I359_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I359_0_TINV_799 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I359_0_TINV
    );
  PerLBusInterface0_I360_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I360_0 : X_TRI
    port map (
      I => N49998,
      CTL => PerLBusInterface0_I360_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I360_0_TINV_800 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I360_0_TINV
    );
  PerLBusInterface0_I361_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I361_0 : X_TRI
    port map (
      I => N50006,
      CTL => PerLBusInterface0_I361_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I361_0_TINV_801 : X_INV
    port map (
      I => PerLBusInterface0_I361_N49951_1,
      O => PerLBusInterface0_I361_0_TINV
    );
  PerLBusInterface0_I361_N49951_1_802 : X_LUT4
    generic map(
      INIT => X"F5FF"
    )
    port map (
      ADR0 => PerLBusInterface0_N35448,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_IntAddr(2),
      O => PerLBusInterface0_I361_N49951_1_FROM
    );
  PerLBusInterface0_I262_N49951_1_803 : X_LUT4
    generic map(
      INIT => X"FBFB"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(3),
      ADR1 => PerLBusInterface0_N35395,
      ADR2 => PerLBusInterface0_IntAddr(2),
      ADR3 => VCC,
      O => PerLBusInterface0_I361_N49951_1_GROM
    );
  PerLBusInterface0_I361_N49951_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I361_N49951_1_FROM,
      O => PerLBusInterface0_I361_N49951_1
    );
  PerLBusInterface0_I361_N49951_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I361_N49951_1_GROM,
      O => PerLBusInterface0_I262_N49951_1
    );
  PerLBusInterface0_I362_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I362_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_2,
      CTL => PerLBusInterface0_I362_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I362_0_TINV_804 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I362_0_TINV
    );
  PerLBusInterface0_I363_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I363_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_3,
      CTL => PerLBusInterface0_I363_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I363_0_TINV_805 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I363_0_TINV
    );
  PerLBusInterface0_I364_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I364_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_4,
      CTL => PerLBusInterface0_I364_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I364_0_TINV_806 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I364_0_TINV
    );
  PerLBusInterface0_I365_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I365_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_5,
      CTL => PerLBusInterface0_I365_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I365_0_TINV_807 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I365_0_TINV
    );
  PerLBusInterface0_I366_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I366_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_6,
      CTL => PerLBusInterface0_I366_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I366_0_TINV_808 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I366_0_TINV
    );
  PerLBusInterface0_I367_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I367_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_7,
      CTL => PerLBusInterface0_I367_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I367_0_TINV_809 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I367_0_TINV
    );
  PerLBusInterface0_I368_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I368_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_8,
      CTL => PerLBusInterface0_I368_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I368_0_TINV_810 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I368_0_TINV
    );
  PerLBusInterface0_I369_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I369_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_9,
      CTL => PerLBusInterface0_I369_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I369_0_TINV_811 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I369_0_TINV
    );
  PerLBusInterface0_I370_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I370_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_10,
      CTL => PerLBusInterface0_I370_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I370_0_TINV_812 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I370_0_TINV
    );
  PerLBusInterface0_I371_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I371_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_11,
      CTL => PerLBusInterface0_I371_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I371_0_TINV_813 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I371_0_TINV
    );
  PerLBusInterface0_I372_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I372_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_12,
      CTL => PerLBusInterface0_I372_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I372_0_TINV_814 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I372_0_TINV
    );
  PerLBusInterface0_I373_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I373_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_13,
      CTL => PerLBusInterface0_I373_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I373_0_TINV_815 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I373_0_TINV
    );
  PerLBusInterface0_I374_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I374_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_14,
      CTL => PerLBusInterface0_I374_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I374_0_TINV_816 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I374_0_TINV
    );
  PerLBusInterface0_I375_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I375_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_15,
      CTL => PerLBusInterface0_I375_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I375_0_TINV_817 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I375_0_TINV
    );
  PerLBusInterface0_I376_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I376_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_16,
      CTL => PerLBusInterface0_I376_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(16)
    );
  PerLBusInterface0_I376_0_TINV_818 : X_INV
    port map (
      I => PerLBusInterface0_I391_N4995,
      O => PerLBusInterface0_I376_0_TINV
    );
  PerLBusInterface0_I377_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I377_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_17,
      CTL => PerLBusInterface0_I377_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(17)
    );
  PerLBusInterface0_I377_0_TINV_819 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I377_0_TINV
    );
  PerLBusInterface0_I378_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I378_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_18,
      CTL => PerLBusInterface0_I378_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(18)
    );
  PerLBusInterface0_I378_0_TINV_820 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I378_0_TINV
    );
  PerLBusInterface0_I379_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I379_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_19,
      CTL => PerLBusInterface0_I379_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(19)
    );
  PerLBusInterface0_I379_0_TINV_821 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I379_0_TINV
    );
  PerLBusInterface0_I380_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I380_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_20,
      CTL => PerLBusInterface0_I380_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(20)
    );
  PerLBusInterface0_I380_0_TINV_822 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I380_0_TINV
    );
  PerLBusInterface0_I381_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I381_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_21,
      CTL => PerLBusInterface0_I381_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(21)
    );
  PerLBusInterface0_I381_0_TINV_823 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I381_0_TINV
    );
  PerLBusInterface0_I382_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I382_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_22,
      CTL => PerLBusInterface0_I382_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(22)
    );
  PerLBusInterface0_I382_0_TINV_824 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I382_0_TINV
    );
  PerLBusInterface0_I383_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I383_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_23,
      CTL => PerLBusInterface0_I383_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(23)
    );
  PerLBusInterface0_I383_0_TINV_825 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I383_0_TINV
    );
  PerLBusInterface0_I384_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I384_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_24,
      CTL => PerLBusInterface0_I384_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(24)
    );
  PerLBusInterface0_I384_0_TINV_826 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I384_0_TINV
    );
  PerLBusInterface0_I385_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I385_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_25,
      CTL => PerLBusInterface0_I385_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(25)
    );
  PerLBusInterface0_I385_0_TINV_827 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I385_0_TINV
    );
  PerLBusInterface0_I386_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I386_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_26,
      CTL => PerLBusInterface0_I386_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(26)
    );
  PerLBusInterface0_I386_0_TINV_828 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I386_0_TINV
    );
  PerLBusInterface0_I387_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I387_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_27,
      CTL => PerLBusInterface0_I387_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(27)
    );
  PerLBusInterface0_I387_0_TINV_829 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I387_0_TINV
    );
  PerLBusInterface0_I388_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I388_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_28,
      CTL => PerLBusInterface0_I388_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(28)
    );
  PerLBusInterface0_I388_0_TINV_830 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I388_0_TINV
    );
  PerLBusInterface0_I389_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I389_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_29,
      CTL => PerLBusInterface0_I389_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(29)
    );
  PerLBusInterface0_I389_0_TINV_831 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I389_0_TINV
    );
  PerLBusInterface0_I390_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I390_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_30,
      CTL => PerLBusInterface0_I390_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(30)
    );
  PerLBusInterface0_I390_0_TINV_832 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I390_0_TINV
    );
  PerLBusInterface0_I391_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I391_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_18_31,
      CTL => PerLBusInterface0_I391_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I391_0_TINV_833 : X_INV
    port map (
      I => PerLBusInterface0_I391_N49951_1,
      O => PerLBusInterface0_I391_0_TINV
    );
  PerLBusInterface0_I391_N49951_1_834 : X_LUT4
    generic map(
      INIT => X"CFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35448,
      O => PerLBusInterface0_I391_N49951_1_FROM
    );
  PerLBusInterface0_I392_EnableTr_INV1 : X_LUT4
    generic map(
      INIT => X"3FFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35448,
      O => PerLBusInterface0_I391_N49951_1_GROM
    );
  PerLBusInterface0_I391_N49951_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_I391_N49951_1_FROM,
      O => PerLBusInterface0_I391_N49951_1
    );
  PerLBusInterface0_I391_N49951_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_I391_N49951_1_GROM,
      O => PerLBusInterface0_I392_N4995
    );
  PerLBusInterface0_I392_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I392_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_19_31_Q,
      CTL => PerLBusInterface0_I392_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(31)
    );
  PerLBusInterface0_I392_0_TINV_835 : X_INV
    port map (
      I => PerLBusInterface0_I392_N4995,
      O => PerLBusInterface0_I392_0_TINV
    );
  PerLBusInterface0_I393_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I393_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I393_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(0)
    );
  PerLBusInterface0_I393_0_TINV_836 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I393_0_TINV
    );
  PerLBusInterface0_I394_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I394_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I394_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(1)
    );
  PerLBusInterface0_I394_0_TINV_837 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I394_0_TINV
    );
  PerLBusInterface0_I395_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I395_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I395_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(2)
    );
  PerLBusInterface0_I395_0_TINV_838 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I395_0_TINV
    );
  PerLBusInterface0_I396_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I396_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I396_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(3)
    );
  PerLBusInterface0_I396_0_TINV_839 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I396_0_TINV
    );
  PerLBusInterface0_I397_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I397_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I397_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(4)
    );
  PerLBusInterface0_I397_0_TINV_840 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I397_0_TINV
    );
  PerLBusInterface0_I398_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I398_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I398_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(5)
    );
  PerLBusInterface0_I398_0_TINV_841 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I398_0_TINV
    );
  PerLBusInterface0_I399_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I399_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I399_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(6)
    );
  PerLBusInterface0_I399_0_TINV_842 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I399_0_TINV
    );
  PerLBusInterface0_I400_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I400_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I400_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(7)
    );
  PerLBusInterface0_I400_0_TINV_843 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I400_0_TINV
    );
  PerLBusInterface0_I401_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I401_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I401_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(8)
    );
  PerLBusInterface0_I401_0_TINV_844 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I401_0_TINV
    );
  PerLBusInterface0_I402_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I402_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I402_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(9)
    );
  PerLBusInterface0_I402_0_TINV_845 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I402_0_TINV
    );
  PerLBusInterface0_I403_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I403_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I403_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(10)
    );
  PerLBusInterface0_I403_0_TINV_846 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I403_0_TINV
    );
  PerLBusInterface0_I404_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I404_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I404_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(11)
    );
  PerLBusInterface0_I404_0_TINV_847 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I404_0_TINV
    );
  PerLBusInterface0_I405_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I405_0 : X_TRI
    port map (
      I => PerLBusInterface0_RegBank_63_12,
      CTL => PerLBusInterface0_I405_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(12)
    );
  PerLBusInterface0_I405_0_TINV_848 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I405_0_TINV
    );
  PerLBusInterface0_I406_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I406_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I406_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(13)
    );
  PerLBusInterface0_I406_0_TINV_849 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I406_0_TINV
    );
  PerLBusInterface0_I407_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I407_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I407_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(14)
    );
  PerLBusInterface0_I407_0_TINV_850 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I407_0_TINV
    );
  PerLBusInterface0_I408_0_PULLUP : X_PU
    port map (
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I408_0 : X_TRI
    port map (
      I => EncoderMonitor0_EncoderReset(3),
      CTL => PerLBusInterface0_I408_0_TINV,
      O => PerLBusInterface0_ReadRegDataMux(15)
    );
  PerLBusInterface0_I408_0_TINV_851 : X_INV
    port map (
      I => PerLBusInterface0_I408_N4995,
      O => PerLBusInterface0_I408_0_TINV
    );
  PerLBusInterface0_I132_N49951 : X_LUT4
    generic map(
      INIT => X"FCFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35462,
      O => PerLBusInterface0_IntAddr_3_GROM
    );
  PerLBusInterface0_IntAddr_3_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_3_GROM,
      O => PerLBusInterface0_I132_N4995
    );
  PerLBusInterface0_IntAddr_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0295_SW0 : X_LUT4
    generic map(
      INIT => X"A000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(5),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(6),
      ADR3 => PerLBusInterface0_IntAddr(7),
      O => PerLBusInterface0_IntAddr_4_FROM
    );
  PerLBusInterface0_I408_N49951 : X_LUT4
    generic map(
      INIT => X"7FFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(4),
      ADR1 => PerLBusInterface0_IntAddr(3),
      ADR2 => PerLBusInterface0_IntAddr(2),
      ADR3 => N45638,
      O => PerLBusInterface0_IntAddr_4_GROM
    );
  PerLBusInterface0_IntAddr_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_4_FROM,
      O => N45638
    );
  PerLBusInterface0_IntAddr_4_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_4_GROM,
      O => PerLBusInterface0_I408_N4995
    );
  PerLBusInterface0_IntAddr_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_4_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0215_Result1 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => pLA_5_IBUF,
      ADR1 => PerLBusInterface0_n0000(3),
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => VCC,
      O => PerLBusInterface0_IntAddr_5_GROM
    );
  PerLBusInterface0_IntAddr_5_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_5_GROM,
      O => PerLBusInterface0_n0215
    );
  PerLBusInterface0_IntAddr_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0214_Result1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => PerLBusInterface0_n0000(4),
      ADR1 => VCC,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => pLA_6_IBUF,
      O => PerLBusInterface0_IntAddr_6_GROM
    );
  PerLBusInterface0_IntAddr_6_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_6_GROM,
      O => PerLBusInterface0_n0214
    );
  PerLBusInterface0_IntAddr_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_6_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0213_Result1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => pnFpgaCs_IBUF,
      ADR1 => VCC,
      ADR2 => pLA_7_IBUF,
      ADR3 => PerLBusInterface0_n0000(5),
      O => PerLBusInterface0_n0213
    );
  PerLBusInterface0_Mmux_n0213_Result1_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => pnFpgaCs_IBUF,
      ADR1 => PerLBusInterface0_n0000(5),
      ADR2 => pLA_7_IBUF,
      ADR3 => VCC,
      O => N50960
    );
  PerLBusInterface0_IntAddr_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0218_Result1 : X_LUT4
    generic map(
      INIT => X"F303"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => pLA_2_IBUF,
      O => PerLBusInterface0_IntAddr_2_2_GROM
    );
  PerLBusInterface0_IntAddr_2_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_2_2_GROM,
      O => PerLBusInterface0_n0218
    );
  PerLBusInterface0_IntAddr_2_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_2_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_4811 : X_MUX2
    port map (
      IA => N51022,
      IB => N51024,
      SEL => PerLBusInterface0_IntAddr_5_1,
      O => PerLBusInterface0_IntAddr_2_3_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_4811_G : X_LUT4
    generic map(
      INIT => X"0013"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_3,
      ADR1 => PerLBusInterface0_IntAddr_6_1,
      ADR2 => PerLBusInterface0_IntAddr_2_3,
      ADR3 => PerLBusInterface0_IntAddr_4_1,
      O => N51024
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_4811_F : X_LUT4
    generic map(
      INIT => X"0F28"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_1,
      ADR1 => PerLBusInterface0_IntAddr_3_1,
      ADR2 => PerLBusInterface0_IntAddr_4_1,
      ADR3 => PerLBusInterface0_IntAddr_6_1,
      O => N51022
    );
  PerLBusInterface0_IntAddr_2_3_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_2_3_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net133
    );
  PerLBusInterface0_IntAddr_2_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_2_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0217_Result1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => pLA_3_IBUF,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_n0000(1),
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_IntAddr_3_2_GROM
    );
  PerLBusInterface0_IntAddr_3_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_3_2_GROM,
      O => PerLBusInterface0_n0217
    );
  PerLBusInterface0_IntAddr_3_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_3_2_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_BeginShift_852 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_BeginShift_FFY_RST,
      O => EncoderMonitor0_BeginShift
    );
  EncoderMonitor0_BeginShift_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_BeginShift_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_BeginShift_FFY_RST
    );
  PerLBusInterface0_n0295_853 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_2_3,
      ADR2 => N45638,
      ADR3 => PerLBusInterface0_IntAddr_3_3,
      O => PerLBusInterface0_IntAddr_3_3_FROM
    );
  PerLBusInterface0_n03161 : X_LUT4
    generic map(
      INIT => X"2200"
    )
    port map (
      ADR0 => PerLBusInterface0_LWnR,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0295,
      O => PerLBusInterface0_n0316
    );
  PerLBusInterface0_IntAddr_3_3_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_3_3_FROM,
      O => PerLBusInterface0_n0295
    );
  PerLBusInterface0_IntAddr_3_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_3_3_SRMUX_OUTPUTNOT
    );
  Encoder2In_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD5,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder2In_1_FFX_RST,
      O => Encoder2In(1)
    );
  Encoder2In_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Encoder2In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder2In_1_FFX_RST
    );
  PerLBusInterface0_Mmux_n0216_Result1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => pnFpgaCs_IBUF,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_n0000(2),
      ADR3 => pLA_4_IBUF,
      O => PerLBusInterface0_IntAddr_4_2_GROM
    );
  PerLBusInterface0_IntAddr_4_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_IntAddr_4_2_GROM,
      O => PerLBusInterface0_n0216
    );
  PerLBusInterface0_IntAddr_4_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_4_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0215_Result1_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => pLA_5_IBUF,
      ADR1 => PerLBusInterface0_n0000(3),
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => N50978
    );
  PerLBusInterface0_IntAddr_5_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_5_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0214_Result1_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => pnFpgaCs_IBUF,
      ADR1 => pLA_6_IBUF,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_n0000(4),
      O => N51000
    );
  PerLBusInterface0_IntAddr_6_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_IntAddr_6_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3711 : X_MUX2
    port map (
      IA => N51027,
      IB => N51029,
      SEL => PerLBusInterface0_IntAddr_5_1,
      O => PerLBusInterface0_Mrom_n0180_net100_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3711_G : X_LUT4
    generic map(
      INIT => X"0015"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_6_1,
      ADR1 => PerLBusInterface0_IntAddr_2_1,
      ADR2 => PerLBusInterface0_IntAddr_3_1,
      ADR3 => PerLBusInterface0_IntAddr_4_1,
      O => N51029
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3711_F : X_LUT4
    generic map(
      INIT => X"0149"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_1,
      ADR1 => PerLBusInterface0_IntAddr_6_1,
      ADR2 => PerLBusInterface0_IntAddr_3_1,
      ADR3 => PerLBusInterface0_IntAddr_4_1,
      O => N51027
    );
  PerLBusInterface0_Mrom_n0180_net100_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net100_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net100
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3811 : X_MUX2
    port map (
      IA => N51047,
      IB => N51049,
      SEL => PerLBusInterface0_IntAddr_5_1,
      O => PerLBusInterface0_Mrom_n0180_net103_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3811_G : X_LUT4
    generic map(
      INIT => X"0007"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_1,
      ADR1 => PerLBusInterface0_IntAddr_2_1,
      ADR2 => PerLBusInterface0_IntAddr_6_1,
      ADR3 => PerLBusInterface0_IntAddr_4_1,
      O => N51049
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3811_F : X_LUT4
    generic map(
      INIT => X"1043"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_1,
      ADR1 => PerLBusInterface0_IntAddr_3_1,
      ADR2 => PerLBusInterface0_IntAddr_6_1,
      ADR3 => PerLBusInterface0_IntAddr_2_1,
      O => N51047
    );
  PerLBusInterface0_Mrom_n0180_net103_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net103_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net103
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_1 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_45,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_46,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net40_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_461 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_46
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_451 : X_LUT4
    generic map(
      INIT => X"07B3"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_45
    );
  PerLBusInterface0_Mrom_n0180_net40_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net40_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net40
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_48,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_49,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net43_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_491 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_49
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_481 : X_LUT4
    generic map(
      INIT => X"1B53"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_48
    );
  PerLBusInterface0_Mrom_n0180_net43_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net43_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net43
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_5 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_51,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_52,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net46_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_521 : X_LUT4
    generic map(
      INIT => X"0007"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_52
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_511 : X_LUT4
    generic map(
      INIT => X"138F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_51
    );
  PerLBusInterface0_Mrom_n0180_net46_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net46_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net46
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_7 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_54,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_55,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net49_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_551 : X_LUT4
    generic map(
      INIT => X"0015"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_55
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_541 : X_LUT4
    generic map(
      INIT => X"07B3"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_54
    );
  PerLBusInterface0_Mrom_n0180_net49_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net49_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net49
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_9 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_57,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_58,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net52_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_581 : X_LUT4
    generic map(
      INIT => X"0006"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_58
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_571 : X_LUT4
    generic map(
      INIT => X"315D"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_57
    );
  PerLBusInterface0_Mrom_n0180_net52_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net52_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net52
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_11 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_60,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_61,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net55_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_611 : X_LUT4
    generic map(
      INIT => X"0014"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_61
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_601 : X_LUT4
    generic map(
      INIT => X"531B"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_60
    );
  PerLBusInterface0_Mrom_n0180_net55_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net55_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net55
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_13 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_63,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_64,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net58_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_641 : X_LUT4
    generic map(
      INIT => X"0006"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_64
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_631 : X_LUT4
    generic map(
      INIT => X"0D75"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_63
    );
  PerLBusInterface0_Mrom_n0180_net58_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net58_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net58
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_15 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_66,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_67,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net61_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_671 : X_LUT4
    generic map(
      INIT => X"0006"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_67
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_661 : X_LUT4
    generic map(
      INIT => X"0793"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_66
    );
  PerLBusInterface0_Mrom_n0180_net61_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net61_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net61
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_17 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_69,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_70,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net64_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_701 : X_LUT4
    generic map(
      INIT => X"0006"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_70
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_691 : X_LUT4
    generic map(
      INIT => X"234F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_69
    );
  PerLBusInterface0_Mrom_n0180_net64_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net64_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net64
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_19 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_72,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_73,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net67_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_731 : X_LUT4
    generic map(
      INIT => X"0012"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_73
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_721 : X_LUT4
    generic map(
      INIT => X"07D5"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_72
    );
  PerLBusInterface0_Mrom_n0180_net67_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net67_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net67
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_21 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_75,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_76,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net70_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_761 : X_LUT4
    generic map(
      INIT => X"0012"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_76
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_751 : X_LUT4
    generic map(
      INIT => X"13D5"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_75
    );
  PerLBusInterface0_Mrom_n0180_net70_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net70_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net70
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_23 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_78,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_79,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net73_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_791 : X_LUT4
    generic map(
      INIT => X"0012"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_79
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_781 : X_LUT4
    generic map(
      INIT => X"185F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_78
    );
  PerLBusInterface0_Mrom_n0180_net73_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net73_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net73
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_25 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_81,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_82,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net76_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_821 : X_LUT4
    generic map(
      INIT => X"0110"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_82
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_811 : X_LUT4
    generic map(
      INIT => X"4237"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_81
    );
  PerLBusInterface0_Mrom_n0180_net76_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net76_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net76
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_27 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_84,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_85,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net79_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_851 : X_LUT4
    generic map(
      INIT => X"0006"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_85
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_841 : X_LUT4
    generic map(
      INIT => X"214F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_84
    );
  PerLBusInterface0_Mrom_n0180_net79_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net79_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net79
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_29 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_87,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_88,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net82_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_881 : X_LUT4
    generic map(
      INIT => X"0102"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_88
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_871 : X_LUT4
    generic map(
      INIT => X"0973"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_87
    );
  PerLBusInterface0_Mrom_n0180_net82_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net82_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net82
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_31 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_inst_lut4_90,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_91,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net85_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_911 : X_LUT4
    generic map(
      INIT => X"0014"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_91
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_901 : X_LUT4
    generic map(
      INIT => X"1587"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_90
    );
  PerLBusInterface0_Mrom_n0180_net85_F5USED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net85_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net85
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_33111 : X_MUX2
    port map (
      IA => N51017,
      IB => N51019,
      SEL => PerLBusInterface0_IntAddr_6_1,
      O => PerLBusInterface0_Mrom_n0180_net88_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_33111_G : X_LUT4
    generic map(
      INIT => X"0102"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_1,
      ADR1 => PerLBusInterface0_IntAddr_5_1,
      ADR2 => PerLBusInterface0_IntAddr_4_1,
      ADR3 => PerLBusInterface0_IntAddr_3_1,
      O => N51019
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_33111_F : X_LUT4
    generic map(
      INIT => X"2456"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_1,
      ADR1 => PerLBusInterface0_IntAddr_5_1,
      ADR2 => PerLBusInterface0_IntAddr_2_1,
      ADR3 => PerLBusInterface0_IntAddr_3_1,
      O => N51017
    );
  PerLBusInterface0_Mrom_n0180_net88_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net88_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net88
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_34111 : X_MUX2
    port map (
      IA => N51032,
      IB => N51034,
      SEL => PerLBusInterface0_IntAddr_6_1,
      O => PerLBusInterface0_Mrom_n0180_net91_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_34111_G : X_LUT4
    generic map(
      INIT => X"0104"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_1,
      ADR1 => PerLBusInterface0_IntAddr_3_1,
      ADR2 => PerLBusInterface0_IntAddr_5_1,
      ADR3 => PerLBusInterface0_IntAddr_2_1,
      O => N51034
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_34111_F : X_LUT4
    generic map(
      INIT => X"2444"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_1,
      ADR1 => PerLBusInterface0_IntAddr_5_1,
      ADR2 => PerLBusInterface0_IntAddr_2_1,
      ADR3 => PerLBusInterface0_IntAddr_3_1,
      O => N51032
    );
  PerLBusInterface0_Mrom_n0180_net91_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net91_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net91
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3511 : X_MUX2
    port map (
      IA => N51037,
      IB => N51039,
      SEL => PerLBusInterface0_IntAddr_5_1,
      O => PerLBusInterface0_Mrom_n0180_net94_F5MUX
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3511_G : X_LUT4
    generic map(
      INIT => X"0103"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_1,
      ADR1 => PerLBusInterface0_IntAddr_4_1,
      ADR2 => PerLBusInterface0_IntAddr_6_1,
      ADR3 => PerLBusInterface0_IntAddr_2_1,
      O => N51039
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_3511_F : X_LUT4
    generic map(
      INIT => X"1281"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_1,
      ADR1 => PerLBusInterface0_IntAddr_4_1,
      ADR2 => PerLBusInterface0_IntAddr_2_1,
      ADR3 => PerLBusInterface0_IntAddr_6_1,
      O => N51037
    );
  PerLBusInterface0_Mrom_n0180_net94_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_Mrom_n0180_net94_F5MUX,
      O => PerLBusInterface0_Mrom_n0180_net94
    );
  PerLBusInterface0_Ker353931 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(4),
      ADR1 => PerLBusInterface0_IntAddr(6),
      ADR2 => PerLBusInterface0_IntAddr(5),
      ADR3 => PerLBusInterface0_IntAddr(7),
      O => PerLBusInterface0_N35395_FROM
    );
  PerLBusInterface0_I262_N49951 : X_LUT4
    generic map(
      INIT => X"EEFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(2),
      ADR1 => PerLBusInterface0_IntAddr(3),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_N35395,
      O => PerLBusInterface0_N35395_GROM
    );
  PerLBusInterface0_N35395_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35395_FROM,
      O => PerLBusInterface0_N35395
    );
  PerLBusInterface0_N35395_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35395_GROM,
      O => PerLBusInterface0_I262_N4995
    );
  PerLBusInterface0_Ker354091 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_FocusCount_54,
      ADR2 => PerLBusInterface0_FocusCount_55,
      ADR3 => PerLBusInterface0_FocusCount_56,
      O => PerLBusInterface0_N35411_FROM
    );
  PerLBusInterface0_n05021 : X_LUT4
    generic map(
      INIT => X"FAFF"
    )
    port map (
      ADR0 => PerLBusInterface0_DoFocus,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_FocusCount_53,
      ADR3 => PerLBusInterface0_N35411,
      O => PerLBusInterface0_N35411_GROM
    );
  PerLBusInterface0_N35411_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35411_FROM,
      O => PerLBusInterface0_N35411
    );
  PerLBusInterface0_N35411_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35411_GROM,
      O => PerLBusInterface0_n0502
    );
  PerLBusInterface0_Ker354221 : X_LUT4
    generic map(
      INIT => X"000F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_3_1,
      ADR3 => PerLBusInterface0_IntAddr_2_1,
      O => PerLBusInterface0_N35424_GROM
    );
  PerLBusInterface0_N35424_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35424_GROM,
      O => PerLBusInterface0_N35424
    );
  PerLBusInterface0_Ker354461 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(7),
      ADR1 => PerLBusInterface0_IntAddr(5),
      ADR2 => PerLBusInterface0_IntAddr(4),
      ADR3 => PerLBusInterface0_IntAddr(6),
      O => PerLBusInterface0_N35448_FROM
    );
  PerLBusInterface0_I391_N49951 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_N35448,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_IntAddr(2),
      O => PerLBusInterface0_N35448_GROM
    );
  PerLBusInterface0_N35448_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35448_FROM,
      O => PerLBusInterface0_N35448
    );
  PerLBusInterface0_N35448_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35448_GROM,
      O => PerLBusInterface0_I391_N4995
    );
  PerLBusInterface0_Ker354531 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(7),
      ADR1 => PerLBusInterface0_IntAddr(5),
      ADR2 => PerLBusInterface0_IntAddr(6),
      ADR3 => PerLBusInterface0_IntAddr(4),
      O => PerLBusInterface0_N35455_FROM
    );
  PerLBusInterface0_I230_N49951 : X_LUT4
    generic map(
      INIT => X"3FFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(3),
      ADR2 => PerLBusInterface0_IntAddr(2),
      ADR3 => PerLBusInterface0_N35455,
      O => PerLBusInterface0_N35455_GROM
    );
  PerLBusInterface0_N35455_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35455_FROM,
      O => PerLBusInterface0_N35455
    );
  PerLBusInterface0_N35455_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35455_GROM,
      O => PerLBusInterface0_I230_N4995
    );
  PerLBusInterface0_Ker354601 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr(7),
      ADR1 => PerLBusInterface0_IntAddr(5),
      ADR2 => PerLBusInterface0_IntAddr(4),
      ADR3 => PerLBusInterface0_IntAddr(6),
      O => PerLBusInterface0_N35462_FROM
    );
  PerLBusInterface0_I156_N49951 : X_LUT4
    generic map(
      INIT => X"F3FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => PerLBusInterface0_N35462,
      O => PerLBusInterface0_N35462_GROM
    );
  PerLBusInterface0_N35462_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35462_FROM,
      O => PerLBusInterface0_N35462
    );
  PerLBusInterface0_N35462_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_N35462_GROM,
      O => PerLBusInterface0_I156_N4995
    );
  PerLBusInterface0_pLDout_10_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegMask(10),
      ADR2 => PerLBusInterface0_ReadRegData(10),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_11_GROM
    );
  PerLBusInterface0_ReadRegData_11_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_11_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_12_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(12),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_ReadRegData(12),
      O => PerLBusInterface0_ReadRegData_13_GROM
    );
  PerLBusInterface0_ReadRegData_13_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_13_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_14_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(14),
      ADR3 => PerLBusInterface0_ReadRegMask(14),
      O => PerLBusInterface0_ReadRegData_15_GROM
    );
  PerLBusInterface0_ReadRegData_15_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_15_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_16_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(16),
      ADR3 => PerLBusInterface0_ReadRegMask(16),
      O => PerLBusInterface0_ReadRegData_17_GROM
    );
  PerLBusInterface0_ReadRegData_17_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_17_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_18_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegMask(18),
      ADR2 => PerLBusInterface0_ReadRegData(18),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_19_GROM
    );
  PerLBusInterface0_ReadRegData_19_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_19_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_0_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(0),
      ADR3 => PerLBusInterface0_ReadRegData(0),
      O => PerLBusInterface0_ReadRegData_1_GROM
    );
  PerLBusInterface0_ReadRegData_1_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_1_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_20_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(20),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_ReadRegData(20),
      O => PerLBusInterface0_ReadRegData_21_GROM
    );
  PerLBusInterface0_ReadRegData_21_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_21_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_22_1 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegMask(22),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_ReadRegData(22),
      O => PerLBusInterface0_ReadRegData_23_GROM
    );
  PerLBusInterface0_ReadRegData_23_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_23_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_23_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_24_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(24),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(24),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_25_GROM
    );
  PerLBusInterface0_ReadRegData_25_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_25_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_26_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(26),
      ADR3 => PerLBusInterface0_ReadRegData(26),
      O => PerLBusInterface0_ReadRegData_27_GROM
    );
  PerLBusInterface0_ReadRegData_27_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_27_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_28_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_ReadRegMask(28),
      ADR2 => PerLBusInterface0_ReadRegData(28),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_29_GROM
    );
  PerLBusInterface0_ReadRegData_29_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_29_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_30_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegData(30),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(30),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_31_GROM
    );
  PerLBusInterface0_ReadRegData_31_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_31_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_2_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegMask(2),
      ADR3 => PerLBusInterface0_ReadRegData(2),
      O => PerLBusInterface0_ReadRegData_3_GROM
    );
  PerLBusInterface0_ReadRegData_3_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_3_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_ReadRegData_5_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_5_FROM
    );
  PerLBusInterface0_pLDout_4_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(4),
      ADR1 => PerLBusInterface0_ReadRegData(4),
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_5_GROM
    );
  PerLBusInterface0_ReadRegData_5_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_5_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_5_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_5_FROM,
      O => PerLBusInterface0_ReadRegData_5_X
    );
  PerLBusInterface0_ReadRegData_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_6_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(6),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(6),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_7_GROM
    );
  PerLBusInterface0_ReadRegData_7_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_7_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_pLDout_8_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_ReadRegMask(8),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_ReadRegData(8),
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegData_9_GROM
    );
  PerLBusInterface0_ReadRegData_9_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegData_9_CEMUXNOT
    );
  PerLBusInterface0_ReadRegData_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegData_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_2 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_0_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_47,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net41
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_471 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_47
    );
  PerLBusInterface0_ReadRegMask_0_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_0_GROM
    );
  PerLBusInterface0_ReadRegMask_0_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_0_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_0_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_1 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net40,
      IB => PerLBusInterface0_Mrom_n0180_net41,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(0)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_22 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_10_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_77,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net71
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_771 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_77
    );
  PerLBusInterface0_ReadRegMask_10_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_10_GROM
    );
  PerLBusInterface0_ReadRegMask_10_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_10_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_10_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_11 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net70,
      IB => PerLBusInterface0_Mrom_n0180_net71,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(10)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_24 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_11_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_80,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net74
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_801 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_80
    );
  PerLBusInterface0_ReadRegMask_11_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_11_GROM
    );
  PerLBusInterface0_ReadRegMask_11_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_11_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_12 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net73,
      IB => PerLBusInterface0_Mrom_n0180_net74,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(11)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_26 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_12_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_83,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net77
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_831 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_83
    );
  PerLBusInterface0_ReadRegMask_12_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_12_GROM
    );
  PerLBusInterface0_ReadRegMask_12_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_12_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_12_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_13 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net76,
      IB => PerLBusInterface0_Mrom_n0180_net77,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(12)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_28 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_13_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_86,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net80
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_861 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_86
    );
  PerLBusInterface0_ReadRegMask_13_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_13_GROM
    );
  PerLBusInterface0_ReadRegMask_13_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_13_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_14 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net79,
      IB => PerLBusInterface0_Mrom_n0180_net80,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(13)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_30 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_14_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_89,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net83
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_891 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_89
    );
  PerLBusInterface0_ReadRegMask_14_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_14_GROM
    );
  PerLBusInterface0_ReadRegMask_14_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_14_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_14_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_15 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net82,
      IB => PerLBusInterface0_Mrom_n0180_net83,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(14)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_32 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_15_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_92,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net86
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_921 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_92
    );
  PerLBusInterface0_ReadRegMask_15_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_15_GROM
    );
  PerLBusInterface0_ReadRegMask_15_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_15_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_16 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net85,
      IB => PerLBusInterface0_Mrom_n0180_net86,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(15)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_181 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_7_1,
      ADR2 => PerLBusInterface0_Mrom_n0180_net91,
      ADR3 => VCC,
      O => PerLBusInterface0_n0180(17)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_171 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_7_1,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_Mrom_n0180_net88,
      O => PerLBusInterface0_n0180(16)
    );
  PerLBusInterface0_ReadRegMask_17_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_17_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_191 : X_LUT4
    generic map(
      INIT => X"3300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_7_1,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_Mrom_n0180_net94,
      O => PerLBusInterface0_n0180(18)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_321 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_Mrom_n0180_net133,
      ADR3 => VCC,
      O => PerLBusInterface0_n0180(31)
    );
  PerLBusInterface0_ReadRegMask_18_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_18_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_18_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_20_SW0 : X_LUT4
    generic map(
      INIT => X"ECB6"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_3,
      ADR1 => PerLBusInterface0_IntAddr_6_2,
      ADR2 => PerLBusInterface0_IntAddr_2_3,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_ReadRegMask_19_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_20 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => VCC,
      ADR3 => N50108,
      O => PerLBusInterface0_n0180(19)
    );
  PerLBusInterface0_ReadRegMask_19_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_19_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_19_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_19_FROM,
      O => N50108
    );
  PerLBusInterface0_ReadRegMask_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_4 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_1_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_50,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net44
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_501 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_50
    );
  PerLBusInterface0_ReadRegMask_1_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_1_GROM
    );
  PerLBusInterface0_ReadRegMask_1_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_1_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_2 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net43,
      IB => PerLBusInterface0_Mrom_n0180_net44,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(1)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_221 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => PerLBusInterface0_Mrom_n0180_net103,
      O => PerLBusInterface0_n0180(21)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_211 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => PerLBusInterface0_Mrom_n0180_net100,
      O => PerLBusInterface0_n0180(20)
    );
  PerLBusInterface0_ReadRegMask_21_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_21_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_23_SW0 : X_LUT4
    generic map(
      INIT => X"EDB2"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_3,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_3,
      ADR3 => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_ReadRegMask_22_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_23 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => N50122,
      O => PerLBusInterface0_n0180(22)
    );
  PerLBusInterface0_ReadRegMask_22_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_22_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_22_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_22_FROM,
      O => N50122
    );
  PerLBusInterface0_ReadRegMask_22_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_22_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_24_SW0 : X_LUT4
    generic map(
      INIT => X"F99A"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_6_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_3,
      ADR3 => PerLBusInterface0_IntAddr_3_3,
      O => PerLBusInterface0_ReadRegMask_23_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_24 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => N50132,
      O => PerLBusInterface0_n0180(23)
    );
  PerLBusInterface0_ReadRegMask_23_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_23_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_23_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_23_FROM,
      O => N50132
    );
  PerLBusInterface0_ReadRegMask_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_23_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_25_SW0 : X_LUT4
    generic map(
      INIT => X"F89E"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_3,
      ADR1 => PerLBusInterface0_IntAddr_2_3,
      ADR2 => PerLBusInterface0_IntAddr_6_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_ReadRegMask_24_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_25 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => N50104,
      O => PerLBusInterface0_n0180(24)
    );
  PerLBusInterface0_ReadRegMask_24_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_24_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_24_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_24_FROM,
      O => N50104
    );
  PerLBusInterface0_ReadRegMask_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_24_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_26_SW0 : X_LUT4
    generic map(
      INIT => X"F98F"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_3,
      ADR1 => PerLBusInterface0_IntAddr_2_3,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_ReadRegMask_25_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_26 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => N50126,
      O => PerLBusInterface0_n0180(25)
    );
  PerLBusInterface0_ReadRegMask_25_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_25_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_25_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_25_FROM,
      O => N50126
    );
  PerLBusInterface0_ReadRegMask_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_27_SW0 : X_LUT4
    generic map(
      INIT => X"ECB7"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_3,
      ADR1 => PerLBusInterface0_IntAddr_6_2,
      ADR2 => PerLBusInterface0_IntAddr_3_3,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_ReadRegMask_26_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_27 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => VCC,
      ADR3 => N50112,
      O => PerLBusInterface0_n0180(26)
    );
  PerLBusInterface0_ReadRegMask_26_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_26_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_26_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_26_FROM,
      O => N50112
    );
  PerLBusInterface0_ReadRegMask_26_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_26_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_28_SW0 : X_LUT4
    generic map(
      INIT => X"F99D"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_6_2,
      ADR2 => PerLBusInterface0_IntAddr_3_3,
      ADR3 => PerLBusInterface0_IntAddr_2_3,
      O => PerLBusInterface0_ReadRegMask_27_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_28 : X_LUT4
    generic map(
      INIT => X"0005"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_2,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => N50100,
      O => PerLBusInterface0_n0180(27)
    );
  PerLBusInterface0_ReadRegMask_27_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_27_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_27_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_27_FROM,
      O => N50100
    );
  PerLBusInterface0_ReadRegMask_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_29_SW0 : X_LUT4
    generic map(
      INIT => X"F99D"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_6_2,
      ADR2 => PerLBusInterface0_IntAddr_3_3,
      ADR3 => PerLBusInterface0_IntAddr_2_3,
      O => PerLBusInterface0_ReadRegMask_28_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_29 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_7_1,
      ADR2 => N50092,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_n0180(28)
    );
  PerLBusInterface0_ReadRegMask_28_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_28_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_28_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_28_FROM,
      O => N50092
    );
  PerLBusInterface0_ReadRegMask_28_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_28_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_30_SW0 : X_LUT4
    generic map(
      INIT => X"EDB5"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_3_3,
      ADR2 => PerLBusInterface0_IntAddr_6_2,
      ADR3 => PerLBusInterface0_IntAddr_2_3,
      O => PerLBusInterface0_ReadRegMask_29_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_30 : X_LUT4
    generic map(
      INIT => X"0003"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_IntAddr_7_1,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => N50116,
      O => PerLBusInterface0_n0180(29)
    );
  PerLBusInterface0_ReadRegMask_29_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_29_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_29_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_29_FROM,
      O => N50116
    );
  PerLBusInterface0_ReadRegMask_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_6 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_2_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_53,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net47
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_531 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_53
    );
  PerLBusInterface0_ReadRegMask_2_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_2_GROM
    );
  PerLBusInterface0_ReadRegMask_2_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_2_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_3 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net46,
      IB => PerLBusInterface0_Mrom_n0180_net47,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(2)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_31_SW0 : X_LUT4
    generic map(
      INIT => X"EAD7"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_6_2,
      ADR1 => PerLBusInterface0_IntAddr_3_3,
      ADR2 => PerLBusInterface0_IntAddr_2_3,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_ReadRegMask_30_FROM
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_31 : X_LUT4
    generic map(
      INIT => X"0011"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => VCC,
      ADR3 => N50084,
      O => PerLBusInterface0_n0180(30)
    );
  PerLBusInterface0_ReadRegMask_30_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_30_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_30_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegMask_30_FROM,
      O => N50084
    );
  PerLBusInterface0_ReadRegMask_30_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_30_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_8 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_3_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_56,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net50
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_561 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_56
    );
  PerLBusInterface0_ReadRegMask_3_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_3_GROM
    );
  PerLBusInterface0_ReadRegMask_3_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_3_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_4 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net49,
      IB => PerLBusInterface0_Mrom_n0180_net50,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(3)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_10 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_4_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_59,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net53
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_591 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_5_2,
      ADR3 => PerLBusInterface0_IntAddr_4_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_59
    );
  PerLBusInterface0_ReadRegMask_4_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_4_GROM
    );
  PerLBusInterface0_ReadRegMask_4_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_4_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_4_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_5 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net52,
      IB => PerLBusInterface0_Mrom_n0180_net53,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(4)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_12 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_5_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_62,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net56
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_621 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_62
    );
  PerLBusInterface0_ReadRegMask_5_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_5_GROM
    );
  PerLBusInterface0_ReadRegMask_5_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_5_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_6 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net55,
      IB => PerLBusInterface0_Mrom_n0180_net56,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(5)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_14 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_6_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_65,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net59
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_651 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_65
    );
  PerLBusInterface0_ReadRegMask_6_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_6_GROM
    );
  PerLBusInterface0_ReadRegMask_6_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_6_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_6_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_7 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net58,
      IB => PerLBusInterface0_Mrom_n0180_net59,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(6)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_16 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_7_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_68,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net62
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_681 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_5_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_68
    );
  PerLBusInterface0_ReadRegMask_7_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_7_GROM
    );
  PerLBusInterface0_ReadRegMask_7_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_7_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_8 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net61,
      IB => PerLBusInterface0_Mrom_n0180_net62,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(7)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_18 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_8_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_71,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net65
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_711 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_71
    );
  PerLBusInterface0_ReadRegMask_8_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_8_GROM
    );
  PerLBusInterface0_ReadRegMask_8_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_8_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_8_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_9 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net64,
      IB => PerLBusInterface0_Mrom_n0180_net65,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(8)
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f5_20 : X_MUX2
    port map (
      IA => PerLBusInterface0_ReadRegMask_9_GROM,
      IB => PerLBusInterface0_Mrom_n0180_inst_lut4_74,
      SEL => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_Mrom_n0180_net68
    );
  PerLBusInterface0_Mrom_n0180_inst_lut4_741 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_2_2,
      O => PerLBusInterface0_Mrom_n0180_inst_lut4_74
    );
  PerLBusInterface0_ReadRegMask_9_G : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_ReadRegMask_9_GROM
    );
  PerLBusInterface0_ReadRegMask_9_CEMUX : X_INV
    port map (
      I => pnFpgaCs_IBUF,
      O => PerLBusInterface0_ReadRegMask_9_CEMUXNOT
    );
  PerLBusInterface0_ReadRegMask_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_ReadRegMask_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mrom_n0180_inst_mux_f6_10 : X_MUX2
    port map (
      IA => PerLBusInterface0_Mrom_n0180_net67,
      IB => PerLBusInterface0_Mrom_n0180_net68,
      SEL => PerLBusInterface0_IntAddr_7_1,
      O => PerLBusInterface0_n0180(9)
    );
  PerLBusInterface0_RegBank_19_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_10_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_19_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_19_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_19_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_4_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_19_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_6_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_19_8_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_19_8_FROM
    );
  PerLBusInterface0_RegBank_19_8_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_19_8_GROM
    );
  PerLBusInterface0_RegBank_19_8_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_19_8_FROM,
      O => PerLBusInterface0_RegBank_19_8_X
    );
  PerLBusInterface0_RegBank_19_8_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_19_8_GROM,
      O => PerLBusInterface0_RegBank_19_8_Y
    );
  PerLBusInterface0_RegBank_19_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_19_8_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_13_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_0_13_FROM
    );
  PerLBusInterface0_RegBank_0_13_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_13_FROM,
      O => PerLBusInterface0_RegBank_0_13_X
    );
  PerLBusInterface0_RegBank_0_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_23_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_24_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_0_9_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_0_9_FROM
    );
  PerLBusInterface0_RegBank_0_9_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_9_FROM,
      O => PerLBusInterface0_RegBank_0_9_X
    );
  PerLBusInterface0_RegBank_0_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_0_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_1_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_0,
      ADR1 => N49970,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(1)
    );
  PerLBusInterface0_Mmux_n0250_Result_0_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49964,
      ADR1 => PerLBusInterface0_RegBank_15_31,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(0)
    );
  PerLBusInterface0_RegBank_14_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_11_1 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => N49912,
      ADR1 => PerLBusInterface0_RegBank_14_10,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(11)
    );
  PerLBusInterface0_Mmux_n0250_Result_10_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_14_9,
      ADR2 => N49910,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(10)
    );
  PerLBusInterface0_RegBank_14_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_13_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49916,
      ADR2 => PerLBusInterface0_RegBank_14_12,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(13)
    );
  PerLBusInterface0_Mmux_n0250_Result_12_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N49914,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_14_11,
      O => PerLBusInterface0_n0250(12)
    );
  PerLBusInterface0_RegBank_14_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_15_1 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_14,
      ADR1 => N49920,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(15)
    );
  PerLBusInterface0_Mmux_n0250_Result_14_1 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_13,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => VCC,
      ADR3 => N49918,
      O => PerLBusInterface0_n0250(14)
    );
  PerLBusInterface0_RegBank_14_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_17_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_16,
      ADR1 => N49928,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(17)
    );
  PerLBusInterface0_Mmux_n0250_Result_16_1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_15,
      ADR1 => VCC,
      ADR2 => N49924,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(16)
    );
  PerLBusInterface0_RegBank_14_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_19_1 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => N49936,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => PerLBusInterface0_RegBank_14_18,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(19)
    );
  PerLBusInterface0_Mmux_n0250_Result_18_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_17,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49932,
      O => PerLBusInterface0_n0250(18)
    );
  PerLBusInterface0_RegBank_14_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_2_1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_1,
      ADR1 => VCC,
      ADR2 => N49976,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(2)
    );
  PerLBusInterface0_Mmux_n0250_Result_22_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_21,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49930,
      O => PerLBusInterface0_n0250(22)
    );
  PerLBusInterface0_RegBank_14_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_21_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49926,
      ADR1 => PerLBusInterface0_RegBank_14_20,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(21)
    );
  PerLBusInterface0_Mmux_n0250_Result_20_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => N49922,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_14_19,
      O => PerLBusInterface0_n0250(20)
    );
  PerLBusInterface0_RegBank_14_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_25_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => PerLBusInterface0_RegBank_14_24,
      ADR2 => N49940,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(25)
    );
  PerLBusInterface0_Mmux_n0250_Result_24_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49938,
      ADR1 => PerLBusInterface0_RegBank_14_23,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(24)
    );
  PerLBusInterface0_RegBank_14_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_27_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_14_26,
      ADR2 => N49948,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(27)
    );
  PerLBusInterface0_Mmux_n0250_Result_26_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_14_25,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49944,
      O => PerLBusInterface0_n0250(26)
    );
  PerLBusInterface0_RegBank_14_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_29_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => PerLBusInterface0_RegBank_14_28,
      ADR2 => VCC,
      ADR3 => N49952,
      O => PerLBusInterface0_n0250(29)
    );
  PerLBusInterface0_Mmux_n0250_Result_28_1 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_27,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => VCC,
      ADR3 => N49950,
      O => PerLBusInterface0_n0250(28)
    );
  PerLBusInterface0_RegBank_14_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_3_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_2,
      ADR1 => N49982,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0250(3)
    );
  PerLBusInterface0_Mmux_n0250_Result_23_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => N49934,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_14_22,
      O => PerLBusInterface0_n0250(23)
    );
  PerLBusInterface0_RegBank_14_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_31_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49946,
      ADR2 => PerLBusInterface0_RegBank_14_30,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(31)
    );
  PerLBusInterface0_Mmux_n0250_Result_30_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => N49942,
      ADR3 => PerLBusInterface0_RegBank_14_29,
      O => PerLBusInterface0_n0250(30)
    );
  PerLBusInterface0_RegBank_14_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_5_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49994,
      ADR1 => PerLBusInterface0_RegBank_14_4,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(5)
    );
  PerLBusInterface0_Mmux_n0250_Result_4_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49988,
      ADR3 => PerLBusInterface0_RegBank_14_3,
      O => PerLBusInterface0_n0250(4)
    );
  PerLBusInterface0_RegBank_14_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_7_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49886,
      ADR1 => PerLBusInterface0_RegBank_14_6,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(7)
    );
  PerLBusInterface0_Mmux_n0250_Result_6_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_14_5,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N50002,
      O => PerLBusInterface0_n0250(6)
    );
  PerLBusInterface0_RegBank_14_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0250_Result_9_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => N49898,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_14_8,
      O => PerLBusInterface0_n0250(9)
    );
  PerLBusInterface0_Mmux_n0250_Result_8_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => PerLBusInterface0_RegBank_14_7,
      ADR2 => N49892,
      ADR3 => VCC,
      O => PerLBusInterface0_n0250(8)
    );
  PerLBusInterface0_RegBank_14_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_14_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_1_1 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => N49970,
      ADR1 => PerLBusInterface0_RegBank_15_0,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(1)
    );
  PerLBusInterface0_Mmux_n0251_Result_0_1 : X_LUT4
    generic map(
      INIT => X"0F00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49964,
      O => PerLBusInterface0_n0251(0)
    );
  PerLBusInterface0_RegBank_15_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_11_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_10,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(11)
    );
  PerLBusInterface0_Mmux_n0251_Result_10_1 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => N49910,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_15_9,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(10)
    );
  PerLBusInterface0_RegBank_15_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_13_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_12,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49916,
      O => PerLBusInterface0_n0251(13)
    );
  PerLBusInterface0_Mmux_n0251_Result_12_1 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => N49914,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_15_11,
      O => PerLBusInterface0_n0251(12)
    );
  PerLBusInterface0_RegBank_15_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_15_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49920,
      ADR2 => PerLBusInterface0_RegBank_15_14,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(15)
    );
  PerLBusInterface0_Mmux_n0251_Result_14_1 : X_LUT4
    generic map(
      INIT => X"AFA0"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_13,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => N49918,
      O => PerLBusInterface0_n0251(14)
    );
  PerLBusInterface0_RegBank_15_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_17_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_16,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(17)
    );
  PerLBusInterface0_Mmux_n0251_Result_16_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N49924,
      ADR2 => PerLBusInterface0_RegBank_15_15,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(16)
    );
  PerLBusInterface0_RegBank_15_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_19_1 : X_LUT4
    generic map(
      INIT => X"F0AA"
    )
    port map (
      ADR0 => N49936,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_15_18,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(19)
    );
  PerLBusInterface0_Mmux_n0251_Result_18_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => PerLBusInterface0_RegBank_15_17,
      ADR2 => VCC,
      ADR3 => N49932,
      O => PerLBusInterface0_n0251(18)
    );
  PerLBusInterface0_RegBank_15_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_2_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_15_1,
      ADR3 => N49976,
      O => PerLBusInterface0_n0251(2)
    );
  PerLBusInterface0_Mmux_n0251_Result_22_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => N49930,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_15_21,
      O => PerLBusInterface0_n0251(22)
    );
  PerLBusInterface0_RegBank_15_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_21_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_20,
      ADR1 => N49926,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(21)
    );
  PerLBusInterface0_Mmux_n0251_Result_20_1 : X_LUT4
    generic map(
      INIT => X"F3C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => PerLBusInterface0_RegBank_15_19,
      ADR3 => N49922,
      O => PerLBusInterface0_n0251(20)
    );
  PerLBusInterface0_RegBank_15_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_25_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49940,
      ADR2 => PerLBusInterface0_RegBank_15_24,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(25)
    );
  PerLBusInterface0_Mmux_n0251_Result_24_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => PerLBusInterface0_RegBank_15_23,
      ADR2 => VCC,
      ADR3 => N49938,
      O => PerLBusInterface0_n0251(24)
    );
  PerLBusInterface0_RegBank_15_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_27_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => N49948,
      ADR3 => PerLBusInterface0_RegBank_15_26,
      O => PerLBusInterface0_n0251(27)
    );
  PerLBusInterface0_Mmux_n0251_Result_26_1 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_15_25,
      ADR1 => N49944,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(26)
    );
  PerLBusInterface0_RegBank_15_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_29_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49952,
      ADR3 => PerLBusInterface0_RegBank_15_28,
      O => PerLBusInterface0_n0251(29)
    );
  PerLBusInterface0_Mmux_n0251_Result_28_1 : X_LUT4
    generic map(
      INIT => X"CACA"
    )
    port map (
      ADR0 => N49950,
      ADR1 => PerLBusInterface0_RegBank_15_27,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(28)
    );
  PerLBusInterface0_RegBank_15_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_3_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49982,
      ADR3 => PerLBusInterface0_RegBank_15_2,
      O => PerLBusInterface0_n0251(3)
    );
  PerLBusInterface0_Mmux_n0251_Result_23_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49934,
      ADR3 => PerLBusInterface0_RegBank_15_22,
      O => PerLBusInterface0_n0251(23)
    );
  PerLBusInterface0_RegBank_15_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_31_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49946,
      ADR3 => PerLBusInterface0_RegBank_15_30,
      O => PerLBusInterface0_n0251(31)
    );
  PerLBusInterface0_Mmux_n0251_Result_30_1 : X_LUT4
    generic map(
      INIT => X"FC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => N49942,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_15_29,
      O => PerLBusInterface0_n0251(30)
    );
  PerLBusInterface0_RegBank_15_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_5_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49994,
      ADR2 => PerLBusInterface0_RegBank_15_4,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(5)
    );
  PerLBusInterface0_Mmux_n0251_Result_4_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_15_3,
      ADR2 => N49988,
      ADR3 => PerLBusInterface0_GateDataOut_1,
      O => PerLBusInterface0_n0251(4)
    );
  PerLBusInterface0_RegBank_15_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_7_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => N49886,
      ADR2 => PerLBusInterface0_RegBank_15_6,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(7)
    );
  PerLBusInterface0_Mmux_n0251_Result_6_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => N50002,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_GateDataOut_1,
      ADR3 => PerLBusInterface0_RegBank_15_5,
      O => PerLBusInterface0_n0251(6)
    );
  PerLBusInterface0_RegBank_15_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_Mmux_n0251_Result_9_1 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => N49898,
      ADR1 => PerLBusInterface0_GateDataOut_1,
      ADR2 => PerLBusInterface0_RegBank_15_8,
      ADR3 => VCC,
      O => PerLBusInterface0_n0251(9)
    );
  PerLBusInterface0_Mmux_n0251_Result_8_1 : X_LUT4
    generic map(
      INIT => X"FA50"
    )
    port map (
      ADR0 => PerLBusInterface0_GateDataOut_1,
      ADR1 => VCC,
      ADR2 => N49892,
      ADR3 => PerLBusInterface0_RegBank_15_7,
      O => PerLBusInterface0_n0251(8)
    );
  PerLBusInterface0_RegBank_15_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_15_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_16_1_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_16_1_FROM
    );
  PerLBusInterface0_RegBank_16_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_16_1_FROM,
      O => PerLBusInterface0_RegBank_16_1_X
    );
  PerLBusInterface0_RegBank_16_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_16_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_16_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_16_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_11_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_18_11_FROM
    );
  PerLBusInterface0_RegBank_18_11_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_18_11_FROM,
      O => PerLBusInterface0_RegBank_18_11_X
    );
  PerLBusInterface0_RegBank_18_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_23_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_25_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_18_25_FROM
    );
  PerLBusInterface0_RegBank_18_25_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_18_25_GROM
    );
  PerLBusInterface0_RegBank_18_25_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_18_25_FROM,
      O => PerLBusInterface0_RegBank_18_25_X
    );
  PerLBusInterface0_RegBank_18_25_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_18_25_GROM,
      O => PerLBusInterface0_RegBank_18_25_Y
    );
  PerLBusInterface0_RegBank_18_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_18_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_18_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_16_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_1_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_1_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_23_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_25_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_27_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_29_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_31_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_5_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_20_5_FROM
    );
  PerLBusInterface0_RegBank_20_5_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_20_5_GROM
    );
  PerLBusInterface0_RegBank_20_5_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_20_5_FROM,
      O => PerLBusInterface0_RegBank_20_5_X
    );
  PerLBusInterface0_RegBank_20_5_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_20_5_GROM,
      O => PerLBusInterface0_RegBank_20_5_Y
    );
  PerLBusInterface0_RegBank_20_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_20_9_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_20_9_FROM
    );
  PerLBusInterface0_RegBank_20_9_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_20_9_GROM
    );
  PerLBusInterface0_RegBank_20_9_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_20_9_FROM,
      O => PerLBusInterface0_RegBank_20_9_X
    );
  PerLBusInterface0_RegBank_20_9_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_20_9_GROM,
      O => PerLBusInterface0_RegBank_20_9_Y
    );
  PerLBusInterface0_RegBank_20_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_20_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_3_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_3_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_11_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_4_11_GROM
    );
  PerLBusInterface0_RegBank_4_11_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_4_11_GROM,
      O => PerLBusInterface0_RegBank_4_11_Y
    );
  PerLBusInterface0_RegBank_4_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_13_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_4_13_FROM
    );
  PerLBusInterface0_RegBank_4_13_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_4_13_FROM,
      O => PerLBusInterface0_RegBank_4_13_X
    );
  PerLBusInterface0_RegBank_4_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_15_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd13_In18 : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_4_20,
      ADR1 => PerLBusInterface0_RegBank_4_21,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_CtrlState_FFd10,
      O => PerLBusInterface0_RegBank_4_20_GROM
    );
  PerLBusInterface0_RegBank_4_20_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_4_20_GROM,
      O => CHOICE351
    );
  PerLBusInterface0_RegBank_4_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_20_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_n003416 : X_LUT4
    generic map(
      INIT => X"0030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_ScanCount_42,
      ADR2 => BScanCtrl0_ScanCount_40,
      ADR3 => PerLBusInterface0_RegBank_4_20,
      O => PerLBusInterface0_RegBank_4_21_FROM
    );
  BScanCtrl0_n003421 : X_LUT4
    generic map(
      INIT => X"A500"
    )
    port map (
      ADR0 => BScanCtrl0_ScanCount_41,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_4_21,
      ADR3 => CHOICE647,
      O => PerLBusInterface0_RegBank_4_21_GROM
    );
  PerLBusInterface0_RegBank_4_21_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_4_21_FROM,
      O => CHOICE647
    );
  PerLBusInterface0_RegBank_4_21_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_4_21_GROM,
      O => CHOICE648
    );
  PerLBusInterface0_RegBank_4_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_21_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_4_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_4_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_10_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_Ker289051 : X_LUT4
    generic map(
      INIT => X"0FFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_5_11,
      ADR3 => PerLBusInterface0_RegBank_5_10,
      O => PerLBusInterface0_RegBank_5_11_GROM
    );
  PerLBusInterface0_RegBank_5_11_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_5_11_GROM,
      O => FocusUnitCtrl0_N28907
    );
  PerLBusInterface0_RegBank_5_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_5_LOGIC_ZERO_854 : X_ZERO
    port map (
      O => PerLBusInterface0_RegBank_5_5_LOGIC_ZERO
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_72_855 : X_MUX2
    port map (
      IA => PerLBusInterface0_RegBank_5_5_LOGIC_ZERO,
      IB => PerLBusInterface0_RegBank_5_5_CYINIT,
      SEL => BScanCtrl0_Mcompar_n0040_inst_lut4_42,
      O => BScanCtrl0_Mcompar_n0040_inst_cy_72
    );
  BScanCtrl0_Mcompar_n0040_inst_lut4_421 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_5,
      ADR1 => BScanCtrl0_ScanCount_44,
      ADR2 => PerLBusInterface0_RegBank_5_4,
      ADR3 => BScanCtrl0_ScanCount_45,
      O => BScanCtrl0_Mcompar_n0040_inst_lut4_42
    );
  BScanCtrl0_Mcompar_n0040_inst_lut4_431 : X_LUT4
    generic map(
      INIT => X"A5A5"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_6,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_ScanCount_46,
      ADR3 => VCC,
      O => BScanCtrl0_Mcompar_n0040_inst_lut4_43
    );
  PerLBusInterface0_RegBank_5_5_COUTUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_5_5_CYMUXG,
      O => BScanCtrl0_n0040
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_73 : X_MUX2
    port map (
      IA => PerLBusInterface0_RegBank_5_5_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0040_inst_cy_72,
      SEL => BScanCtrl0_Mcompar_n0040_inst_lut4_43,
      O => PerLBusInterface0_RegBank_5_5_CYMUXG
    );
  PerLBusInterface0_RegBank_5_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_5_CYINIT_856 : X_BUF
    port map (
      I => BScanCtrl0_Mcompar_n0040_inst_cy_71_CYMUXG,
      O => PerLBusInterface0_RegBank_5_5_CYINIT
    );
  PerLBusInterface0_RegBank_5_8_LOGIC_ZERO_857 : X_ZERO
    port map (
      O => PerLBusInterface0_RegBank_5_8_LOGIC_ZERO
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_72_858 : X_MUX2
    port map (
      IA => PerLBusInterface0_RegBank_5_8_LOGIC_ZERO,
      IB => PerLBusInterface0_RegBank_5_8_CYINIT,
      SEL => BScanCtrl0_Mcompar_n0041_inst_lut4_42,
      O => BScanCtrl0_Mcompar_n0041_inst_cy_72
    );
  BScanCtrl0_Mcompar_n0041_inst_lut4_421 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_4,
      ADR1 => PerLBusInterface0_RegBank_5_5,
      ADR2 => BScanCtrl0_RxCount(4),
      ADR3 => BScanCtrl0_RxCount(5),
      O => BScanCtrl0_Mcompar_n0041_inst_lut4_42
    );
  BScanCtrl0_Mcompar_n0041_inst_lut4_431 : X_LUT4
    generic map(
      INIT => X"9999"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(6),
      ADR1 => PerLBusInterface0_RegBank_5_6,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Mcompar_n0041_inst_lut4_43
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_73 : X_MUX2
    port map (
      IA => PerLBusInterface0_RegBank_5_8_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0041_inst_cy_72,
      SEL => BScanCtrl0_Mcompar_n0041_inst_lut4_43,
      O => PerLBusInterface0_RegBank_5_8_CYMUXG
    );
  PerLBusInterface0_RegBank_5_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_5_8_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_5_8_CYINIT_859 : X_BUF
    port map (
      I => BScanCtrl0_Mcompar_n0041_inst_cy_71_CYMUXG,
      O => PerLBusInterface0_RegBank_5_8_CYINIT
    );
  PerLBusInterface0_RegBank_63_12_LOGIC_ZERO_860 : X_ZERO
    port map (
      O => PerLBusInterface0_RegBank_63_12_LOGIC_ZERO
    );
  PerLBusInterface0_RegBank_63_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_63_12_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_14_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_5_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_6_9_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_6_9_FROM
    );
  PerLBusInterface0_RegBank_6_9_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_6_9_FROM,
      O => PerLBusInterface0_RegBank_6_9_X
    );
  PerLBusInterface0_RegBank_6_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_6_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_1_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_7_1_GROM
    );
  PerLBusInterface0_RegBank_7_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_7_1_GROM,
      O => PerLBusInterface0_RegBank_7_1_Y
    );
  PerLBusInterface0_RegBank_7_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_11_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_13_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_17_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_Mmux_n0016_inst_mux_f6_0111 : X_MUX2
    port map (
      IA => N51012,
      IB => N51014,
      SEL => PerLBusInterface0_RegBank_7_16,
      O => PerLBusInterface0_RegBank_7_18_F5MUX
    );
  EncoderMonitor0_Mmux_n0016_inst_mux_f6_0111_G : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_17,
      ADR1 => PerLBusInterface0_RegBank_7_18,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_pEncoderReset(1),
      O => N51014
    );
  EncoderMonitor0_Mmux_n0016_inst_mux_f6_0111_F : X_LUT4
    generic map(
      INIT => X"5140"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_7_18,
      ADR1 => PerLBusInterface0_RegBank_7_17,
      ADR2 => PerLBusInterface0_pEncoderReset(2),
      ADR3 => PerLBusInterface0_pEncoderReset(0),
      O => N51012
    );
  PerLBusInterface0_RegBank_7_18_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_7_18_F5MUX,
      O => EncoderMonitor0_n0016
    );
  PerLBusInterface0_RegBank_7_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_18_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_3_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_5_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n0077_6_SW0 : X_LUT4
    generic map(
      INIT => X"FF3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => EncoderMonitor0_vTrigCountMin,
      ADR2 => PerLBusInterface0_RegBank_7_6,
      ADR3 => EncoderMonitor0_SelEncInc_1,
      O => PerLBusInterface0_RegBank_7_7_GROM
    );
  PerLBusInterface0_RegBank_7_7_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_7_7_GROM,
      O => N46283
    );
  PerLBusInterface0_RegBank_7_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_7_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_RegBank_7_9_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_RegBank_7_9_GROM
    );
  PerLBusInterface0_RegBank_7_9_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_7_9_GROM,
      O => PerLBusInterface0_RegBank_7_9_Y
    );
  PerLBusInterface0_RegBank_7_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegBank_7_9_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03241 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_n0297,
      ADR2 => PerLBusInterface0_N35395,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_n0324
    );
  PerLBusInterface0_n03251 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_N35395,
      ADR3 => PerLBusInterface0_n0297,
      O => PerLBusInterface0_n0325
    );
  PerLBusInterface0_RegWriteEn_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_10_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0323_SW0 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_6_2,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_RegWriteEn_14_FROM
    );
  PerLBusInterface0_n0323_861 : X_LUT4
    generic map(
      INIT => X"0020"
    )
    port map (
      ADR0 => PerLBusInterface0_n0297,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => N46894,
      O => PerLBusInterface0_n0323
    );
  PerLBusInterface0_RegWriteEn_14_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegWriteEn_14_FROM,
      O => N46894
    );
  PerLBusInterface0_RegWriteEn_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_14_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0322_SW0 : X_LUT4
    generic map(
      INIT => X"FBFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => PerLBusInterface0_IntAddr_4_2,
      ADR2 => PerLBusInterface0_IntAddr_6_2,
      ADR3 => PerLBusInterface0_IntAddr_5_2,
      O => PerLBusInterface0_RegWriteEn_15_FROM
    );
  PerLBusInterface0_n0322_862 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_n0297,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => N46943,
      O => PerLBusInterface0_n0322
    );
  PerLBusInterface0_RegWriteEn_15_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegWriteEn_15_FROM,
      O => N46943
    );
  PerLBusInterface0_RegWriteEn_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_15_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n02971 : X_LUT4
    generic map(
      INIT => X"00CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_LWnR,
      ADR2 => VCC,
      ADR3 => pnFpgaCs_IBUF,
      O => PerLBusInterface0_RegWriteEn_17_FROM
    );
  PerLBusInterface0_n03201 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => PerLBusInterface0_N35448,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_IntAddr_3_2,
      ADR3 => PerLBusInterface0_n0297,
      O => PerLBusInterface0_n0320
    );
  PerLBusInterface0_RegWriteEn_17_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegWriteEn_17_FROM,
      O => PerLBusInterface0_n0297
    );
  PerLBusInterface0_RegWriteEn_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_17_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03181 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_n0297,
      ADR3 => PerLBusInterface0_N35448,
      O => PerLBusInterface0_n0318
    );
  PerLBusInterface0_n03191 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => PerLBusInterface0_N35448,
      ADR1 => PerLBusInterface0_n0297,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_n0319
    );
  PerLBusInterface0_RegWriteEn_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_19_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03321 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_N35462,
      ADR3 => PerLBusInterface0_n0297,
      O => PerLBusInterface0_n0332
    );
  PerLBusInterface0_n03331 : X_LUT4
    generic map(
      INIT => X"0800"
    )
    port map (
      ADR0 => PerLBusInterface0_LWnR,
      ADR1 => PerLBusInterface0_N35462,
      ADR2 => pnFpgaCs_IBUF,
      ADR3 => PerLBusInterface0_N35424,
      O => PerLBusInterface0_n0333
    );
  PerLBusInterface0_RegWriteEn_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0317_SW113_SW0 : X_LUT4
    generic map(
      INIT => X"EFFF"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_7_1,
      ADR1 => PerLBusInterface0_IntAddr_5_2,
      ADR2 => PerLBusInterface0_IntAddr_4_2,
      ADR3 => PerLBusInterface0_IntAddr_6_2,
      O => PerLBusInterface0_RegWriteEn_20_FROM
    );
  PerLBusInterface0_n0317_SW113 : X_LUT4
    generic map(
      INIT => X"0010"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_n0297,
      ADR3 => N50895,
      O => PerLBusInterface0_n0317
    );
  PerLBusInterface0_RegWriteEn_20_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_RegWriteEn_20_FROM,
      O => N50895
    );
  PerLBusInterface0_RegWriteEn_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_20_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03301 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => PerLBusInterface0_LWnR,
      ADR1 => pnFpgaCs_IBUF,
      ADR2 => PerLBusInterface0_N35424,
      ADR3 => PerLBusInterface0_N35455,
      O => PerLBusInterface0_n0330
    );
  PerLBusInterface0_n03311 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_n0297,
      ADR3 => PerLBusInterface0_N35462,
      O => PerLBusInterface0_n0331
    );
  PerLBusInterface0_RegWriteEn_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_4_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03281 : X_LUT4
    generic map(
      INIT => X"2000"
    )
    port map (
      ADR0 => PerLBusInterface0_n0297,
      ADR1 => PerLBusInterface0_IntAddr_2_2,
      ADR2 => PerLBusInterface0_N35455,
      ADR3 => PerLBusInterface0_IntAddr_3_2,
      O => PerLBusInterface0_n0328
    );
  PerLBusInterface0_n03291 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_3_2,
      ADR1 => PerLBusInterface0_n0297,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_N35455,
      O => PerLBusInterface0_n0329
    );
  PerLBusInterface0_RegWriteEn_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_6_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n03261 : X_LUT4
    generic map(
      INIT => X"1000"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_2_2,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_N35395,
      ADR3 => PerLBusInterface0_n0297,
      O => PerLBusInterface0_n0326
    );
  PerLBusInterface0_n03271 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => PerLBusInterface0_n0297,
      ADR1 => PerLBusInterface0_IntAddr_3_2,
      ADR2 => PerLBusInterface0_IntAddr_2_2,
      ADR3 => PerLBusInterface0_N35455,
      O => PerLBusInterface0_n0327
    );
  PerLBusInterface0_RegWriteEn_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_RegWriteEn_8_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_StrobeExtender0_n00131 : X_LUT4
    generic map(
      INIT => X"EAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_ForceBScan,
      ADR1 => PerLBusInterface0_StrobeExtender0_CountLFSR(1),
      ADR2 => PerLBusInterface0_StrobeExtender0_CountLFSR(2),
      ADR3 => PerLBusInterface0_StrobeExtender0_CountLFSR(0),
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FROM
    );
  PerLBusInterface0_StrobeExtender0_Mxor_FeedbackBit_Result1 : X_LUT4
    generic map(
      INIT => X"3C3C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_StrobeExtender0_CountLFSR(1),
      ADR2 => PerLBusInterface0_StrobeExtender0_CountLFSR(2),
      ADR3 => VCC,
      O => PerLBusInterface0_StrobeExtender0_FeedbackBit
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_1_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FROM,
      O => PerLBusInterface0_StrobeExtender0_n0013
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_StrobeExtender0_n00071 : X_LUT4
    generic map(
      INIT => X"FF7F"
    )
    port map (
      ADR0 => PerLBusInterface0_StrobeExtender0_CountLFSR(2),
      ADR1 => PerLBusInterface0_StrobeExtender0_CountLFSR(0),
      ADR2 => PerLBusInterface0_StrobeExtender0_CountLFSR(1),
      ADR3 => PerLBusInterface0_ForceBScan,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_2_GROM
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_StrobeExtender0_CountLFSR_2_GROM,
      O => PerLBusInterface0_StrobeExtender0_n0007
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_2_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_StrobeExtender0_pStrobeOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => PerLBusInterface0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT
    );
  PerLBusInterface0_n0000_1_LOGIC_ZERO_863 : X_ZERO
    port map (
      O => PerLBusInterface0_n0000_1_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0000_inst_cy_111_864 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => PerLBusInterface0_n0000_1_LOGIC_ZERO,
      SEL => PerLBusInterface0_Madd_n0000_inst_lut2_49,
      O => PerLBusInterface0_Madd_n0000_inst_cy_111
    );
  PerLBusInterface0_Madd_n0000_inst_lut2_491 : X_LUT4
    generic map(
      INIT => X"3333"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => PerLBusInterface0_IntAddr(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_Madd_n0000_inst_lut2_49
    );
  PerLBusInterface0_n0000_1_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr(3),
      ADR3 => VCC,
      O => PerLBusInterface0_n0000_1_GROM
    );
  PerLBusInterface0_n0000_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0000_1_XORG,
      O => PerLBusInterface0_n0000(1)
    );
  PerLBusInterface0_Madd_n0000_inst_cy_112 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => PerLBusInterface0_Madd_n0000_inst_cy_111,
      SEL => PerLBusInterface0_n0000_1_GROM,
      O => PerLBusInterface0_n0000_1_CYMUXG
    );
  PerLBusInterface0_Madd_n0000_inst_sum_97 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0000_inst_cy_111,
      I1 => PerLBusInterface0_n0000_1_GROM,
      O => PerLBusInterface0_n0000_1_XORG
    );
  PerLBusInterface0_n0000_2_LOGIC_ZERO_865 : X_ZERO
    port map (
      O => PerLBusInterface0_n0000_2_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0000_inst_cy_113_866 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0000_2_LOGIC_ZERO,
      IB => PerLBusInterface0_n0000_2_CYINIT,
      SEL => PerLBusInterface0_n0000_2_FROM,
      O => PerLBusInterface0_Madd_n0000_inst_cy_113
    );
  PerLBusInterface0_Madd_n0000_inst_sum_98 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0000_2_CYINIT,
      I1 => PerLBusInterface0_n0000_2_FROM,
      O => PerLBusInterface0_n0000_2_XORF
    );
  PerLBusInterface0_n0000_2_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_IntAddr_4_1,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0000_2_FROM
    );
  PerLBusInterface0_n0000_2_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_5_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0000_2_GROM
    );
  PerLBusInterface0_n0000_2_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0000_2_XORF,
      O => PerLBusInterface0_n0000(2)
    );
  PerLBusInterface0_n0000_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0000_2_XORG,
      O => PerLBusInterface0_n0000(3)
    );
  PerLBusInterface0_Madd_n0000_inst_cy_114 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0000_2_LOGIC_ZERO,
      IB => PerLBusInterface0_Madd_n0000_inst_cy_113,
      SEL => PerLBusInterface0_n0000_2_GROM,
      O => PerLBusInterface0_n0000_2_CYMUXG
    );
  PerLBusInterface0_Madd_n0000_inst_sum_99 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0000_inst_cy_113,
      I1 => PerLBusInterface0_n0000_2_GROM,
      O => PerLBusInterface0_n0000_2_XORG
    );
  PerLBusInterface0_n0000_2_CYINIT_867 : X_BUF
    port map (
      I => PerLBusInterface0_n0000_1_CYMUXG,
      O => PerLBusInterface0_n0000_2_CYINIT
    );
  PerLBusInterface0_n0000_4_LOGIC_ZERO_868 : X_ZERO
    port map (
      O => PerLBusInterface0_n0000_4_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0000_inst_cy_115_869 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0000_4_LOGIC_ZERO,
      IB => PerLBusInterface0_n0000_4_CYINIT,
      SEL => PerLBusInterface0_n0000_4_FROM,
      O => PerLBusInterface0_Madd_n0000_inst_cy_115
    );
  PerLBusInterface0_Madd_n0000_inst_sum_100 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0000_4_CYINIT,
      I1 => PerLBusInterface0_n0000_4_FROM,
      O => PerLBusInterface0_n0000_4_XORF
    );
  PerLBusInterface0_n0000_4_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_6_1,
      ADR3 => VCC,
      O => PerLBusInterface0_n0000_4_FROM
    );
  PerLBusInterface0_IntAddr_7_1_rt_870 : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_IntAddr_7_1,
      ADR3 => VCC,
      O => PerLBusInterface0_IntAddr_7_1_rt
    );
  PerLBusInterface0_n0000_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0000_4_XORF,
      O => PerLBusInterface0_n0000(4)
    );
  PerLBusInterface0_n0000_4_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0000_4_XORG,
      O => PerLBusInterface0_n0000(5)
    );
  PerLBusInterface0_Madd_n0000_inst_sum_101 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0000_inst_cy_115,
      I1 => PerLBusInterface0_IntAddr_7_1_rt,
      O => PerLBusInterface0_n0000_4_XORG
    );
  PerLBusInterface0_n0000_4_CYINIT_871 : X_BUF
    port map (
      I => PerLBusInterface0_n0000_2_CYMUXG,
      O => PerLBusInterface0_n0000_4_CYINIT
    );
  PerLBusInterface0_n0152_1_LOGIC_ZERO_872 : X_ZERO
    port map (
      O => PerLBusInterface0_n0152_1_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0152_inst_cy_74_873 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => PerLBusInterface0_n0152_1_LOGIC_ZERO,
      SEL => PerLBusInterface0_Madd_n0152_inst_lut2_20,
      O => PerLBusInterface0_Madd_n0152_inst_cy_74
    );
  PerLBusInterface0_Madd_n0152_inst_lut2_201 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_DelayValAddr(2),
      O => PerLBusInterface0_Madd_n0152_inst_lut2_20
    );
  PerLBusInterface0_n0152_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_DelayValAddr(3),
      O => PerLBusInterface0_n0152_1_GROM
    );
  PerLBusInterface0_n0152_1_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_1_XORG,
      O => PerLBusInterface0_n0152(1)
    );
  PerLBusInterface0_Madd_n0152_inst_cy_75 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => PerLBusInterface0_Madd_n0152_inst_cy_74,
      SEL => PerLBusInterface0_n0152_1_GROM,
      O => PerLBusInterface0_n0152_1_CYMUXG
    );
  PerLBusInterface0_Madd_n0152_inst_sum_61 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0152_inst_cy_74,
      I1 => PerLBusInterface0_n0152_1_GROM,
      O => PerLBusInterface0_n0152_1_XORG
    );
  PerLBusInterface0_n0152_2_LOGIC_ZERO_874 : X_ZERO
    port map (
      O => PerLBusInterface0_n0152_2_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0152_inst_cy_76_875 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0152_2_LOGIC_ZERO,
      IB => PerLBusInterface0_n0152_2_CYINIT,
      SEL => PerLBusInterface0_n0152_2_FROM,
      O => PerLBusInterface0_Madd_n0152_inst_cy_76
    );
  PerLBusInterface0_Madd_n0152_inst_sum_62 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0152_2_CYINIT,
      I1 => PerLBusInterface0_n0152_2_FROM,
      O => PerLBusInterface0_n0152_2_XORF
    );
  PerLBusInterface0_n0152_2_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_DelayValAddr(4),
      ADR3 => VCC,
      O => PerLBusInterface0_n0152_2_FROM
    );
  PerLBusInterface0_n0152_2_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_DelayValAddr(5),
      ADR3 => VCC,
      O => PerLBusInterface0_n0152_2_GROM
    );
  PerLBusInterface0_n0152_2_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_2_XORF,
      O => PerLBusInterface0_n0152(2)
    );
  PerLBusInterface0_n0152_2_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_2_XORG,
      O => PerLBusInterface0_n0152(3)
    );
  PerLBusInterface0_Madd_n0152_inst_cy_77 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0152_2_LOGIC_ZERO,
      IB => PerLBusInterface0_Madd_n0152_inst_cy_76,
      SEL => PerLBusInterface0_n0152_2_GROM,
      O => PerLBusInterface0_n0152_2_CYMUXG
    );
  PerLBusInterface0_Madd_n0152_inst_sum_63 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0152_inst_cy_76,
      I1 => PerLBusInterface0_n0152_2_GROM,
      O => PerLBusInterface0_n0152_2_XORG
    );
  PerLBusInterface0_n0152_2_CYINIT_876 : X_BUF
    port map (
      I => PerLBusInterface0_n0152_1_CYMUXG,
      O => PerLBusInterface0_n0152_2_CYINIT
    );
  PerLBusInterface0_n0152_4_LOGIC_ZERO_877 : X_ZERO
    port map (
      O => PerLBusInterface0_n0152_4_LOGIC_ZERO
    );
  PerLBusInterface0_Madd_n0152_inst_cy_78_878 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0152_4_LOGIC_ZERO,
      IB => PerLBusInterface0_n0152_4_CYINIT,
      SEL => PerLBusInterface0_n0152_4_FROM,
      O => PerLBusInterface0_Madd_n0152_inst_cy_78
    );
  PerLBusInterface0_Madd_n0152_inst_sum_64 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0152_4_CYINIT,
      I1 => PerLBusInterface0_n0152_4_FROM,
      O => PerLBusInterface0_n0152_4_XORF
    );
  PerLBusInterface0_n0152_4_F : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddr(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0152_4_FROM
    );
  PerLBusInterface0_n0152_4_G : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddr(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_n0152_4_GROM
    );
  PerLBusInterface0_n0152_4_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_4_XORF,
      O => PerLBusInterface0_n0152(4)
    );
  PerLBusInterface0_n0152_4_YUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_4_XORG,
      O => PerLBusInterface0_n0152(5)
    );
  PerLBusInterface0_Madd_n0152_inst_cy_79 : X_MUX2
    port map (
      IA => PerLBusInterface0_n0152_4_LOGIC_ZERO,
      IB => PerLBusInterface0_Madd_n0152_inst_cy_78,
      SEL => PerLBusInterface0_n0152_4_GROM,
      O => PerLBusInterface0_n0152_4_CYMUXG
    );
  PerLBusInterface0_Madd_n0152_inst_sum_65 : X_XOR2
    port map (
      I0 => PerLBusInterface0_Madd_n0152_inst_cy_78,
      I1 => PerLBusInterface0_n0152_4_GROM,
      O => PerLBusInterface0_n0152_4_XORG
    );
  PerLBusInterface0_n0152_4_CYINIT_879 : X_BUF
    port map (
      I => PerLBusInterface0_n0152_2_CYMUXG,
      O => PerLBusInterface0_n0152_4_CYINIT
    );
  PerLBusInterface0_Madd_n0152_inst_sum_66 : X_XOR2
    port map (
      I0 => PerLBusInterface0_n0152_6_CYINIT,
      I1 => PerLBusInterface0_DelayValAddr_8_rt,
      O => PerLBusInterface0_n0152_6_XORF
    );
  PerLBusInterface0_DelayValAddr_8_rt_880 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => PerLBusInterface0_DelayValAddr(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => PerLBusInterface0_DelayValAddr_8_rt
    );
  PerLBusInterface0_n0152_6_XUSED : X_BUF
    port map (
      I => PerLBusInterface0_n0152_6_XORF,
      O => PerLBusInterface0_n0152(6)
    );
  PerLBusInterface0_n0152_6_CYINIT_881 : X_BUF
    port map (
      I => PerLBusInterface0_n0152_4_CYMUXG,
      O => PerLBusInterface0_n0152_6_CYINIT
    );
  FocusUnitCtrl0_CtrlState_FFd3_882 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd3_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd3_FFX_RST,
      O => FocusUnitCtrl0_CtrlState_FFd3
    );
  FocusUnitCtrl0_CtrlState_FFd3_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd3_FFX_RST
    );
  FocusUnitCtrl0_CtrlState_FFd5_883 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd5_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd6_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd5
    );
  FocusUnitCtrl0_CtrlState_FFd6_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd6_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd6_884 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd6_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd6_FFX_RST,
      O => FocusUnitCtrl0_CtrlState_FFd6
    );
  FocusUnitCtrl0_CtrlState_FFd6_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd6_FFX_RST
    );
  FocusUnitCtrl0_CtrlState_FFd7_885 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd7_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd8_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd7
    );
  FocusUnitCtrl0_CtrlState_FFd8_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd8_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd8_886 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd8_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd8_FFX_RST,
      O => FocusUnitCtrl0_CtrlState_FFd8
    );
  FocusUnitCtrl0_CtrlState_FFd8_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd8_FFX_RST
    );
  FocusUnitCtrl0_DelayDataDone_887 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0052,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayDataDone_FFY_RST,
      O => FocusUnitCtrl0_DelayDataDone
    );
  FocusUnitCtrl0_DelayDataDone_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayDataDone_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayDataDone_FFY_RST
    );
  FocusUnitCtrl0_DelayValAddr_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0050(0),
      CE => FocusUnitCtrl0_n0065,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValAddr_0_FFY_RST,
      O => FocusUnitCtrl0_DelayValAddr(0)
    );
  FocusUnitCtrl0_DelayValAddr_0_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValAddr_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValAddr_0_FFY_RST
    );
  FocusUnitCtrl0_DelayValAddr_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0050(1),
      CE => FocusUnitCtrl0_n0065,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValAddr_1_FFY_RST,
      O => FocusUnitCtrl0_DelayValAddr(1)
    );
  FocusUnitCtrl0_DelayValAddr_1_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValAddr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValAddr_1_FFY_RST
    );
  TriggerDelay0_DelayCount_3_57_LOGIC_ONE_888 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_57_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_145_889 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => TriggerDelay0_DelayCount_3_57_LOGIC_ONE,
      SEL => TriggerDelay0_n0025_rt,
      O => TriggerDelay0_DelayCount_3_inst_cy_145
    );
  TriggerDelay0_n0025_rt_890 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_n0025_rt
    );
  TriggerDelay0_DelayCount_3_57_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_DelayCount_3_inst_lut3_281_O,
      ADR3 => VCC,
      O => TriggerDelay0_DelayCount_3_57_GROM
    );
  TriggerDelay0_DelayCount_3_inst_cy_146 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => TriggerDelay0_DelayCount_3_inst_cy_145,
      SEL => TriggerDelay0_DelayCount_3_57_GROM,
      O => TriggerDelay0_DelayCount_3_57_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_128_891 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_145,
      I1 => TriggerDelay0_DelayCount_3_57_GROM,
      O => TriggerDelay0_DelayCount_3_inst_sum_128
    );
  TriggerDelay0_DelayCount_3_57_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_57_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_58_LOGIC_ONE_892 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_58_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_147_893 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_58_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_3_inst_cy_147
    );
  TriggerDelay0_DelayCount_3_inst_sum_129_894 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_58_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_291_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_129
    );
  TriggerDelay0_DelayCount_3_inst_lut3_291 : X_LUT4
    generic map(
      INIT => X"02F7"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_1,
      ADR2 => N50552,
      ADR3 => TriggerDelay0_DelayCount_3_58,
      O => TriggerDelay0_DelayCount_3_inst_lut3_291_O
    );
  TriggerDelay0_DelayCount_3_inst_lut3_301 : X_LUT4
    generic map(
      INIT => X"0F27"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_2,
      ADR2 => TriggerDelay0_DelayCount_3_59,
      ADR3 => N50552,
      O => TriggerDelay0_DelayCount_3_inst_lut3_301_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_148 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_58_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_147,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_3_58_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_130_895 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_147,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_301_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_130
    );
  TriggerDelay0_DelayCount_3_58_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_58_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_58_CYINIT_896 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_57_CYMUXG,
      O => TriggerDelay0_DelayCount_3_58_CYINIT
    );
  TriggerDelay0_DelayCount_3_60_LOGIC_ONE_897 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_60_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_149_898 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_60_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_3_inst_cy_149
    );
  TriggerDelay0_DelayCount_3_inst_sum_131_899 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_60_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_311_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_131
    );
  TriggerDelay0_DelayCount_3_inst_lut3_311 : X_LUT4
    generic map(
      INIT => X"10BF"
    )
    port map (
      ADR0 => N50552,
      ADR1 => PerLBusInterface0_RegBank_1_3,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => TriggerDelay0_DelayCount_3_60,
      O => TriggerDelay0_DelayCount_3_inst_lut3_311_O
    );
  TriggerDelay0_DelayCount_3_inst_lut3_321 : X_LUT4
    generic map(
      INIT => X"3353"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_4,
      ADR1 => TriggerDelay0_DelayCount_3_61,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => N50552,
      O => TriggerDelay0_DelayCount_3_inst_lut3_321_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_150 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_60_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_149,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_3_60_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_132_900 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_149,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_321_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_132
    );
  TriggerDelay0_DelayCount_3_60_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_60_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_60_CYINIT_901 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_58_CYMUXG,
      O => TriggerDelay0_DelayCount_3_60_CYINIT
    );
  TriggerDelay0_DelayCount_3_62_LOGIC_ONE_902 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_62_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_151_903 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_62_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_331_O,
      O => TriggerDelay0_DelayCount_3_inst_cy_151
    );
  TriggerDelay0_DelayCount_3_inst_sum_133_904 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_62_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_331_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_133
    );
  TriggerDelay0_DelayCount_3_inst_lut3_331 : X_LUT4
    generic map(
      INIT => X"10BF"
    )
    port map (
      ADR0 => N50552,
      ADR1 => PerLBusInterface0_RegBank_1_5,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => TriggerDelay0_DelayCount_3_62,
      O => TriggerDelay0_DelayCount_3_inst_lut3_331_O
    );
  TriggerDelay0_DelayCount_3_inst_lut3_341 : X_LUT4
    generic map(
      INIT => X"0B4F"
    )
    port map (
      ADR0 => N50552,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => TriggerDelay0_DelayCount_3_63,
      ADR3 => PerLBusInterface0_RegBank_1_6,
      O => TriggerDelay0_DelayCount_3_inst_lut3_341_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_152 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_62_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_151,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_3_62_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_134_905 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_151,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_341_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_134
    );
  TriggerDelay0_DelayCount_3_62_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_62_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_62_CYINIT_906 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_60_CYMUXG,
      O => TriggerDelay0_DelayCount_3_62_CYINIT
    );
  TriggerDelay0_DelayCount_3_64_LOGIC_ONE_907 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_64_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_153_908 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_64_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_35,
      O => TriggerDelay0_DelayCount_3_inst_cy_153
    );
  TriggerDelay0_DelayCount_3_inst_sum_135_909 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_64_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_35,
      O => TriggerDelay0_DelayCount_3_inst_sum_135
    );
  TriggerDelay0_DelayCount_3_inst_lut3_351 : X_LUT4
    generic map(
      INIT => X"04BF"
    )
    port map (
      ADR0 => N50568,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => PerLBusInterface0_RegBank_1_7,
      ADR3 => TriggerDelay0_DelayCount_3_64,
      O => TriggerDelay0_DelayCount_3_inst_lut3_35
    );
  TriggerDelay0_DelayCount_3_inst_lut3_361 : X_LUT4
    generic map(
      INIT => X"02F7"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => PerLBusInterface0_RegBank_1_8,
      ADR2 => N50552,
      ADR3 => TriggerDelay0_DelayCount_3_65,
      O => TriggerDelay0_DelayCount_3_inst_lut3_361_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_154 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_64_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_153,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_361_O,
      O => TriggerDelay0_DelayCount_3_64_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_136_910 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_153,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_361_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_136
    );
  TriggerDelay0_DelayCount_3_64_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_64_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_64_CYINIT_911 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_62_CYMUXG,
      O => TriggerDelay0_DelayCount_3_64_CYINIT
    );
  TriggerDelay0_DelayCount_3_66_LOGIC_ONE_912 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_66_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_155_913 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_66_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_37,
      O => TriggerDelay0_DelayCount_3_inst_cy_155
    );
  TriggerDelay0_DelayCount_3_inst_sum_137_914 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_66_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_37,
      O => TriggerDelay0_DelayCount_3_inst_sum_137
    );
  TriggerDelay0_DelayCount_3_inst_lut3_371 : X_LUT4
    generic map(
      INIT => X"02DF"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerRegs_1_1,
      ADR1 => N50552,
      ADR2 => PerLBusInterface0_RegBank_1_9,
      ADR3 => TriggerDelay0_DelayCount_3_66,
      O => TriggerDelay0_DelayCount_3_inst_lut3_37
    );
  TriggerDelay0_DelayCount_3_inst_lut3_381 : X_LUT4
    generic map(
      INIT => X"303F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_1_10,
      ADR2 => TriggerDelay0_n0025,
      ADR3 => TriggerDelay0_DelayCount_3_67,
      O => TriggerDelay0_DelayCount_3_inst_lut3_381_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_156 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_66_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_155,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_3_66_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_138_915 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_155,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_381_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_138
    );
  TriggerDelay0_DelayCount_3_66_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_66_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_66_CYINIT_916 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_64_CYMUXG,
      O => TriggerDelay0_DelayCount_3_66_CYINIT
    );
  TriggerDelay0_DelayCount_3_68_LOGIC_ONE_917 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_68_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_157_918 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_68_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_3_inst_cy_157
    );
  TriggerDelay0_DelayCount_3_inst_sum_139_919 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_68_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_391_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_139
    );
  TriggerDelay0_DelayCount_3_inst_lut3_391 : X_LUT4
    generic map(
      INIT => X"330F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_RegBank_1_11,
      ADR2 => TriggerDelay0_DelayCount_3_68,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_DelayCount_3_inst_lut3_391_O
    );
  TriggerDelay0_DelayCount_3_inst_lut3_401 : X_LUT4
    generic map(
      INIT => X"505F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_12,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_n0025,
      ADR3 => TriggerDelay0_DelayCount_3_69,
      O => TriggerDelay0_DelayCount_3_inst_lut3_401_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_158 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_68_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_157,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_3_68_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_140_920 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_157,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_401_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_140
    );
  TriggerDelay0_DelayCount_3_68_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_68_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_68_CYINIT_921 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_66_CYMUXG,
      O => TriggerDelay0_DelayCount_3_68_CYINIT
    );
  TriggerDelay0_DelayCount_3_70_LOGIC_ONE_922 : X_ONE
    port map (
      O => TriggerDelay0_DelayCount_3_70_LOGIC_ONE
    );
  TriggerDelay0_DelayCount_3_inst_cy_159_923 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_70_CYINIT,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_3_inst_cy_159
    );
  TriggerDelay0_DelayCount_3_inst_sum_141_924 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_70_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_411_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_141
    );
  TriggerDelay0_DelayCount_3_inst_lut3_411 : X_LUT4
    generic map(
      INIT => X"0F33"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayCount_3_70,
      ADR2 => PerLBusInterface0_RegBank_1_13,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_DelayCount_3_inst_lut3_411_O
    );
  TriggerDelay0_DelayCount_3_inst_lut3_421 : X_LUT4
    generic map(
      INIT => X"550F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_14,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_DelayCount_3_71,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_DelayCount_3_inst_lut3_421_O
    );
  TriggerDelay0_DelayCount_3_inst_cy_160 : X_MUX2
    port map (
      IA => TriggerDelay0_DelayCount_3_70_LOGIC_ONE,
      IB => TriggerDelay0_DelayCount_3_inst_cy_159,
      SEL => TriggerDelay0_DelayCount_3_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_3_70_CYMUXG
    );
  TriggerDelay0_DelayCount_3_inst_sum_142_925 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_inst_cy_159,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_421_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_142
    );
  TriggerDelay0_DelayCount_3_70_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_70_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_70_CYINIT_926 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_68_CYMUXG,
      O => TriggerDelay0_DelayCount_3_70_CYINIT
    );
  TriggerDelay0_DelayCount_3_inst_sum_143_927 : X_XOR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_72_CYINIT,
      I1 => TriggerDelay0_DelayCount_3_inst_lut3_431_O,
      O => TriggerDelay0_DelayCount_3_inst_sum_143
    );
  TriggerDelay0_DelayCount_3_inst_lut3_431 : X_LUT4
    generic map(
      INIT => X"550F"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_15,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_DelayCount_3_72,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_DelayCount_3_inst_lut3_431_O
    );
  TriggerDelay0_n00781 : X_LUT4
    generic map(
      INIT => X"FF88"
    )
    port map (
      ADR0 => TriggerDelay0_n0048,
      ADR1 => TriggerDelay0_DelayActive(3),
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0025,
      O => TriggerDelay0_DelayCount_3_72_GROM
    );
  TriggerDelay0_DelayCount_3_72_YUSED : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_72_GROM,
      O => TriggerDelay0_n0078
    );
  TriggerDelay0_DelayCount_3_72_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_DelayCount_3_72_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_3_72_CYINIT_928 : X_BUF
    port map (
      I => TriggerDelay0_DelayCount_3_70_CYMUXG,
      O => TriggerDelay0_DelayCount_3_72_CYINIT
    );
  TriggerDelay0_n0038_0_1 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerOut(2),
      ADR1 => TriggerDelay0_TriggerOut(0),
      ADR2 => TriggerDelay0_TriggerOut(1),
      ADR3 => TriggerDelay0_TriggerOut(3),
      O => TriggerDelay0_n0038(0)
    );
  TriggerDelay0_OutShifter_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_OutShifter_0_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n00641 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_TriggerOut(3),
      ADR1 => TriggerDelay0_TriggerOut(1),
      ADR2 => TriggerDelay0_TriggerOut(2),
      ADR3 => TriggerDelay0_TriggerOut(0),
      O => TriggerDelay0_OutShifter_1_FROM
    );
  TriggerDelay0_n0038_1_1 : X_LUT4
    generic map(
      INIT => X"CCFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_OutShifter(0),
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0064,
      O => TriggerDelay0_n0038(1)
    );
  TriggerDelay0_OutShifter_1_XUSED : X_BUF
    port map (
      I => TriggerDelay0_OutShifter_1_FROM,
      O => TriggerDelay0_n0064
    );
  TriggerDelay0_OutShifter_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_OutShifter_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n005175 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => CHOICE589,
      ADR1 => CHOICE596,
      ADR2 => CHOICE581,
      ADR3 => N50596,
      O => TriggerDelay0_TriggerOut_0_FROM
    );
  TriggerDelay0_n00291 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(0),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0051,
      O => TriggerDelay0_n0029
    );
  TriggerDelay0_TriggerOut_0_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerOut_0_FROM,
      O => TriggerDelay0_n0051
    );
  TriggerDelay0_TriggerOut_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerOut_0_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n005075 : X_LUT4
    generic map(
      INIT => X"0080"
    )
    port map (
      ADR0 => CHOICE565,
      ADR1 => CHOICE558,
      ADR2 => CHOICE550,
      ADR3 => N50600,
      O => TriggerDelay0_TriggerOut_1_FROM
    );
  TriggerDelay0_n00281 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayActive(1),
      ADR2 => VCC,
      ADR3 => TriggerDelay0_n0050,
      O => TriggerDelay0_n0028
    );
  TriggerDelay0_TriggerOut_1_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerOut_1_FROM,
      O => TriggerDelay0_n0050
    );
  TriggerDelay0_TriggerOut_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerOut_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n004975 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => N50588,
      ADR1 => CHOICE496,
      ADR2 => CHOICE503,
      ADR3 => CHOICE488,
      O => TriggerDelay0_TriggerOut_2_FROM
    );
  TriggerDelay0_n00271 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => TriggerDelay0_DelayActive(2),
      ADR2 => TriggerDelay0_n0049,
      ADR3 => VCC,
      O => TriggerDelay0_n0027
    );
  TriggerDelay0_TriggerOut_2_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerOut_2_FROM,
      O => TriggerDelay0_n0049
    );
  TriggerDelay0_TriggerOut_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerOut_2_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n004875 : X_LUT4
    generic map(
      INIT => X"4000"
    )
    port map (
      ADR0 => N50592,
      ADR1 => CHOICE534,
      ADR2 => CHOICE519,
      ADR3 => CHOICE527,
      O => TriggerDelay0_TriggerOut_3_FROM
    );
  TriggerDelay0_n00261 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_DelayActive(3),
      ADR3 => TriggerDelay0_n0048,
      O => TriggerDelay0_n0026
    );
  TriggerDelay0_TriggerOut_3_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerOut_3_FROM,
      O => TriggerDelay0_n0048
    );
  TriggerDelay0_TriggerOut_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerOut_3_SRMUX_OUTPUTNOT
    );
  FocusUnitCtrl0_CtrlState_FFd13_In11 : X_LUT4
    generic map(
      INIT => X"CC0C"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_CtrlState_FFd13,
      ADR2 => BScanCtrl0_pTriggerOut,
      ADR3 => FocusUnitCtrl0_vLastTrigger,
      O => TriggerDelay0_TriggerRegs_1_FROM
    );
  Mmux_RawTrigger_Result1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_1_16,
      ADR1 => BScanCtrl0_pTriggerOut,
      ADR2 => pZ9_IBUF,
      ADR3 => VCC,
      O => RawTrigger
    );
  TriggerDelay0_TriggerRegs_1_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerRegs_1_FROM,
      O => CHOICE347
    );
  TriggerDelay0_TriggerRegs_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerRegs_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_0_inst_lut3_331_SW0 : X_LUT4
    generic map(
      INIT => X"FFFE"
    )
    port map (
      ADR0 => TriggerDelay0_ActiveCount(0),
      ADR1 => TriggerDelay0_DelayActive(0),
      ADR2 => TriggerDelay0_TriggerRegs(2),
      ADR3 => TriggerDelay0_ActiveCount(1),
      O => TriggerDelay0_TriggerRegs_2_FROM
    );
  TriggerDelay0_DelayCount_0_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"551D"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_0_57,
      ADR1 => TriggerDelay0_TriggerRegs_1_1,
      ADR2 => PerLBusInterface0_RegBank_1_0,
      ADR3 => N50536,
      O => TriggerDelay0_TriggerRegs_2_GROM
    );
  TriggerDelay0_TriggerRegs_2_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerRegs_2_FROM,
      O => N50536
    );
  TriggerDelay0_TriggerRegs_2_YUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerRegs_2_GROM,
      O => TriggerDelay0_DelayCount_0_inst_lut3_281_O
    );
  TriggerDelay0_TriggerRegs_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerRegs_2_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_DelayCount_1_inst_lut3_351_SW0 : X_LUT4
    generic map(
      INIT => X"FEFF"
    )
    port map (
      ADR0 => TriggerDelay0_DelayActive(1),
      ADR1 => TriggerDelay0_ActiveCount(1),
      ADR2 => TriggerDelay0_TriggerRegs(2),
      ADR3 => TriggerDelay0_ActiveCount(0),
      O => TriggerDelay0_TriggerRegs_1_1_FROM
    );
  TriggerDelay0_DelayCount_1_inst_lut3_281 : X_LUT4
    generic map(
      INIT => X"5535"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_57,
      ADR1 => PerLBusInterface0_RegBank_1_0,
      ADR2 => TriggerDelay0_TriggerRegs_1_1,
      ADR3 => N50560,
      O => TriggerDelay0_TriggerRegs_1_1_GROM
    );
  TriggerDelay0_TriggerRegs_1_1_XUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerRegs_1_1_FROM,
      O => N50560
    );
  TriggerDelay0_TriggerRegs_1_1_YUSED : X_BUF
    port map (
      I => TriggerDelay0_TriggerRegs_1_1_GROM,
      O => TriggerDelay0_DelayCount_1_inst_lut3_281_O
    );
  TriggerDelay0_TriggerRegs_1_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => TriggerDelay0_TriggerRegs_1_1_SRMUX_OUTPUTNOT
    );
  TriggerDelay0_n0038_2_1 : X_LUT4
    generic map(
      INIT => X"F0FF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => TriggerDelay0_OutShifter(1),
      ADR3 => TriggerDelay0_n0064,
      O => TriggerDelay0_n0038_2_GROM
    );
  pAIN_0_OBUF : X_TRI
    port map (
      I => pAIN_0_OUTMUX,
      CTL => pAIN_0_ENABLE,
      O => pAIN(0)
    );
  pAIN_0_ENABLEINV : X_INV
    port map (
      I => pAIN_0_TORGTS,
      O => pAIN_0_ENABLE
    );
  pAIN_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAIN_0_TORGTS
    );
  pAIN_0_OUTMUX_929 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_2_1,
      O => pAIN_0_OUTMUX
    );
  pAIN_0_OMUX : X_BUF
    port map (
      I => N49976,
      O => pAIN_0_OD
    );
  pAIN_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pAIN_0_SRMUXNOT
    );
  pAIN_1_OBUF : X_TRI
    port map (
      I => pAIN_1_OUTMUX,
      CTL => pAIN_1_ENABLE,
      O => pAIN(1)
    );
  pAIN_1_ENABLEINV : X_INV
    port map (
      I => pAIN_1_TORGTS,
      O => pAIN_1_ENABLE
    );
  pAIN_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAIN_1_TORGTS
    );
  pAIN_1_OUTMUX_930 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_3_1,
      O => pAIN_1_OUTMUX
    );
  pAIN_1_OMUX : X_BUF
    port map (
      I => N49982,
      O => pAIN_1_OD
    );
  pAIN_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pAIN_1_SRMUXNOT
    );
  pAIN_2_OBUF : X_TRI
    port map (
      I => pAIN_2_OUTMUX,
      CTL => pAIN_2_ENABLE,
      O => pAIN(2)
    );
  pAIN_2_ENABLEINV : X_INV
    port map (
      I => pAIN_2_TORGTS,
      O => pAIN_2_ENABLE
    );
  pAIN_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAIN_2_TORGTS
    );
  pAIN_2_OUTMUX_931 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_4_1,
      O => pAIN_2_OUTMUX
    );
  pAIN_2_OMUX : X_BUF
    port map (
      I => N49988,
      O => pAIN_2_OD
    );
  pAIN_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pAIN_2_SRMUXNOT
    );
  pAIN_3_OBUF : X_TRI
    port map (
      I => pAIN_3_OUTMUX,
      CTL => pAIN_3_ENABLE,
      O => pAIN(3)
    );
  pAIN_3_ENABLEINV : X_INV
    port map (
      I => pAIN_3_TORGTS,
      O => pAIN_3_ENABLE
    );
  pAIN_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAIN_3_TORGTS
    );
  pAIN_3_OUTMUX_932 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_5_1,
      O => pAIN_3_OUTMUX
    );
  pAIN_3_OMUX : X_BUF
    port map (
      I => N49994,
      O => pAIN_3_OD
    );
  pAIN_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pAIN_3_SRMUXNOT
    );
  pATOD_RANGE_OBUF : X_TRI
    port map (
      I => pATOD_RANGE_OUTMUX,
      CTL => pATOD_RANGE_ENABLE,
      O => pATOD_RANGE
    );
  pATOD_RANGE_ENABLEINV : X_INV
    port map (
      I => pATOD_RANGE_TORGTS,
      O => pATOD_RANGE_ENABLE
    );
  pATOD_RANGE_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pATOD_RANGE_TORGTS
    );
  pATOD_RANGE_OUTMUX_933 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_14_1,
      O => pATOD_RANGE_OUTMUX
    );
  pAUX_0_OBUF : X_TRI
    port map (
      I => pAUX_0_OUTMUX,
      CTL => pAUX_0_ENABLE,
      O => pAUX(0)
    );
  pAUX_0_ENABLEINV : X_INV
    port map (
      I => pAUX_0_TORGTS,
      O => pAUX_0_ENABLE
    );
  pAUX_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAUX_0_TORGTS
    );
  pAUX_0_OUTMUX_934 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_23_1,
      O => pAUX_0_OUTMUX
    );
  pAUX_1_OBUF : X_TRI
    port map (
      I => pAUX_1_OUTMUX,
      CTL => pAUX_1_ENABLE,
      O => pAUX(1)
    );
  pAUX_1_ENABLEINV : X_INV
    port map (
      I => pAUX_1_TORGTS,
      O => pAUX_1_ENABLE
    );
  pAUX_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pAUX_1_TORGTS
    );
  pAUX_1_OUTMUX_935 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_24_1,
      O => pAUX_1_OUTMUX
    );
  pCAL_0_OBUF : X_TRI
    port map (
      I => pCAL_0_OUTMUX,
      CTL => pCAL_0_ENABLE,
      O => pCAL(0)
    );
  pCAL_0_ENABLEINV : X_INV
    port map (
      I => pCAL_0_TORGTS,
      O => pCAL_0_ENABLE
    );
  pCAL_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCAL_0_TORGTS
    );
  pCAL_0_OUTMUX_936 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_20_1,
      O => pCAL_0_OUTMUX
    );
  pCAL_0_OMUX : X_BUF
    port map (
      I => N49922,
      O => pCAL_0_OD
    );
  pCAL_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pCAL_0_SRMUXNOT
    );
  pCAL_1_OBUF : X_TRI
    port map (
      I => pCAL_1_OUTMUX,
      CTL => pCAL_1_ENABLE,
      O => pCAL(1)
    );
  pCAL_1_ENABLEINV : X_INV
    port map (
      I => pCAL_1_TORGTS,
      O => pCAL_1_ENABLE
    );
  pCAL_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCAL_1_TORGTS
    );
  pCAL_1_OUTMUX_937 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_21_1,
      O => pCAL_1_OUTMUX
    );
  pCAL_1_OMUX : X_BUF
    port map (
      I => N49926,
      O => pCAL_1_OD
    );
  pCAL_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pCAL_1_SRMUXNOT
    );
  pCAL_2_OBUF : X_TRI
    port map (
      I => pCAL_2_OUTMUX,
      CTL => pCAL_2_ENABLE,
      O => pCAL(2)
    );
  pCAL_2_ENABLEINV : X_INV
    port map (
      I => pCAL_2_TORGTS,
      O => pCAL_2_ENABLE
    );
  pCAL_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCAL_2_TORGTS
    );
  pCAL_2_OUTMUX_938 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_22_1,
      O => pCAL_2_OUTMUX
    );
  pCAL_2_OMUX : X_BUF
    port map (
      I => N49930,
      O => pCAL_2_OD
    );
  pCAL_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pCAL_2_SRMUXNOT
    );
  OFD1_OBUF : X_TRI
    port map (
      I => pCalDac_CLK_OUTMUX,
      CTL => pCalDac_CLK_ENABLE,
      O => pCalDac_CLK
    );
  pCalDac_CLK_ENABLEINV : X_INV
    port map (
      I => pCalDac_CLK_TORGTS,
      O => pCalDac_CLK_ENABLE
    );
  pCalDac_CLK_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCalDac_CLK_TORGTS
    );
  pCalDac_CLK_OUTMUX_939 : X_BUF
    port map (
      I => OFD1_QBUF,
      O => pCalDac_CLK_OUTMUX
    );
  pCalDac_CLK_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_CLK,
      O => pCalDac_CLK_OD
    );
  OFD0_OBUF : X_TRI
    port map (
      I => pCalDac_SDI_OUTMUX,
      CTL => pCalDac_SDI_ENABLE,
      O => pCalDac_SDI
    );
  pCalDac_SDI_ENABLEINV : X_INV
    port map (
      I => pCalDac_SDI_TORGTS,
      O => pCalDac_SDI_ENABLE
    );
  pCalDac_SDI_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCalDac_SDI_TORGTS
    );
  pCalDac_SDI_OUTMUX_940 : X_BUF
    port map (
      I => OFD0_QBUF,
      O => pCalDac_SDI_OUTMUX
    );
  pCalDac_SDI_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_CalDacShiftReg(13),
      O => pCalDac_SDI_OD
    );
  OFD3_OBUF : X_TRI
    port map (
      I => pCalDac_nCS_OUTMUX,
      CTL => pCalDac_nCS_ENABLE,
      O => pCalDac_nCS
    );
  pCalDac_nCS_ENABLEINV : X_INV
    port map (
      I => pCalDac_nCS_TORGTS,
      O => pCalDac_nCS_ENABLE
    );
  pCalDac_nCS_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCalDac_nCS_TORGTS
    );
  pCalDac_nCS_OUTMUX_941 : X_BUF
    port map (
      I => OFD3_QBUF,
      O => pCalDac_nCS_OUTMUX
    );
  pCalDac_nCS_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_nCS,
      O => pCalDac_nCS_OD
    );
  OFD2_OBUF : X_TRI
    port map (
      I => pCalDac_nLD_OUTMUX,
      CTL => pCalDac_nLD_ENABLE,
      O => pCalDac_nLD
    );
  pCalDac_nLD_ENABLEINV : X_INV
    port map (
      I => pCalDac_nLD_TORGTS,
      O => pCalDac_nLD_ENABLE
    );
  pCalDac_nLD_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pCalDac_nLD_TORGTS
    );
  pCalDac_nLD_OUTMUX_942 : X_BUF
    port map (
      I => OFD2_QBUF,
      O => pCalDac_nLD_OUTMUX
    );
  pCalDac_nLD_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pCalDac_nLD,
      O => pCalDac_nLD_OD
    );
  pDATA_FORMAT_OBUF : X_TRI
    port map (
      I => pDATA_FORMAT_OUTMUX,
      CTL => pDATA_FORMAT_ENABLE,
      O => pDATA_FORMAT
    );
  pDATA_FORMAT_ENABLEINV : X_INV
    port map (
      I => pDATA_FORMAT_TORGTS,
      O => pDATA_FORMAT_ENABLE
    );
  pDATA_FORMAT_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pDATA_FORMAT_TORGTS
    );
  pDATA_FORMAT_OUTMUX_943 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_13_1,
      O => pDATA_FORMAT_OUTMUX
    );
  pDdsFsk_OBUF : X_TRI
    port map (
      I => pDdsFsk_OUTMUX,
      CTL => pDdsFsk_ENABLE,
      O => pDdsFsk
    );
  pDdsFsk_ENABLEINV : X_INV
    port map (
      I => pDdsFsk_TORGTS,
      O => pDdsFsk_ENABLE
    );
  pDdsFsk_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pDdsFsk_TORGTS
    );
  pDdsFsk_OUTMUX_944 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_19_1,
      O => pDdsFsk_OUTMUX
    );
  pDdsFsk_OMUX : X_BUF
    port map (
      I => N49936,
      O => pDdsFsk_OD
    );
  pDdsFsk_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pDdsFsk_SRMUXNOT
    );
  pDdsKey_OBUF : X_TRI
    port map (
      I => pDdsKey_OUTMUX,
      CTL => pDdsKey_ENABLE,
      O => pDdsKey
    );
  pDdsKey_ENABLEINV : X_INV
    port map (
      I => pDdsKey_TORGTS,
      O => pDdsKey_ENABLE
    );
  pDdsKey_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pDdsKey_TORGTS
    );
  pDdsKey_OUTMUX_945 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_18_1,
      O => pDdsKey_OUTMUX
    );
  pDdsKey_OMUX : X_BUF
    port map (
      I => N49932,
      O => pDdsKey_OD
    );
  pDdsKey_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pDdsKey_SRMUXNOT
    );
  pEncoder0In_0_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder0In(0)
    );
  IFD0_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder0In(0),
      O => IFD0_DBUF
    );
  pEncoder0In_0_DELAY : X_BUF
    port map (
      I => IFD0_DBUF,
      O => pEncoder0In_0_IDELAY
    );
  pEncoder0In_1_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder0In(1)
    );
  IFD1_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder0In(1),
      O => IFD1_DBUF
    );
  pEncoder0In_1_DELAY : X_BUF
    port map (
      I => IFD1_DBUF,
      O => pEncoder0In_1_IDELAY
    );
  pEncoder1In_0_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder1In(0)
    );
  IFD2_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder1In(0),
      O => IFD2_DBUF
    );
  pEncoder1In_0_DELAY : X_BUF
    port map (
      I => IFD2_DBUF,
      O => pEncoder1In_0_IDELAY
    );
  pEncoder1In_1_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder1In(1)
    );
  IFD3_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder1In(1),
      O => IFD3_DBUF
    );
  pEncoder1In_1_DELAY : X_BUF
    port map (
      I => IFD3_DBUF,
      O => pEncoder1In_1_IDELAY
    );
  pEncoder2In_0_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder2In(0)
    );
  IFD4_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder2In(0),
      O => IFD4_DBUF
    );
  pEncoder2In_0_DELAY : X_BUF
    port map (
      I => IFD4_DBUF,
      O => pEncoder2In_0_IDELAY
    );
  pEncoder2In_1_PULLDOWN : X_PD
    port map (
      O => NlwRenamedSig_IO_pEncoder2In(1)
    );
  IFD5_IBUF : X_BUF
    port map (
      I => NlwRenamedSig_IO_pEncoder2In(1),
      O => IFD5_DBUF
    );
  pEncoder2In_1_DELAY : X_BUF
    port map (
      I => IFD5_DBUF,
      O => pEncoder2In_1_IDELAY
    );
  pGAIN_0_OBUF : X_TRI
    port map (
      I => pGAIN_0_OUTMUX,
      CTL => pGAIN_0_ENABLE,
      O => pGAIN(0)
    );
  pGAIN_0_ENABLEINV : X_INV
    port map (
      I => pGAIN_0_TORGTS,
      O => pGAIN_0_ENABLE
    );
  pGAIN_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_0_TORGTS
    );
  pGAIN_0_OUTMUX_946 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_6_1,
      O => pGAIN_0_OUTMUX
    );
  pGAIN_1_OBUF : X_TRI
    port map (
      I => pGAIN_1_OUTMUX,
      CTL => pGAIN_1_ENABLE,
      O => pGAIN(1)
    );
  pGAIN_1_ENABLEINV : X_INV
    port map (
      I => pGAIN_1_TORGTS,
      O => pGAIN_1_ENABLE
    );
  pGAIN_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_1_TORGTS
    );
  pGAIN_1_OUTMUX_947 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_7_1,
      O => pGAIN_1_OUTMUX
    );
  pGAIN_2_OBUF : X_TRI
    port map (
      I => pGAIN_2_OUTMUX,
      CTL => pGAIN_2_ENABLE,
      O => pGAIN(2)
    );
  pGAIN_2_ENABLEINV : X_INV
    port map (
      I => pGAIN_2_TORGTS,
      O => pGAIN_2_ENABLE
    );
  pGAIN_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_2_TORGTS
    );
  pGAIN_2_OUTMUX_948 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_8_1,
      O => pGAIN_2_OUTMUX
    );
  pGAIN_3_OBUF : X_TRI
    port map (
      I => pGAIN_3_OUTMUX,
      CTL => pGAIN_3_ENABLE,
      O => pGAIN(3)
    );
  pGAIN_3_ENABLEINV : X_INV
    port map (
      I => pGAIN_3_TORGTS,
      O => pGAIN_3_ENABLE
    );
  pGAIN_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_3_TORGTS
    );
  pGAIN_3_OUTMUX_949 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_9_1,
      O => pGAIN_3_OUTMUX
    );
  pGAIN_4_OBUF : X_TRI
    port map (
      I => pGAIN_4_OUTMUX,
      CTL => pGAIN_4_ENABLE,
      O => pGAIN(4)
    );
  pGAIN_4_ENABLEINV : X_INV
    port map (
      I => pGAIN_4_TORGTS,
      O => pGAIN_4_ENABLE
    );
  pGAIN_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_4_TORGTS
    );
  pGAIN_4_OUTMUX_950 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_10_1,
      O => pGAIN_4_OUTMUX
    );
  pGAIN_5_OBUF : X_TRI
    port map (
      I => pGAIN_5_OUTMUX,
      CTL => pGAIN_5_ENABLE,
      O => pGAIN(5)
    );
  pGAIN_5_ENABLEINV : X_INV
    port map (
      I => pGAIN_5_TORGTS,
      O => pGAIN_5_ENABLE
    );
  pGAIN_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pGAIN_5_TORGTS
    );
  pGAIN_5_OUTMUX_951 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_11_1,
      O => pGAIN_5_OUTMUX
    );
  pLA_2_IMUX : X_BUF
    port map (
      I => pLA_2_IBUF_8,
      O => pLA_2_IBUF
    );
  pLA_2_IBUF_952 : X_BUF
    port map (
      I => pLA(2),
      O => pLA_2_IBUF_8
    );
  pLA_3_IMUX : X_BUF
    port map (
      I => pLA_3_IBUF_9,
      O => pLA_3_IBUF
    );
  pLA_3_IBUF_953 : X_BUF
    port map (
      I => pLA(3),
      O => pLA_3_IBUF_9
    );
  pLA_4_IMUX : X_BUF
    port map (
      I => pLA_4_IBUF_10,
      O => pLA_4_IBUF
    );
  pLA_4_IBUF_954 : X_BUF
    port map (
      I => pLA(4),
      O => pLA_4_IBUF_10
    );
  pLA_5_IMUX : X_BUF
    port map (
      I => pLA_5_IBUF_11,
      O => pLA_5_IBUF
    );
  pLA_5_IBUF_955 : X_BUF
    port map (
      I => pLA(5),
      O => pLA_5_IBUF_11
    );
  pLA_6_IMUX : X_BUF
    port map (
      I => pLA_6_IBUF_12,
      O => pLA_6_IBUF
    );
  pLA_6_IBUF_956 : X_BUF
    port map (
      I => pLA(6),
      O => pLA_6_IBUF_12
    );
  pLA_7_IMUX : X_BUF
    port map (
      I => pLA_7_IBUF_13,
      O => pLA_7_IBUF
    );
  pLA_7_IBUF_957 : X_BUF
    port map (
      I => pLA(7),
      O => pLA_7_IBUF_13
    );
  pLD_0_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_0_OUTMUX,
      CTL => pLD_0_ENABLE,
      O => pLD(0)
    );
  pLD_0_ENABLEINV : X_INV
    port map (
      I => pLD_0_TORGTS,
      O => pLD_0_ENABLE
    );
  pLD_0_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_0_TORGTS
    );
  pLD_0_OUTMUX_958 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_1_GROM,
      O => pLD_0_OUTMUX
    );
  pLD_0_IMUX : X_BUF
    port map (
      I => pLD_0_IBUF,
      O => N49964
    );
  pLD_0_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(0),
      O => pLD_0_IBUF
    );
  pLD_0_DELAY : X_BUF
    port map (
      I => pLD_0_IBUF,
      O => pLD_0_IDELAY
    );
  pLD_0_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_0_SRMUXNOT
    );
  pLD_10_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_10_OUTMUX,
      CTL => pLD_10_ENABLE,
      O => pLD(10)
    );
  pLD_10_ENABLEINV : X_INV
    port map (
      I => pLD_10_TORGTS,
      O => pLD_10_ENABLE
    );
  pLD_10_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_10_TORGTS
    );
  pLD_10_OUTMUX_959 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_11_GROM,
      O => pLD_10_OUTMUX
    );
  pLD_10_IMUX : X_BUF
    port map (
      I => pLD_10_IBUF,
      O => N49910
    );
  pLD_10_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(10),
      O => pLD_10_IBUF
    );
  pLD_10_DELAY : X_BUF
    port map (
      I => pLD_10_IBUF,
      O => pLD_10_IDELAY
    );
  pLD_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_10_SRMUXNOT
    );
  pLD_11_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_11_OUTMUX,
      CTL => pLD_11_ENABLE,
      O => pLD(11)
    );
  pLD_11_ENABLEINV : X_INV
    port map (
      I => pLD_11_TORGTS,
      O => pLD_11_ENABLE
    );
  pLD_11_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_11_TORGTS
    );
  pLD_11_OUTMUX_960 : X_BUF
    port map (
      I => LD_Out_11_GROM,
      O => pLD_11_OUTMUX
    );
  pLD_11_IMUX : X_BUF
    port map (
      I => pLD_11_IBUF,
      O => N49912
    );
  pLD_11_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(11),
      O => pLD_11_IBUF
    );
  pLD_11_DELAY : X_BUF
    port map (
      I => pLD_11_IBUF,
      O => pLD_11_IDELAY
    );
  pLD_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_11_SRMUXNOT
    );
  pLD_12_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_12_OUTMUX,
      CTL => pLD_12_ENABLE,
      O => pLD(12)
    );
  pLD_12_ENABLEINV : X_INV
    port map (
      I => pLD_12_TORGTS,
      O => pLD_12_ENABLE
    );
  pLD_12_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_12_TORGTS
    );
  pLD_12_OUTMUX_961 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_13_GROM,
      O => pLD_12_OUTMUX
    );
  pLD_12_IMUX : X_BUF
    port map (
      I => pLD_12_IBUF,
      O => N49914
    );
  pLD_12_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(12),
      O => pLD_12_IBUF
    );
  pLD_12_DELAY : X_BUF
    port map (
      I => pLD_12_IBUF,
      O => pLD_12_IDELAY
    );
  pLD_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_12_SRMUXNOT
    );
  pLD_13_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_13_OUTMUX,
      CTL => pLD_13_ENABLE,
      O => pLD(13)
    );
  pLD_13_ENABLEINV : X_INV
    port map (
      I => pLD_13_TORGTS,
      O => pLD_13_ENABLE
    );
  pLD_13_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_13_TORGTS
    );
  pLD_13_OUTMUX_962 : X_BUF
    port map (
      I => LD_Out_13_GROM,
      O => pLD_13_OUTMUX
    );
  pLD_13_IMUX : X_BUF
    port map (
      I => pLD_13_IBUF,
      O => N49916
    );
  pLD_13_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(13),
      O => pLD_13_IBUF
    );
  pLD_13_DELAY : X_BUF
    port map (
      I => pLD_13_IBUF,
      O => pLD_13_IDELAY
    );
  pLD_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_13_SRMUXNOT
    );
  pLD_14_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_14_OUTMUX,
      CTL => pLD_14_ENABLE,
      O => pLD(14)
    );
  pLD_14_ENABLEINV : X_INV
    port map (
      I => pLD_14_TORGTS,
      O => pLD_14_ENABLE
    );
  pLD_14_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_14_TORGTS
    );
  pLD_14_OUTMUX_963 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_15_GROM,
      O => pLD_14_OUTMUX
    );
  pLD_14_IMUX : X_BUF
    port map (
      I => pLD_14_IBUF,
      O => N49918
    );
  pLD_14_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(14),
      O => pLD_14_IBUF
    );
  pLD_14_DELAY : X_BUF
    port map (
      I => pLD_14_IBUF,
      O => pLD_14_IDELAY
    );
  pLD_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_14_SRMUXNOT
    );
  pLD_15_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_15_OUTMUX,
      CTL => pLD_15_ENABLE,
      O => pLD(15)
    );
  pLD_15_ENABLEINV : X_INV
    port map (
      I => pLD_15_TORGTS,
      O => pLD_15_ENABLE
    );
  pLD_15_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_15_TORGTS
    );
  pLD_15_OUTMUX_964 : X_BUF
    port map (
      I => LD_Out_15_GROM,
      O => pLD_15_OUTMUX
    );
  pLD_15_IMUX : X_BUF
    port map (
      I => pLD_15_IBUF,
      O => N49920
    );
  pLD_15_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(15),
      O => pLD_15_IBUF
    );
  pLD_15_DELAY : X_BUF
    port map (
      I => pLD_15_IBUF,
      O => pLD_15_IDELAY
    );
  pLD_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_15_SRMUXNOT
    );
  pLD_16_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_16_OUTMUX,
      CTL => pLD_16_ENABLE,
      O => pLD(16)
    );
  pLD_16_ENABLEINV : X_INV
    port map (
      I => pLD_16_TORGTS,
      O => pLD_16_ENABLE
    );
  pLD_16_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_16_TORGTS
    );
  pLD_16_OUTMUX_965 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_17_GROM,
      O => pLD_16_OUTMUX
    );
  pLD_16_IMUX : X_BUF
    port map (
      I => pLD_16_IBUF,
      O => N49924
    );
  pLD_16_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(16),
      O => pLD_16_IBUF
    );
  pLD_16_DELAY : X_BUF
    port map (
      I => pLD_16_IBUF,
      O => pLD_16_IDELAY
    );
  pLD_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_16_SRMUXNOT
    );
  pLD_17_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_17_OUTMUX,
      CTL => pLD_17_ENABLE,
      O => pLD(17)
    );
  pLD_17_ENABLEINV : X_INV
    port map (
      I => pLD_17_TORGTS,
      O => pLD_17_ENABLE
    );
  pLD_17_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_17_TORGTS
    );
  pLD_17_OUTMUX_966 : X_BUF
    port map (
      I => LD_Out_17_GROM,
      O => pLD_17_OUTMUX
    );
  pLD_17_IMUX : X_BUF
    port map (
      I => pLD_17_IBUF,
      O => N49928
    );
  pLD_17_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(17),
      O => pLD_17_IBUF
    );
  pLD_17_DELAY : X_BUF
    port map (
      I => pLD_17_IBUF,
      O => pLD_17_IDELAY
    );
  pLD_17_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_17_SRMUXNOT
    );
  pLD_18_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_18_OUTMUX,
      CTL => pLD_18_ENABLE,
      O => pLD(18)
    );
  pLD_18_ENABLEINV : X_INV
    port map (
      I => pLD_18_TORGTS,
      O => pLD_18_ENABLE
    );
  pLD_18_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_18_TORGTS
    );
  pLD_18_OUTMUX_967 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_19_GROM,
      O => pLD_18_OUTMUX
    );
  pLD_18_IMUX : X_BUF
    port map (
      I => pLD_18_IBUF,
      O => N49932
    );
  pLD_18_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(18),
      O => pLD_18_IBUF
    );
  pLD_18_DELAY : X_BUF
    port map (
      I => pLD_18_IBUF,
      O => pLD_18_IDELAY
    );
  pLD_18_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_18_SRMUXNOT
    );
  pLD_19_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_19_OUTMUX,
      CTL => pLD_19_ENABLE,
      O => pLD(19)
    );
  pLD_19_ENABLEINV : X_INV
    port map (
      I => pLD_19_TORGTS,
      O => pLD_19_ENABLE
    );
  pLD_19_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_19_TORGTS
    );
  pLD_19_OUTMUX_968 : X_BUF
    port map (
      I => LD_Out_19_GROM,
      O => pLD_19_OUTMUX
    );
  pLD_19_IMUX : X_BUF
    port map (
      I => pLD_19_IBUF,
      O => N49936
    );
  pLD_19_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(19),
      O => pLD_19_IBUF
    );
  pLD_19_DELAY : X_BUF
    port map (
      I => pLD_19_IBUF,
      O => pLD_19_IDELAY
    );
  pLD_19_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_19_SRMUXNOT
    );
  pLD_1_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_1_OUTMUX,
      CTL => pLD_1_ENABLE,
      O => pLD(1)
    );
  pLD_1_ENABLEINV : X_INV
    port map (
      I => pLD_1_TORGTS,
      O => pLD_1_ENABLE
    );
  pLD_1_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_1_TORGTS
    );
  pLD_1_OUTMUX_969 : X_BUF
    port map (
      I => LD_Out_1_GROM,
      O => pLD_1_OUTMUX
    );
  pLD_1_IMUX : X_BUF
    port map (
      I => pLD_1_IBUF,
      O => N49970
    );
  pLD_1_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(1),
      O => pLD_1_IBUF
    );
  pLD_1_DELAY : X_BUF
    port map (
      I => pLD_1_IBUF,
      O => pLD_1_IDELAY
    );
  pLD_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_1_SRMUXNOT
    );
  pLD_20_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_20_OUTMUX,
      CTL => pLD_20_ENABLE,
      O => pLD(20)
    );
  pLD_20_ENABLEINV : X_INV
    port map (
      I => pLD_20_TORGTS,
      O => pLD_20_ENABLE
    );
  pLD_20_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_20_TORGTS
    );
  pLD_20_OUTMUX_970 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_21_GROM,
      O => pLD_20_OUTMUX
    );
  pLD_20_IMUX : X_BUF
    port map (
      I => pLD_20_IBUF,
      O => N49922
    );
  pLD_20_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(20),
      O => pLD_20_IBUF
    );
  pLD_20_DELAY : X_BUF
    port map (
      I => pLD_20_IBUF,
      O => pLD_20_IDELAY
    );
  pLD_20_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_20_SRMUXNOT
    );
  pLD_21_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_21_OUTMUX,
      CTL => pLD_21_ENABLE,
      O => pLD(21)
    );
  pLD_21_ENABLEINV : X_INV
    port map (
      I => pLD_21_TORGTS,
      O => pLD_21_ENABLE
    );
  pLD_21_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_21_TORGTS
    );
  pLD_21_OUTMUX_971 : X_BUF
    port map (
      I => LD_Out_21_GROM,
      O => pLD_21_OUTMUX
    );
  pLD_21_IMUX : X_BUF
    port map (
      I => pLD_21_IBUF,
      O => N49926
    );
  pLD_21_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(21),
      O => pLD_21_IBUF
    );
  pLD_21_DELAY : X_BUF
    port map (
      I => pLD_21_IBUF,
      O => pLD_21_IDELAY
    );
  pLD_21_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_21_SRMUXNOT
    );
  pLD_22_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_22_OUTMUX,
      CTL => pLD_22_ENABLE,
      O => pLD(22)
    );
  pLD_22_ENABLEINV : X_INV
    port map (
      I => pLD_22_TORGTS,
      O => pLD_22_ENABLE
    );
  pLD_22_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_22_TORGTS
    );
  pLD_22_OUTMUX_972 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_23_GROM,
      O => pLD_22_OUTMUX
    );
  pLD_22_IMUX : X_BUF
    port map (
      I => pLD_22_IBUF,
      O => N49930
    );
  pLD_22_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(22),
      O => pLD_22_IBUF
    );
  pLD_22_DELAY : X_BUF
    port map (
      I => pLD_22_IBUF,
      O => pLD_22_IDELAY
    );
  pLD_22_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_22_SRMUXNOT
    );
  pLD_23_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_23_OUTMUX,
      CTL => pLD_23_ENABLE,
      O => pLD(23)
    );
  pLD_23_ENABLEINV : X_INV
    port map (
      I => pLD_23_TORGTS,
      O => pLD_23_ENABLE
    );
  pLD_23_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_23_TORGTS
    );
  pLD_23_OUTMUX_973 : X_BUF
    port map (
      I => LD_Out_23_GROM,
      O => pLD_23_OUTMUX
    );
  pLD_23_IMUX : X_BUF
    port map (
      I => pLD_23_IBUF,
      O => N49934
    );
  pLD_23_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(23),
      O => pLD_23_IBUF
    );
  pLD_23_DELAY : X_BUF
    port map (
      I => pLD_23_IBUF,
      O => pLD_23_IDELAY
    );
  pLD_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_23_SRMUXNOT
    );
  pLD_24_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_24_OUTMUX,
      CTL => pLD_24_ENABLE,
      O => pLD(24)
    );
  pLD_24_ENABLEINV : X_INV
    port map (
      I => pLD_24_TORGTS,
      O => pLD_24_ENABLE
    );
  pLD_24_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_24_TORGTS
    );
  pLD_24_OUTMUX_974 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_25_GROM,
      O => pLD_24_OUTMUX
    );
  pLD_24_IMUX : X_BUF
    port map (
      I => pLD_24_IBUF,
      O => N49938
    );
  pLD_24_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(24),
      O => pLD_24_IBUF
    );
  pLD_24_DELAY : X_BUF
    port map (
      I => pLD_24_IBUF,
      O => pLD_24_IDELAY
    );
  pLD_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_24_SRMUXNOT
    );
  pLD_25_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_25_OUTMUX,
      CTL => pLD_25_ENABLE,
      O => pLD(25)
    );
  pLD_25_ENABLEINV : X_INV
    port map (
      I => pLD_25_TORGTS,
      O => pLD_25_ENABLE
    );
  pLD_25_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_25_TORGTS
    );
  pLD_25_OUTMUX_975 : X_BUF
    port map (
      I => LD_Out_25_GROM,
      O => pLD_25_OUTMUX
    );
  pLD_25_IMUX : X_BUF
    port map (
      I => pLD_25_IBUF,
      O => N49940
    );
  pLD_25_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(25),
      O => pLD_25_IBUF
    );
  pLD_25_DELAY : X_BUF
    port map (
      I => pLD_25_IBUF,
      O => pLD_25_IDELAY
    );
  pLD_25_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_25_SRMUXNOT
    );
  pLD_26_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_26_OUTMUX,
      CTL => pLD_26_ENABLE,
      O => pLD(26)
    );
  pLD_26_ENABLEINV : X_INV
    port map (
      I => pLD_26_TORGTS,
      O => pLD_26_ENABLE
    );
  pLD_26_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_26_TORGTS
    );
  pLD_26_OUTMUX_976 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_27_GROM,
      O => pLD_26_OUTMUX
    );
  pLD_26_IMUX : X_BUF
    port map (
      I => pLD_26_IBUF,
      O => N49944
    );
  pLD_26_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(26),
      O => pLD_26_IBUF
    );
  pLD_26_DELAY : X_BUF
    port map (
      I => pLD_26_IBUF,
      O => pLD_26_IDELAY
    );
  pLD_26_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_26_SRMUXNOT
    );
  pLD_27_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_27_OUTMUX,
      CTL => pLD_27_ENABLE,
      O => pLD(27)
    );
  pLD_27_ENABLEINV : X_INV
    port map (
      I => pLD_27_TORGTS,
      O => pLD_27_ENABLE
    );
  pLD_27_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_27_TORGTS
    );
  pLD_27_OUTMUX_977 : X_BUF
    port map (
      I => LD_Out_27_GROM,
      O => pLD_27_OUTMUX
    );
  pLD_27_IMUX : X_BUF
    port map (
      I => pLD_27_IBUF,
      O => N49948
    );
  pLD_27_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(27),
      O => pLD_27_IBUF
    );
  pLD_27_DELAY : X_BUF
    port map (
      I => pLD_27_IBUF,
      O => pLD_27_IDELAY
    );
  pLD_27_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_27_SRMUXNOT
    );
  pLD_28_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_28_OUTMUX,
      CTL => pLD_28_ENABLE,
      O => pLD(28)
    );
  pLD_28_ENABLEINV : X_INV
    port map (
      I => pLD_28_TORGTS,
      O => pLD_28_ENABLE
    );
  pLD_28_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_28_TORGTS
    );
  pLD_28_OUTMUX_978 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_29_GROM,
      O => pLD_28_OUTMUX
    );
  pLD_28_IMUX : X_BUF
    port map (
      I => pLD_28_IBUF,
      O => N49950
    );
  pLD_28_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(28),
      O => pLD_28_IBUF
    );
  pLD_28_DELAY : X_BUF
    port map (
      I => pLD_28_IBUF,
      O => pLD_28_IDELAY
    );
  pLD_28_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_28_SRMUXNOT
    );
  pLD_29_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_29_OUTMUX,
      CTL => pLD_29_ENABLE,
      O => pLD(29)
    );
  pLD_29_ENABLEINV : X_INV
    port map (
      I => pLD_29_TORGTS,
      O => pLD_29_ENABLE
    );
  pLD_29_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_29_TORGTS
    );
  pLD_29_OUTMUX_979 : X_BUF
    port map (
      I => LD_Out_29_GROM,
      O => pLD_29_OUTMUX
    );
  pLD_29_IMUX : X_BUF
    port map (
      I => pLD_29_IBUF,
      O => N49952
    );
  pLD_29_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(29),
      O => pLD_29_IBUF
    );
  pLD_29_DELAY : X_BUF
    port map (
      I => pLD_29_IBUF,
      O => pLD_29_IDELAY
    );
  pLD_29_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_29_SRMUXNOT
    );
  pLD_2_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_2_OUTMUX,
      CTL => pLD_2_ENABLE,
      O => pLD(2)
    );
  pLD_2_ENABLEINV : X_INV
    port map (
      I => pLD_2_TORGTS,
      O => pLD_2_ENABLE
    );
  pLD_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_2_TORGTS
    );
  pLD_2_OUTMUX_980 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_3_GROM,
      O => pLD_2_OUTMUX
    );
  pLD_2_IMUX : X_BUF
    port map (
      I => pLD_2_IBUF,
      O => N49976
    );
  pLD_2_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(2),
      O => pLD_2_IBUF
    );
  pLD_2_DELAY : X_BUF
    port map (
      I => pLD_2_IBUF,
      O => pLD_2_IDELAY
    );
  pLD_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_2_SRMUXNOT
    );
  pLD_30_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_30_OUTMUX,
      CTL => pLD_30_ENABLE,
      O => pLD(30)
    );
  pLD_30_ENABLEINV : X_INV
    port map (
      I => pLD_30_TORGTS,
      O => pLD_30_ENABLE
    );
  pLD_30_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_30_TORGTS
    );
  pLD_30_OUTMUX_981 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_31_GROM,
      O => pLD_30_OUTMUX
    );
  pLD_30_IMUX : X_BUF
    port map (
      I => pLD_30_IBUF,
      O => N49942
    );
  pLD_30_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(30),
      O => pLD_30_IBUF
    );
  pLD_30_DELAY : X_BUF
    port map (
      I => pLD_30_IBUF,
      O => pLD_30_IDELAY
    );
  pLD_30_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_30_SRMUXNOT
    );
  pLD_31_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_31_OUTMUX,
      CTL => pLD_31_ENABLE,
      O => pLD(31)
    );
  pLD_31_ENABLEINV : X_INV
    port map (
      I => pLD_31_TORGTS,
      O => pLD_31_ENABLE
    );
  pLD_31_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_31_TORGTS
    );
  pLD_31_OUTMUX_982 : X_BUF
    port map (
      I => LD_Out_31_GROM,
      O => pLD_31_OUTMUX
    );
  pLD_31_IMUX : X_BUF
    port map (
      I => pLD_31_IBUF,
      O => N49946
    );
  pLD_31_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(31),
      O => pLD_31_IBUF
    );
  pLD_31_DELAY : X_BUF
    port map (
      I => pLD_31_IBUF,
      O => pLD_31_IDELAY
    );
  pLD_31_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_31_SRMUXNOT
    );
  pLD_3_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_3_OUTMUX,
      CTL => pLD_3_ENABLE,
      O => pLD(3)
    );
  pLD_3_ENABLEINV : X_INV
    port map (
      I => pLD_3_TORGTS,
      O => pLD_3_ENABLE
    );
  pLD_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_3_TORGTS
    );
  pLD_3_OUTMUX_983 : X_BUF
    port map (
      I => LD_Out_3_GROM,
      O => pLD_3_OUTMUX
    );
  pLD_3_IMUX : X_BUF
    port map (
      I => pLD_3_IBUF,
      O => N49982
    );
  pLD_3_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(3),
      O => pLD_3_IBUF
    );
  pLD_3_DELAY : X_BUF
    port map (
      I => pLD_3_IBUF,
      O => pLD_3_IDELAY
    );
  pLD_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_3_SRMUXNOT
    );
  pLD_4_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_4_OUTMUX,
      CTL => pLD_4_ENABLE,
      O => pLD(4)
    );
  pLD_4_ENABLEINV : X_INV
    port map (
      I => pLD_4_TORGTS,
      O => pLD_4_ENABLE
    );
  pLD_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_4_TORGTS
    );
  pLD_4_OUTMUX_984 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_5_GROM,
      O => pLD_4_OUTMUX
    );
  pLD_4_IMUX : X_BUF
    port map (
      I => pLD_4_IBUF,
      O => N49988
    );
  pLD_4_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(4),
      O => pLD_4_IBUF
    );
  pLD_4_DELAY : X_BUF
    port map (
      I => pLD_4_IBUF,
      O => pLD_4_IDELAY
    );
  pLD_4_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_4_SRMUXNOT
    );
  pLD_5_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_5_OUTMUX,
      CTL => pLD_5_ENABLE,
      O => pLD(5)
    );
  pLD_5_ENABLEINV : X_INV
    port map (
      I => pLD_5_TORGTS,
      O => pLD_5_ENABLE
    );
  pLD_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_5_TORGTS
    );
  pLD_5_OUTMUX_985 : X_BUF
    port map (
      I => LD_Out_5_GROM,
      O => pLD_5_OUTMUX
    );
  pLD_5_IMUX : X_BUF
    port map (
      I => pLD_5_IBUF,
      O => N49994
    );
  pLD_5_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(5),
      O => pLD_5_IBUF
    );
  pLD_5_DELAY : X_BUF
    port map (
      I => pLD_5_IBUF,
      O => pLD_5_IDELAY
    );
  pLD_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_5_SRMUXNOT
    );
  pLD_6_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_6_OUTMUX,
      CTL => pLD_6_ENABLE,
      O => pLD(6)
    );
  pLD_6_ENABLEINV : X_INV
    port map (
      I => pLD_6_TORGTS,
      O => pLD_6_ENABLE
    );
  pLD_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_6_TORGTS
    );
  pLD_6_OUTMUX_986 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_7_GROM,
      O => pLD_6_OUTMUX
    );
  pLD_6_IMUX : X_BUF
    port map (
      I => pLD_6_IBUF,
      O => N50002
    );
  pLD_6_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(6),
      O => pLD_6_IBUF
    );
  pLD_6_DELAY : X_BUF
    port map (
      I => pLD_6_IBUF,
      O => pLD_6_IDELAY
    );
  pLD_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_6_SRMUXNOT
    );
  pLD_7_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_7_OUTMUX,
      CTL => pLD_7_ENABLE,
      O => pLD(7)
    );
  pLD_7_ENABLEINV : X_INV
    port map (
      I => pLD_7_TORGTS,
      O => pLD_7_ENABLE
    );
  pLD_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_7_TORGTS
    );
  pLD_7_OUTMUX_987 : X_BUF
    port map (
      I => LD_Out_7_GROM,
      O => pLD_7_OUTMUX
    );
  pLD_7_IMUX : X_BUF
    port map (
      I => pLD_7_IBUF,
      O => N49886
    );
  pLD_7_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(7),
      O => pLD_7_IBUF
    );
  pLD_7_DELAY : X_BUF
    port map (
      I => pLD_7_IBUF,
      O => pLD_7_IDELAY
    );
  pLD_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_7_SRMUXNOT
    );
  pLD_8_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_8_OUTMUX,
      CTL => pLD_8_ENABLE,
      O => pLD(8)
    );
  pLD_8_ENABLEINV : X_INV
    port map (
      I => pLD_8_TORGTS,
      O => pLD_8_ENABLE
    );
  pLD_8_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_8_TORGTS
    );
  pLD_8_OUTMUX_988 : X_BUF
    port map (
      I => PerLBusInterface0_ReadRegData_9_GROM,
      O => pLD_8_OUTMUX
    );
  pLD_8_IMUX : X_BUF
    port map (
      I => pLD_8_IBUF,
      O => N49892
    );
  pLD_8_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(8),
      O => pLD_8_IBUF
    );
  pLD_8_DELAY : X_BUF
    port map (
      I => pLD_8_IBUF,
      O => pLD_8_IDELAY
    );
  pLD_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_8_SRMUXNOT
    );
  pLD_9_IOBUF_OBUFT : X_TRI
    port map (
      I => pLD_9_OUTMUX,
      CTL => pLD_9_ENABLE,
      O => pLD(9)
    );
  pLD_9_ENABLEINV : X_INV
    port map (
      I => pLD_9_TORGTS,
      O => pLD_9_ENABLE
    );
  pLD_9_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => I71_N4874,
      O => pLD_9_TORGTS
    );
  pLD_9_OUTMUX_989 : X_BUF
    port map (
      I => LD_Out_9_GROM,
      O => pLD_9_OUTMUX
    );
  pLD_9_IMUX : X_BUF
    port map (
      I => pLD_9_IBUF,
      O => N49898
    );
  pLD_9_IOBUF_IBUF : X_BUF
    port map (
      I => pLD(9),
      O => pLD_9_IBUF
    );
  pLD_9_DELAY : X_BUF
    port map (
      I => pLD_9_IBUF,
      O => pLD_9_IDELAY
    );
  pLD_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLD_9_SRMUXNOT
    );
  pLED_D8_OBUF : X_TRI
    port map (
      I => pLED_D8_OUTMUX,
      CTL => pLED_D8_ENABLE,
      O => pLED_D8
    );
  pLED_D8_ENABLEINV : X_INV
    port map (
      I => pLED_D8_TORGTS,
      O => pLED_D8_ENABLE
    );
  pLED_D8_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pLED_D8_TORGTS
    );
  pLED_D8_OUTMUX_990 : X_BUF
    port map (
      I => pLED_D8_ODNOT,
      O => pLED_D8_OUTMUX
    );
  pLED_D8_OMUX : X_INV
    port map (
      I => Sample2xClkValid,
      O => pLED_D8_ODNOT
    );
  pLED_D9_LOGIC_ONE_991 : X_ONE
    port map (
      O => pLED_D9_LOGIC_ONE
    );
  pLED_D9_OBUF_992 : X_TRI
    port map (
      I => pLED_D9_OUTMUX,
      CTL => pLED_D9_ENABLE,
      O => pLED_D9
    );
  pLED_D9_ENABLEINV : X_INV
    port map (
      I => pLED_D9_TORGTS,
      O => pLED_D9_ENABLE
    );
  pLED_D9_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pLED_D9_TORGTS
    );
  pLED_D9_OUTMUX_993 : X_BUF
    port map (
      I => pLED_D9_LOGIC_ONE,
      O => pLED_D9_OUTMUX
    );
  pLWnR_IBUF_994 : X_BUF
    port map (
      I => pLWnR,
      O => pLWnR_IBUF
    );
  pLWnR_DELAY : X_BUF
    port map (
      I => pLWnR_IBUF,
      O => pLWnR_IDELAY
    );
  pLWnR_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pLWnR_SRMUXNOT
    );
  pPIO_10_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_10_OUTMUX,
      CTL => pPIO_10_ENABLE,
      O => pPIO(10)
    );
  pPIO_10_ENABLEINV : X_INV
    port map (
      I => pPIO_10_TORGTS,
      O => pPIO_10_ENABLE
    );
  pPIO_10_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_10_TDATANOT,
      O => pPIO_10_TORGTS
    );
  pPIO_10_OUTMUX_995 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_10,
      O => pPIO_10_OUTMUX
    );
  pPIO_10_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_10,
      O => pPIO_10_TDATANOT
    );
  pPIO_10_OMUX : X_BUF
    port map (
      I => N49910,
      O => pPIO_10_OD
    );
  pPIO_10_IMUX : X_BUF
    port map (
      I => pPIO_10_IBUF,
      O => N49954
    );
  pPIO_10_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(10),
      O => pPIO_10_IBUF
    );
  pPIO_10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_10_SRMUXNOT
    );
  pPIO_11_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_11_OUTMUX,
      CTL => pPIO_11_ENABLE,
      O => pPIO(11)
    );
  pPIO_11_ENABLEINV : X_INV
    port map (
      I => pPIO_11_TORGTS,
      O => pPIO_11_ENABLE
    );
  pPIO_11_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_11_TDATANOT,
      O => pPIO_11_TORGTS
    );
  pPIO_11_OUTMUX_996 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_11,
      O => pPIO_11_OUTMUX
    );
  pPIO_11_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_11,
      O => pPIO_11_TDATANOT
    );
  pPIO_11_OMUX : X_BUF
    port map (
      I => N49912,
      O => pPIO_11_OD
    );
  pPIO_11_IMUX : X_BUF
    port map (
      I => pPIO_11_IBUF,
      O => N49956
    );
  pPIO_11_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(11),
      O => pPIO_11_IBUF
    );
  pPIO_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_11_SRMUXNOT
    );
  pPIO_12_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_12_OUTMUX,
      CTL => pPIO_12_ENABLE,
      O => pPIO(12)
    );
  pPIO_12_ENABLEINV : X_INV
    port map (
      I => pPIO_12_TORGTS,
      O => pPIO_12_ENABLE
    );
  pPIO_12_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_12_TDATANOT,
      O => pPIO_12_TORGTS
    );
  pPIO_12_OUTMUX_997 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_12,
      O => pPIO_12_OUTMUX
    );
  pPIO_12_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_12,
      O => pPIO_12_TDATANOT
    );
  pPIO_12_OMUX : X_BUF
    port map (
      I => N49914,
      O => pPIO_12_OD
    );
  pPIO_12_IMUX : X_BUF
    port map (
      I => pPIO_12_IBUF,
      O => N49958
    );
  pPIO_12_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(12),
      O => pPIO_12_IBUF
    );
  pPIO_12_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_12_SRMUXNOT
    );
  pPIO_13_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_13_OUTMUX,
      CTL => pPIO_13_ENABLE,
      O => pPIO(13)
    );
  pPIO_13_ENABLEINV : X_INV
    port map (
      I => pPIO_13_TORGTS,
      O => pPIO_13_ENABLE
    );
  pPIO_13_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_13_TDATANOT,
      O => pPIO_13_TORGTS
    );
  pPIO_13_OUTMUX_998 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_13,
      O => pPIO_13_OUTMUX
    );
  pPIO_13_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_13,
      O => pPIO_13_TDATANOT
    );
  pPIO_13_OMUX : X_BUF
    port map (
      I => N49916,
      O => pPIO_13_OD
    );
  pPIO_13_IMUX : X_BUF
    port map (
      I => pPIO_13_IBUF,
      O => N49960
    );
  pPIO_13_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(13),
      O => pPIO_13_IBUF
    );
  pPIO_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_13_SRMUXNOT
    );
  pPIO_14_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_14_OUTMUX,
      CTL => pPIO_14_ENABLE,
      O => pPIO(14)
    );
  pPIO_14_ENABLEINV : X_INV
    port map (
      I => pPIO_14_TORGTS,
      O => pPIO_14_ENABLE
    );
  pPIO_14_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_14_TDATANOT,
      O => pPIO_14_TORGTS
    );
  pPIO_14_OUTMUX_999 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_14,
      O => pPIO_14_OUTMUX
    );
  pPIO_14_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_14,
      O => pPIO_14_TDATANOT
    );
  pPIO_14_OMUX : X_BUF
    port map (
      I => N49918,
      O => pPIO_14_OD
    );
  pPIO_14_IMUX : X_BUF
    port map (
      I => pPIO_14_IBUF,
      O => N49962
    );
  pPIO_14_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(14),
      O => pPIO_14_IBUF
    );
  pPIO_14_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_14_SRMUXNOT
    );
  pPIO_15_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_15_OUTMUX,
      CTL => pPIO_15_ENABLE,
      O => pPIO(15)
    );
  pPIO_15_ENABLEINV : X_INV
    port map (
      I => pPIO_15_TORGTS,
      O => pPIO_15_ENABLE
    );
  pPIO_15_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_15_TDATANOT,
      O => pPIO_15_TORGTS
    );
  pPIO_15_OUTMUX_1000 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_15,
      O => pPIO_15_OUTMUX
    );
  pPIO_15_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_15,
      O => pPIO_15_TDATANOT
    );
  pPIO_15_IMUX : X_BUF
    port map (
      I => pPIO_15_IBUF,
      O => N49966
    );
  pPIO_15_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(15),
      O => pPIO_15_IBUF
    );
  pPIO_16_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_16_OUTMUX,
      CTL => pPIO_16_ENABLE,
      O => pPIO(16)
    );
  pPIO_16_ENABLEINV : X_INV
    port map (
      I => pPIO_16_TORGTS,
      O => pPIO_16_ENABLE
    );
  pPIO_16_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_16_TDATANOT,
      O => pPIO_16_TORGTS
    );
  pPIO_16_OUTMUX_1001 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_16,
      O => pPIO_16_OUTMUX
    );
  pPIO_16_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_16,
      O => pPIO_16_TDATANOT
    );
  pPIO_16_IMUX : X_BUF
    port map (
      I => pPIO_16_IBUF,
      O => N49972
    );
  pPIO_16_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(16),
      O => pPIO_16_IBUF
    );
  pPIO_17_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_17_OUTMUX,
      CTL => pPIO_17_ENABLE,
      O => pPIO(17)
    );
  pPIO_17_ENABLEINV : X_INV
    port map (
      I => pPIO_17_TORGTS,
      O => pPIO_17_ENABLE
    );
  pPIO_17_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_17_TDATANOT,
      O => pPIO_17_TORGTS
    );
  pPIO_17_OUTMUX_1002 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_17,
      O => pPIO_17_OUTMUX
    );
  pPIO_17_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_17,
      O => pPIO_17_TDATANOT
    );
  pPIO_17_IMUX : X_BUF
    port map (
      I => pPIO_17_IBUF,
      O => N49978
    );
  pPIO_17_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(17),
      O => pPIO_17_IBUF
    );
  pPIO_18_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_18_OUTMUX,
      CTL => pPIO_18_ENABLE,
      O => pPIO(18)
    );
  pPIO_18_ENABLEINV : X_INV
    port map (
      I => pPIO_18_TORGTS,
      O => pPIO_18_ENABLE
    );
  pPIO_18_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_18_TDATANOT,
      O => pPIO_18_TORGTS
    );
  pPIO_18_OUTMUX_1003 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_18,
      O => pPIO_18_OUTMUX
    );
  pPIO_18_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_18,
      O => pPIO_18_TDATANOT
    );
  pPIO_18_IMUX : X_BUF
    port map (
      I => pPIO_18_IBUF,
      O => N49984
    );
  pPIO_18_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(18),
      O => pPIO_18_IBUF
    );
  pPIO_19_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_19_OUTMUX,
      CTL => pPIO_19_ENABLE,
      O => pPIO(19)
    );
  pPIO_19_ENABLEINV : X_INV
    port map (
      I => pPIO_19_TORGTS,
      O => pPIO_19_ENABLE
    );
  pPIO_19_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_19_TDATANOT,
      O => pPIO_19_TORGTS
    );
  pPIO_19_OUTMUX_1004 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_19,
      O => pPIO_19_OUTMUX
    );
  pPIO_19_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_19,
      O => pPIO_19_TDATANOT
    );
  pPIO_19_IMUX : X_BUF
    port map (
      I => pPIO_19_IBUF,
      O => N49990
    );
  pPIO_19_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(19),
      O => pPIO_19_IBUF
    );
  pPIO_20_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_20_OUTMUX,
      CTL => pPIO_20_ENABLE,
      O => pPIO(20)
    );
  pPIO_20_ENABLEINV : X_INV
    port map (
      I => pPIO_20_TORGTS,
      O => pPIO_20_ENABLE
    );
  pPIO_20_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_20_TDATANOT,
      O => pPIO_20_TORGTS
    );
  pPIO_20_OUTMUX_1005 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_20,
      O => pPIO_20_OUTMUX
    );
  pPIO_20_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_20,
      O => pPIO_20_TDATANOT
    );
  pPIO_20_IMUX : X_BUF
    port map (
      I => pPIO_20_IBUF,
      O => N49968
    );
  pPIO_20_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(20),
      O => pPIO_20_IBUF
    );
  pPIO_21_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_21_OUTMUX,
      CTL => pPIO_21_ENABLE,
      O => pPIO(21)
    );
  pPIO_21_ENABLEINV : X_INV
    port map (
      I => pPIO_21_TORGTS,
      O => pPIO_21_ENABLE
    );
  pPIO_21_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_21_TDATANOT,
      O => pPIO_21_TORGTS
    );
  pPIO_21_OUTMUX_1006 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_21,
      O => pPIO_21_OUTMUX
    );
  pPIO_21_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_21,
      O => pPIO_21_TDATANOT
    );
  pPIO_21_IMUX : X_BUF
    port map (
      I => pPIO_21_IBUF,
      O => N49974
    );
  pPIO_21_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(21),
      O => pPIO_21_IBUF
    );
  pPIO_22_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_22_OUTMUX,
      CTL => pPIO_22_ENABLE,
      O => pPIO(22)
    );
  pPIO_22_ENABLEINV : X_INV
    port map (
      I => pPIO_22_TORGTS,
      O => pPIO_22_ENABLE
    );
  pPIO_22_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_22_TDATANOT,
      O => pPIO_22_TORGTS
    );
  pPIO_22_OUTMUX_1007 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_22,
      O => pPIO_22_OUTMUX
    );
  pPIO_22_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_22,
      O => pPIO_22_TDATANOT
    );
  pPIO_22_IMUX : X_BUF
    port map (
      I => pPIO_22_IBUF,
      O => N49980
    );
  pPIO_22_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(22),
      O => pPIO_22_IBUF
    );
  pPIO_23_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_23_OUTMUX,
      CTL => pPIO_23_ENABLE,
      O => pPIO(23)
    );
  pPIO_23_ENABLEINV : X_INV
    port map (
      I => pPIO_23_TORGTS,
      O => pPIO_23_ENABLE
    );
  pPIO_23_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_23_TDATANOT,
      O => pPIO_23_TORGTS
    );
  pPIO_23_OUTMUX_1008 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_23,
      O => pPIO_23_OUTMUX
    );
  pPIO_23_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_23,
      O => pPIO_23_TDATANOT
    );
  pPIO_23_OMUX : X_BUF
    port map (
      I => N49934,
      O => pPIO_23_OD
    );
  pPIO_23_IMUX : X_BUF
    port map (
      I => pPIO_23_IBUF,
      O => N49986
    );
  pPIO_23_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(23),
      O => pPIO_23_IBUF
    );
  pPIO_23_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_23_SRMUXNOT
    );
  pPIO_24_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_24_OUTMUX,
      CTL => pPIO_24_ENABLE,
      O => pPIO(24)
    );
  pPIO_24_ENABLEINV : X_INV
    port map (
      I => pPIO_24_TORGTS,
      O => pPIO_24_ENABLE
    );
  pPIO_24_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_24_TDATANOT,
      O => pPIO_24_TORGTS
    );
  pPIO_24_OUTMUX_1009 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_24,
      O => pPIO_24_OUTMUX
    );
  pPIO_24_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_24,
      O => pPIO_24_TDATANOT
    );
  pPIO_24_OMUX : X_BUF
    port map (
      I => N49938,
      O => pPIO_24_OD
    );
  pPIO_24_IMUX : X_BUF
    port map (
      I => pPIO_24_IBUF,
      O => N49992
    );
  pPIO_24_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(24),
      O => pPIO_24_IBUF
    );
  pPIO_24_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_24_SRMUXNOT
    );
  pPIO_25_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_25_OUTMUX,
      CTL => pPIO_25_ENABLE,
      O => pPIO(25)
    );
  pPIO_25_ENABLEINV : X_INV
    port map (
      I => pPIO_25_TORGTS,
      O => pPIO_25_ENABLE
    );
  pPIO_25_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_25_TDATANOT,
      O => pPIO_25_TORGTS
    );
  pPIO_25_OUTMUX_1010 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_25,
      O => pPIO_25_OUTMUX
    );
  pPIO_25_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_25,
      O => pPIO_25_TDATANOT
    );
  pPIO_25_IMUX : X_BUF
    port map (
      I => pPIO_25_IBUF,
      O => N49996
    );
  pPIO_25_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(25),
      O => pPIO_25_IBUF
    );
  pPIO_26_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_26_OUTMUX,
      CTL => pPIO_26_ENABLE,
      O => pPIO(26)
    );
  pPIO_26_ENABLEINV : X_INV
    port map (
      I => pPIO_26_TORGTS,
      O => pPIO_26_ENABLE
    );
  pPIO_26_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_26_TDATANOT,
      O => pPIO_26_TORGTS
    );
  pPIO_26_OUTMUX_1011 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_26,
      O => pPIO_26_OUTMUX
    );
  pPIO_26_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_26,
      O => pPIO_26_TDATANOT
    );
  pPIO_26_IMUX : X_BUF
    port map (
      I => pPIO_26_IBUF,
      O => N50004
    );
  pPIO_26_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(26),
      O => pPIO_26_IBUF
    );
  pPIO_27_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_27_OUTMUX,
      CTL => pPIO_27_ENABLE,
      O => pPIO(27)
    );
  pPIO_27_ENABLEINV : X_INV
    port map (
      I => pPIO_27_TORGTS,
      O => pPIO_27_ENABLE
    );
  pPIO_27_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_27_TDATANOT,
      O => pPIO_27_TORGTS
    );
  pPIO_27_OUTMUX_1012 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_27,
      O => pPIO_27_OUTMUX
    );
  pPIO_27_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_27,
      O => pPIO_27_TDATANOT
    );
  pPIO_27_IMUX : X_BUF
    port map (
      I => pPIO_27_IBUF,
      O => N49888
    );
  pPIO_27_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(27),
      O => pPIO_27_IBUF
    );
  pPIO_28_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_28_OUTMUX,
      CTL => pPIO_28_ENABLE,
      O => pPIO(28)
    );
  pPIO_28_ENABLEINV : X_INV
    port map (
      I => pPIO_28_TORGTS,
      O => pPIO_28_ENABLE
    );
  pPIO_28_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_28_TDATANOT,
      O => pPIO_28_TORGTS
    );
  pPIO_28_OUTMUX_1013 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_28,
      O => pPIO_28_OUTMUX
    );
  pPIO_28_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_28,
      O => pPIO_28_TDATANOT
    );
  pPIO_28_IMUX : X_BUF
    port map (
      I => pPIO_28_IBUF,
      O => N49894
    );
  pPIO_28_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(28),
      O => pPIO_28_IBUF
    );
  pPIO_29_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_29_OUTMUX,
      CTL => pPIO_29_ENABLE,
      O => pPIO(29)
    );
  pPIO_29_ENABLEINV : X_INV
    port map (
      I => pPIO_29_TORGTS,
      O => pPIO_29_ENABLE
    );
  pPIO_29_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_29_TDATANOT,
      O => pPIO_29_TORGTS
    );
  pPIO_29_OUTMUX_1014 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_29,
      O => pPIO_29_OUTMUX
    );
  pPIO_29_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_29,
      O => pPIO_29_TDATANOT
    );
  pPIO_29_IMUX : X_BUF
    port map (
      I => pPIO_29_IBUF,
      O => N49900
    );
  pPIO_29_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(29),
      O => pPIO_29_IBUF
    );
  pPIO_2_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_2_OUTMUX,
      CTL => pPIO_2_ENABLE,
      O => pPIO(2)
    );
  pPIO_2_ENABLEINV : X_INV
    port map (
      I => pPIO_2_TORGTS,
      O => pPIO_2_ENABLE
    );
  pPIO_2_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_2_TDATANOT,
      O => pPIO_2_TORGTS
    );
  pPIO_2_OUTMUX_1015 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_2,
      O => pPIO_2_OUTMUX
    );
  pPIO_2_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_2,
      O => pPIO_2_TDATANOT
    );
  pPIO_2_IMUX : X_BUF
    port map (
      I => pPIO_2_IBUF,
      O => N50000
    );
  pPIO_2_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(2),
      O => pPIO_2_IBUF
    );
  pPIO_30_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_30_OUTMUX,
      CTL => pPIO_30_ENABLE,
      O => pPIO(30)
    );
  pPIO_30_ENABLEINV : X_INV
    port map (
      I => pPIO_30_TORGTS,
      O => pPIO_30_ENABLE
    );
  pPIO_30_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_30_TDATANOT,
      O => pPIO_30_TORGTS
    );
  pPIO_30_OUTMUX_1016 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_30,
      O => pPIO_30_OUTMUX
    );
  pPIO_30_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_30,
      O => pPIO_30_TDATANOT
    );
  pPIO_30_IMUX : X_BUF
    port map (
      I => pPIO_30_IBUF,
      O => N49998
    );
  pPIO_30_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(30),
      O => pPIO_30_IBUF
    );
  pPIO_31_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_31_OUTMUX,
      CTL => pPIO_31_ENABLE,
      O => pPIO(31)
    );
  pPIO_31_ENABLEINV : X_INV
    port map (
      I => pPIO_31_TORGTS,
      O => pPIO_31_ENABLE
    );
  pPIO_31_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_31_TDATANOT,
      O => pPIO_31_TORGTS
    );
  pPIO_31_OUTMUX_1017 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_31,
      O => pPIO_31_OUTMUX
    );
  pPIO_31_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_31,
      O => pPIO_31_TDATANOT
    );
  pPIO_31_IMUX : X_BUF
    port map (
      I => pPIO_31_IBUF,
      O => N50006
    );
  pPIO_31_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(31),
      O => pPIO_31_IBUF
    );
  pPIO_3_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_3_OUTMUX,
      CTL => pPIO_3_ENABLE,
      O => pPIO(3)
    );
  pPIO_3_ENABLEINV : X_INV
    port map (
      I => pPIO_3_TORGTS,
      O => pPIO_3_ENABLE
    );
  pPIO_3_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_3_TDATANOT,
      O => pPIO_3_TORGTS
    );
  pPIO_3_OUTMUX_1018 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_3,
      O => pPIO_3_OUTMUX
    );
  pPIO_3_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_3,
      O => pPIO_3_TDATANOT
    );
  pPIO_3_IMUX : X_BUF
    port map (
      I => pPIO_3_IBUF,
      O => N49884
    );
  pPIO_3_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(3),
      O => pPIO_3_IBUF
    );
  pPIO_4_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_4_OUTMUX,
      CTL => pPIO_4_ENABLE,
      O => pPIO(4)
    );
  pPIO_4_ENABLEINV : X_INV
    port map (
      I => pPIO_4_TORGTS,
      O => pPIO_4_ENABLE
    );
  pPIO_4_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_4_TDATANOT,
      O => pPIO_4_TORGTS
    );
  pPIO_4_OUTMUX_1019 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_4,
      O => pPIO_4_OUTMUX
    );
  pPIO_4_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_4,
      O => pPIO_4_TDATANOT
    );
  pPIO_4_IMUX : X_BUF
    port map (
      I => pPIO_4_IBUF,
      O => N49890
    );
  pPIO_4_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(4),
      O => pPIO_4_IBUF
    );
  pPIO_5_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_5_OUTMUX,
      CTL => pPIO_5_ENABLE,
      O => pPIO(5)
    );
  pPIO_5_ENABLEINV : X_INV
    port map (
      I => pPIO_5_TORGTS,
      O => pPIO_5_ENABLE
    );
  pPIO_5_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_5_TDATANOT,
      O => pPIO_5_TORGTS
    );
  pPIO_5_OUTMUX_1020 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_5,
      O => pPIO_5_OUTMUX
    );
  pPIO_5_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_5,
      O => pPIO_5_TDATANOT
    );
  pPIO_5_IMUX : X_BUF
    port map (
      I => pPIO_5_IBUF,
      O => N49896
    );
  pPIO_5_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(5),
      O => pPIO_5_IBUF
    );
  pPIO_6_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_6_OUTMUX,
      CTL => pPIO_6_ENABLE,
      O => pPIO(6)
    );
  pPIO_6_ENABLEINV : X_INV
    port map (
      I => pPIO_6_TORGTS,
      O => pPIO_6_ENABLE
    );
  pPIO_6_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_6_TDATANOT,
      O => pPIO_6_TORGTS
    );
  pPIO_6_OUTMUX_1021 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_6,
      O => pPIO_6_OUTMUX
    );
  pPIO_6_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_6,
      O => pPIO_6_TDATANOT
    );
  pPIO_6_OMUX : X_BUF
    port map (
      I => N50002,
      O => pPIO_6_OD
    );
  pPIO_6_IMUX : X_BUF
    port map (
      I => pPIO_6_IBUF,
      O => N49902
    );
  pPIO_6_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(6),
      O => pPIO_6_IBUF
    );
  pPIO_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_6_SRMUXNOT
    );
  pPIO_7_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_7_OUTMUX,
      CTL => pPIO_7_ENABLE,
      O => pPIO(7)
    );
  pPIO_7_ENABLEINV : X_INV
    port map (
      I => pPIO_7_TORGTS,
      O => pPIO_7_ENABLE
    );
  pPIO_7_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_7_TDATANOT,
      O => pPIO_7_TORGTS
    );
  pPIO_7_OUTMUX_1022 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_7,
      O => pPIO_7_OUTMUX
    );
  pPIO_7_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_7,
      O => pPIO_7_TDATANOT
    );
  pPIO_7_OMUX : X_BUF
    port map (
      I => N49886,
      O => pPIO_7_OD
    );
  pPIO_7_IMUX : X_BUF
    port map (
      I => pPIO_7_IBUF,
      O => N49904
    );
  pPIO_7_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(7),
      O => pPIO_7_IBUF
    );
  pPIO_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_7_SRMUXNOT
    );
  pPIO_8_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_8_OUTMUX,
      CTL => pPIO_8_ENABLE,
      O => pPIO(8)
    );
  pPIO_8_ENABLEINV : X_INV
    port map (
      I => pPIO_8_TORGTS,
      O => pPIO_8_ENABLE
    );
  pPIO_8_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_8_TDATANOT,
      O => pPIO_8_TORGTS
    );
  pPIO_8_OUTMUX_1023 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_8,
      O => pPIO_8_OUTMUX
    );
  pPIO_8_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_8,
      O => pPIO_8_TDATANOT
    );
  pPIO_8_OMUX : X_BUF
    port map (
      I => N49892,
      O => pPIO_8_OD
    );
  pPIO_8_IMUX : X_BUF
    port map (
      I => pPIO_8_IBUF,
      O => N49906
    );
  pPIO_8_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(8),
      O => pPIO_8_IBUF
    );
  pPIO_8_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_8_SRMUXNOT
    );
  pPIO_9_IOBUF_OBUFT : X_TRI
    port map (
      I => pPIO_9_OUTMUX,
      CTL => pPIO_9_ENABLE,
      O => pPIO(9)
    );
  pPIO_9_ENABLEINV : X_INV
    port map (
      I => pPIO_9_TORGTS,
      O => pPIO_9_ENABLE
    );
  pPIO_9_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pPIO_9_TDATANOT,
      O => pPIO_9_TORGTS
    );
  pPIO_9_OUTMUX_1024 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_17_9,
      O => pPIO_9_OUTMUX
    );
  pPIO_9_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_18_9,
      O => pPIO_9_TDATANOT
    );
  pPIO_9_OMUX : X_BUF
    port map (
      I => N49898,
      O => pPIO_9_OD
    );
  pPIO_9_IMUX : X_BUF
    port map (
      I => pPIO_9_IBUF,
      O => N49908
    );
  pPIO_9_IOBUF_IBUF : X_BUF
    port map (
      I => pPIO(9),
      O => pPIO_9_IBUF
    );
  pPIO_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pPIO_9_SRMUXNOT
    );
  pPORT_FORMAT_OBUF : X_TRI
    port map (
      I => pPORT_FORMAT_OUTMUX,
      CTL => pPORT_FORMAT_ENABLE,
      O => pPORT_FORMAT
    );
  pPORT_FORMAT_ENABLEINV : X_INV
    port map (
      I => pPORT_FORMAT_TORGTS,
      O => pPORT_FORMAT_ENABLE
    );
  pPORT_FORMAT_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pPORT_FORMAT_TORGTS
    );
  pPORT_FORMAT_OUTMUX_1025 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_12_1,
      O => pPORT_FORMAT_OUTMUX
    );
  pProbeAper_0_OBUF : X_TRI
    port map (
      I => pProbeAper_0_OUTMUX,
      CTL => pProbeAper_0_ENABLE,
      O => pProbeAper(0)
    );
  pProbeAper_0_ENABLEINV : X_INV
    port map (
      I => pProbeAper_0_TORGTS,
      O => pProbeAper_0_ENABLE
    );
  pProbeAper_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeAper_0_TORGTS
    );
  pProbeAper_0_OUTMUX_1026 : X_BUF
    port map (
      I => pProbeAper_1_OBUF_GROM,
      O => pProbeAper_0_OUTMUX
    );
  pProbeAper_1_OBUF : X_TRI
    port map (
      I => pProbeAper_1_OUTMUX,
      CTL => pProbeAper_1_ENABLE,
      O => pProbeAper(1)
    );
  pProbeAper_1_ENABLEINV : X_INV
    port map (
      I => pProbeAper_1_TORGTS,
      O => pProbeAper_1_ENABLE
    );
  pProbeAper_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeAper_1_TORGTS
    );
  pProbeAper_1_OUTMUX_1027 : X_BUF
    port map (
      I => pProbeAper_1_OBUF_FROM,
      O => pProbeAper_1_OUTMUX
    );
  Mmux_pProbeAper_Result_1_1 : X_LUT4
    generic map(
      INIT => X"AA00"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_19_9_Q,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_FocusWrite,
      O => pProbeAper_1_OBUF_FROM
    );
  Mmux_pProbeAper_Result_0_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusWrite,
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_19_8_Q,
      ADR3 => FocusUnitCtrl0_pProbeCtrl_0_Q,
      O => pProbeAper_1_OBUF_GROM
    );
  pProbeDClk_OBUF : X_TRI
    port map (
      I => pProbeDClk_OUTMUX,
      CTL => pProbeDClk_ENABLE,
      O => pProbeDClk
    );
  pProbeDClk_ENABLEINV : X_INV
    port map (
      I => pProbeDClk_TORGTS,
      O => pProbeDClk_ENABLE
    );
  pProbeDClk_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeDClk_TORGTS
    );
  pProbeDClk_OUTMUX_1028 : X_BUF
    port map (
      I => PerLBusInterface0_FocusWrite_FROM,
      O => pProbeDClk_OUTMUX
    );
  pProbeDSel_OBUF : X_TRI
    port map (
      I => pProbeDSel_OUTMUX,
      CTL => pProbeDSel_ENABLE,
      O => pProbeDSel
    );
  pProbeDSel_ENABLEINV : X_INV
    port map (
      I => pProbeDSel_TORGTS,
      O => pProbeDSel_ENABLE
    );
  pProbeDSel_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeDSel_TORGTS
    );
  pProbeDSel_OUTMUX_1029 : X_BUF
    port map (
      I => PerLBusInterface0_FocusWrite_GROM,
      O => pProbeDSel_OUTMUX
    );
  pProbeData_0_OBUF : X_TRI
    port map (
      I => pProbeData_0_OUTMUX,
      CTL => pProbeData_0_ENABLE,
      O => pProbeData(0)
    );
  pProbeData_0_ENABLEINV : X_INV
    port map (
      I => pProbeData_0_TORGTS,
      O => pProbeData_0_ENABLE
    );
  pProbeData_0_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_0_TORGTS
    );
  pProbeData_0_OUTMUX_1030 : X_BUF
    port map (
      I => pProbeData_7_OBUF_GROM,
      O => pProbeData_0_OUTMUX
    );
  pProbeData_1_OBUF : X_TRI
    port map (
      I => pProbeData_1_OUTMUX,
      CTL => pProbeData_1_ENABLE,
      O => pProbeData(1)
    );
  pProbeData_1_ENABLEINV : X_INV
    port map (
      I => pProbeData_1_TORGTS,
      O => pProbeData_1_ENABLE
    );
  pProbeData_1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_1_TORGTS
    );
  pProbeData_1_OUTMUX_1031 : X_BUF
    port map (
      I => pProbeData_6_OBUF_GROM,
      O => pProbeData_1_OUTMUX
    );
  pProbeData_2_OBUF : X_TRI
    port map (
      I => pProbeData_2_OUTMUX,
      CTL => pProbeData_2_ENABLE,
      O => pProbeData(2)
    );
  pProbeData_2_ENABLEINV : X_INV
    port map (
      I => pProbeData_2_TORGTS,
      O => pProbeData_2_ENABLE
    );
  pProbeData_2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_2_TORGTS
    );
  pProbeData_2_OUTMUX_1032 : X_BUF
    port map (
      I => pProbeData_5_OBUF_GROM,
      O => pProbeData_2_OUTMUX
    );
  pProbeData_3_OBUF : X_TRI
    port map (
      I => pProbeData_3_OUTMUX,
      CTL => pProbeData_3_ENABLE,
      O => pProbeData(3)
    );
  pProbeData_3_ENABLEINV : X_INV
    port map (
      I => pProbeData_3_TORGTS,
      O => pProbeData_3_ENABLE
    );
  pProbeData_3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_3_TORGTS
    );
  pProbeData_3_OUTMUX_1033 : X_BUF
    port map (
      I => pProbeData_4_OBUF_GROM,
      O => pProbeData_3_OUTMUX
    );
  pProbeData_4_OBUF : X_TRI
    port map (
      I => pProbeData_4_OUTMUX,
      CTL => pProbeData_4_ENABLE,
      O => pProbeData(4)
    );
  pProbeData_4_ENABLEINV : X_INV
    port map (
      I => pProbeData_4_TORGTS,
      O => pProbeData_4_ENABLE
    );
  pProbeData_4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_4_TORGTS
    );
  pProbeData_4_OUTMUX_1034 : X_BUF
    port map (
      I => pProbeData_4_OBUF_FROM,
      O => pProbeData_4_OUTMUX
    );
  pProbeData_5_OBUF : X_TRI
    port map (
      I => pProbeData_5_OUTMUX,
      CTL => pProbeData_5_ENABLE,
      O => pProbeData(5)
    );
  pProbeData_5_ENABLEINV : X_INV
    port map (
      I => pProbeData_5_TORGTS,
      O => pProbeData_5_ENABLE
    );
  pProbeData_5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_5_TORGTS
    );
  pProbeData_5_OUTMUX_1035 : X_BUF
    port map (
      I => pProbeData_5_OBUF_FROM,
      O => pProbeData_5_OUTMUX
    );
  pProbeData_6_OBUF : X_TRI
    port map (
      I => pProbeData_6_OUTMUX,
      CTL => pProbeData_6_ENABLE,
      O => pProbeData(6)
    );
  pProbeData_6_ENABLEINV : X_INV
    port map (
      I => pProbeData_6_TORGTS,
      O => pProbeData_6_ENABLE
    );
  pProbeData_6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_6_TORGTS
    );
  pProbeData_6_OUTMUX_1036 : X_BUF
    port map (
      I => pProbeData_6_OBUF_FROM,
      O => pProbeData_6_OUTMUX
    );
  pProbeData_7_OBUF : X_TRI
    port map (
      I => pProbeData_7_OUTMUX,
      CTL => pProbeData_7_ENABLE,
      O => pProbeData(7)
    );
  pProbeData_7_ENABLEINV : X_INV
    port map (
      I => pProbeData_7_TORGTS,
      O => pProbeData_7_ENABLE
    );
  pProbeData_7_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeData_7_TORGTS
    );
  pProbeData_7_OUTMUX_1037 : X_BUF
    port map (
      I => pProbeData_7_OBUF_FROM,
      O => pProbeData_7_OUTMUX
    );
  Mmux_pProbeData_Result_4_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => PerLBusInterface0_FocusWrite,
      ADR1 => PerLBusInterface0_RegBank_19_4_Q,
      ADR2 => VCC,
      ADR3 => FocusUnitCtrl0_pProbeData(4),
      O => pProbeData_4_OBUF_FROM
    );
  Mmux_pProbeData_Result_3_1 : X_LUT4
    generic map(
      INIT => X"F0CC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => FocusUnitCtrl0_pProbeData(3),
      ADR2 => PerLBusInterface0_RegBank_19_3_Q,
      ADR3 => PerLBusInterface0_FocusWrite,
      O => pProbeData_4_OBUF_GROM
    );
  Mmux_pProbeData_Result_5_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_19_5_Q,
      ADR1 => FocusUnitCtrl0_pProbeData(5),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_FocusWrite,
      O => pProbeData_5_OBUF_FROM
    );
  Mmux_pProbeData_Result_2_1 : X_LUT4
    generic map(
      INIT => X"FA0A"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeData(2),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_FocusWrite,
      ADR3 => PerLBusInterface0_RegBank_19_2_Q,
      O => pProbeData_5_OBUF_GROM
    );
  Mmux_pProbeData_Result_6_1 : X_LUT4
    generic map(
      INIT => X"ACAC"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_19_6_Q,
      ADR1 => FocusUnitCtrl0_pProbeData(6),
      ADR2 => PerLBusInterface0_FocusWrite,
      ADR3 => VCC,
      O => pProbeData_6_OBUF_FROM
    );
  Mmux_pProbeData_Result_1_1 : X_LUT4
    generic map(
      INIT => X"EE22"
    )
    port map (
      ADR0 => FocusUnitCtrl0_pProbeData(1),
      ADR1 => PerLBusInterface0_FocusWrite,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_19_1_Q,
      O => pProbeData_6_OBUF_GROM
    );
  Mmux_pProbeData_Result_7_1 : X_LUT4
    generic map(
      INIT => X"B8B8"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_19_7_Q,
      ADR1 => PerLBusInterface0_FocusWrite,
      ADR2 => FocusUnitCtrl0_pProbeData(7),
      ADR3 => VCC,
      O => pProbeData_7_OBUF_FROM
    );
  Mmux_pProbeData_Result_0_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_FocusWrite,
      ADR2 => FocusUnitCtrl0_pProbeData(0),
      ADR3 => PerLBusInterface0_RegBank_19_0_Q,
      O => pProbeData_7_OBUF_GROM
    );
  pProbeSense_IMUX : X_BUF
    port map (
      I => pProbeSense_IBUF_14,
      O => pProbeSense_IBUF
    );
  pProbeSense_IBUF_1038 : X_BUF
    port map (
      I => pProbeSense,
      O => pProbeSense_IBUF_14
    );
  pProbeTx_OBUF : X_TRI
    port map (
      I => pProbeTx_OUTMUX,
      CTL => pProbeTx_ENABLE,
      O => pProbeTx
    );
  pProbeTx_ENABLEINV : X_INV
    port map (
      I => pProbeTx_TORGTS,
      O => pProbeTx_ENABLE
    );
  pProbeTx_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pProbeTx_TORGTS
    );
  pProbeTx_OUTMUX_1039 : X_BUF
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_pStrobeOut,
      O => pProbeTx_OUTMUX
    );
  pSEL_1M_50R_OBUF : X_TRI
    port map (
      I => pSEL_1M_50R_OUTMUX,
      CTL => pSEL_1M_50R_ENABLE,
      O => pSEL_1M_50R
    );
  pSEL_1M_50R_ENABLEINV : X_INV
    port map (
      I => pSEL_1M_50R_TORGTS,
      O => pSEL_1M_50R_ENABLE
    );
  pSEL_1M_50R_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pSEL_1M_50R_TORGTS
    );
  pSEL_1M_50R_OUTMUX_1040 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_1_1,
      O => pSEL_1M_50R_OUTMUX
    );
  pSEL_AC_DC_OBUF : X_TRI
    port map (
      I => pSEL_AC_DC_OUTMUX,
      CTL => pSEL_AC_DC_ENABLE,
      O => pSEL_AC_DC
    );
  pSEL_AC_DC_ENABLEINV : X_INV
    port map (
      I => pSEL_AC_DC_TORGTS,
      O => pSEL_AC_DC_ENABLE
    );
  pSEL_AC_DC_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pSEL_AC_DC_TORGTS
    );
  pSEL_AC_DC_OUTMUX_1041 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_0_0_1,
      O => pSEL_AC_DC_OUTMUX
    );
  pSEL_AC_DC_OMUX : X_BUF
    port map (
      I => N49964,
      O => pSEL_AC_DC_OD
    );
  pSEL_AC_DC_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pSEL_AC_DC_SRMUXNOT
    );
  pSENSE_LOGIC_ONE_1042 : X_ONE
    port map (
      O => pSENSE_LOGIC_ONE
    );
  pSENSE_OBUFT : X_TRI
    port map (
      I => pSENSE_OUTMUX,
      CTL => pSENSE_ENABLE,
      O => pSENSE
    );
  pSENSE_ENABLEINV : X_INV
    port map (
      I => pSENSE_TORGTS,
      O => pSENSE_ENABLE
    );
  pSENSE_GTS_OR : X_OR2
    port map (
      I0 => GTS,
      I1 => pSENSE_TDATANOT,
      O => pSENSE_TORGTS
    );
  pSENSE_OUTMUX_1043 : X_BUF
    port map (
      I => pSENSE_LOGIC_ONE,
      O => pSENSE_OUTMUX
    );
  pSENSE_TRIMUX : X_INV
    port map (
      I => PerLBusInterface0_RegBank_0_15,
      O => pSENSE_TDATANOT
    );
  pZ0_IMUX : X_BUF
    port map (
      I => pZ0_IBUF_15,
      O => pZ0_IBUF
    );
  pZ0_IBUF_1044 : X_BUF
    port map (
      I => pZ0,
      O => pZ0_IBUF_15
    );
  OFD4_OBUF : X_TRI
    port map (
      I => pZ1_OUTMUX,
      CTL => pZ1_ENABLE,
      O => pZ1
    );
  pZ1_ENABLEINV : X_INV
    port map (
      I => pZ1_TORGTS,
      O => pZ1_ENABLE
    );
  pZ1_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ1_TORGTS
    );
  pZ1_OUTMUX_1045 : X_BUF
    port map (
      I => OFD4_QBUF,
      O => pZ1_OUTMUX
    );
  pZ1_OMUX : X_BUF
    port map (
      I => EncoderMonitor0_pSerialOutEn,
      O => pZ1_OD
    );
  pZ10_OBUF : X_TRI
    port map (
      I => pZ10_OUTMUX,
      CTL => pZ10_ENABLE,
      O => pZ10
    );
  pZ10_ENABLEINV : X_INV
    port map (
      I => pZ10_TORGTS,
      O => pZ10_ENABLE
    );
  pZ10_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ10_TORGTS
    );
  pZ10_OUTMUX_1046 : X_BUF
    port map (
      I => TriggerDelay0_OutShifter(2),
      O => pZ10_OUTMUX
    );
  pZ10_OMUX : X_BUF
    port map (
      I => TriggerDelay0_n0038_2_GROM,
      O => pZ10_OD
    );
  pZ10_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pZ10_SRMUXNOT
    );
  pZ11_OBUF : X_TRI
    port map (
      I => pZ11_OUTMUX,
      CTL => pZ11_ENABLE,
      O => pZ11
    );
  pZ11_ENABLEINV : X_INV
    port map (
      I => pZ11_TORGTS,
      O => pZ11_ENABLE
    );
  pZ11_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ11_TORGTS
    );
  pZ11_OUTMUX_1047 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_1_16_1,
      O => pZ11_OUTMUX
    );
  pZ11_OMUX : X_BUF
    port map (
      I => N49924,
      O => pZ11_OD
    );
  pZ11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => pZ11_SRMUXNOT
    );
  OFD5_OBUF : X_TRI
    port map (
      I => pZ2_OUTMUX,
      CTL => pZ2_ENABLE,
      O => pZ2
    );
  pZ2_ENABLEINV : X_INV
    port map (
      I => pZ2_TORGTS,
      O => pZ2_ENABLE
    );
  pZ2_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ2_TORGTS
    );
  pZ2_OUTMUX_1048 : X_BUF
    port map (
      I => OFD5_QBUF,
      O => pZ2_OUTMUX
    );
  pZ2_OMUX : X_BUF
    port map (
      I => EncoderMonitor0_pSerialOut,
      O => pZ2_OD
    );
  OFD6_OBUF : X_TRI
    port map (
      I => pZ3_OUTMUX,
      CTL => pZ3_ENABLE,
      O => pZ3
    );
  pZ3_ENABLEINV : X_INV
    port map (
      I => pZ3_TORGTS,
      O => pZ3_ENABLE
    );
  pZ3_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ3_TORGTS
    );
  pZ3_OUTMUX_1049 : X_BUF
    port map (
      I => OFD6_QBUF,
      O => pZ3_OUTMUX
    );
  pZ3_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataOut,
      O => pZ3_OD
    );
  OFD7_OBUF : X_TRI
    port map (
      I => pZ4_OUTMUX,
      CTL => pZ4_ENABLE,
      O => pZ4
    );
  pZ4_ENABLEINV : X_INV
    port map (
      I => pZ4_TORGTS,
      O => pZ4_ENABLE
    );
  pZ4_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ4_TORGTS
    );
  pZ4_OUTMUX_1050 : X_BUF
    port map (
      I => OFD7_QBUF,
      O => pZ4_OUTMUX
    );
  pZ4_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataEn,
      O => pZ4_OD
    );
  OFD8_OBUF : X_TRI
    port map (
      I => pZ5_OUTMUX,
      CTL => pZ5_ENABLE,
      O => pZ5
    );
  pZ5_ENABLEINV : X_INV
    port map (
      I => pZ5_TORGTS,
      O => pZ5_ENABLE
    );
  pZ5_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ5_TORGTS
    );
  pZ5_OUTMUX_1051 : X_BUF
    port map (
      I => OFD8_QBUF,
      O => pZ5_OUTMUX
    );
  pZ5_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataSel(0),
      O => pZ5_OD
    );
  OFD9_OBUF : X_TRI
    port map (
      I => pZ6_OUTMUX,
      CTL => pZ6_ENABLE,
      O => pZ6
    );
  pZ6_ENABLEINV : X_INV
    port map (
      I => pZ6_TORGTS,
      O => pZ6_ENABLE
    );
  pZ6_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ6_TORGTS
    );
  pZ6_OUTMUX_1052 : X_BUF
    port map (
      I => OFD9_QBUF,
      O => pZ6_OUTMUX
    );
  pZ6_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataSel(1),
      O => pZ6_OD
    );
  OFD10_OBUF : X_TRI
    port map (
      I => pZ7_OUTMUX,
      CTL => pZ7_ENABLE,
      O => pZ7
    );
  pZ7_ENABLEINV : X_INV
    port map (
      I => pZ7_TORGTS,
      O => pZ7_ENABLE
    );
  pZ7_GTS_OR : X_BUF
    port map (
      I => GTS,
      O => pZ7_TORGTS
    );
  pZ7_OUTMUX_1053 : X_BUF
    port map (
      I => OFD10_QBUF,
      O => pZ7_OUTMUX
    );
  pZ7_OMUX : X_BUF
    port map (
      I => PerLBusInterface0_pGateDataSel(2),
      O => pZ7_OD
    );
  pZ9_IMUX : X_BUF
    port map (
      I => pZ9_IBUF_16,
      O => pZ9_IBUF
    );
  pZ9_IBUF_1054 : X_BUF
    port map (
      I => pZ9,
      O => pZ9_IBUF_16
    );
  pnFpgaCs_IMUX : X_BUF
    port map (
      I => pnFpgaCs_IBUF_17,
      O => pnFpgaCs_IBUF
    );
  pnFpgaCs_IBUF_1055 : X_BUF
    port map (
      I => pnFpgaCs,
      O => pnFpgaCs_IBUF_17
    );
  pnLReset_IMUX : X_BUF
    port map (
      I => pnLReset_IBUF_18,
      O => pnLReset_IBUF
    );
  pnLReset_IBUF_1056 : X_BUF
    port map (
      I => pnLReset,
      O => pnLReset_IBUF_18
    );
  EncoderMonitor0_SerialResults_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0085,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_29_FFX_RST,
      O => EncoderMonitor0_SerialResults(29)
    );
  EncoderMonitor0_SerialResults_29_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_29_FFX_RST
    );
  EncoderMonitor0_SerialResults_149 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0221,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_149_FFX_RST,
      O => EncoderMonitor0_SerialResults(149)
    );
  EncoderMonitor0_SerialResults_149_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_149_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_149_FFX_RST
    );
  EncoderMonitor0_SerialResults_150 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0220,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_150_FFY_RST,
      O => EncoderMonitor0_SerialResults(150)
    );
  EncoderMonitor0_SerialResults_150_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_150_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_150_FFY_RST
    );
  EncoderMonitor0_SerialResults_143 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0227,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_143_FFX_RST,
      O => EncoderMonitor0_SerialResults(143)
    );
  EncoderMonitor0_SerialResults_143_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_143_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_143_FFX_RST
    );
  EncoderMonitor0_SerialResults_146 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0224,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_147_FFY_RST,
      O => EncoderMonitor0_SerialResults(146)
    );
  EncoderMonitor0_SerialResults_147_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_147_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_147_FFY_RST
    );
  EncoderMonitor0_SerialResults_147 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0223,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_147_FFX_RST,
      O => EncoderMonitor0_SerialResults(147)
    );
  EncoderMonitor0_SerialResults_147_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_147_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_147_FFX_RST
    );
  EncoderMonitor0_SerialResults_148 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0222,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_149_FFY_RST,
      O => EncoderMonitor0_SerialResults(148)
    );
  EncoderMonitor0_SerialResults_149_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_149_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_149_FFY_RST
    );
  EncoderMonitor0_SerialResults_145 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0225,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_145_FFX_RST,
      O => EncoderMonitor0_SerialResults(145)
    );
  EncoderMonitor0_SerialResults_145_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_145_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_145_FFX_RST
    );
  EncoderMonitor0_SerialResults_157 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0213,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_157_FFX_RST,
      O => EncoderMonitor0_SerialResults(157)
    );
  EncoderMonitor0_SerialResults_157_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_157_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_157_FFX_RST
    );
  EncoderMonitor0_SerialResults_151 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0219,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_151_FFY_RST,
      O => EncoderMonitor0_SerialResults(151)
    );
  EncoderMonitor0_SerialResults_151_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_151_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_151_FFY_RST
    );
  EncoderMonitor0_SerialResults_158 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0212,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_159_FFY_RST,
      O => EncoderMonitor0_SerialResults(158)
    );
  EncoderMonitor0_SerialResults_159_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_159_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_159_FFY_RST
    );
  EncoderMonitor0_SerialResults_155 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0215,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_155_FFX_RST,
      O => EncoderMonitor0_SerialResults(155)
    );
  EncoderMonitor0_SerialResults_155_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_155_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_155_FFX_RST
    );
  EncoderMonitor0_SerialResults_156 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0214,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_157_FFY_RST,
      O => EncoderMonitor0_SerialResults(156)
    );
  EncoderMonitor0_SerialResults_157_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_157_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_157_FFY_RST
    );
  EncoderMonitor0_SerialResults_153 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0217,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_153_FFX_RST,
      O => EncoderMonitor0_SerialResults(153)
    );
  EncoderMonitor0_SerialResults_153_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_153_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_153_FFX_RST
    );
  EncoderMonitor0_SerialResults_154 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0216,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_155_FFY_RST,
      O => EncoderMonitor0_SerialResults(154)
    );
  EncoderMonitor0_SerialResults_155_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_155_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_155_FFY_RST
    );
  EncoderMonitor0_SerialResults_141 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0229,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_141_FFX_RST,
      O => EncoderMonitor0_SerialResults(141)
    );
  EncoderMonitor0_SerialResults_141_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_141_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_141_FFX_RST
    );
  EncoderMonitor0_SerialResults_142 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0228,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_143_FFY_RST,
      O => EncoderMonitor0_SerialResults(142)
    );
  EncoderMonitor0_SerialResults_143_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_143_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_143_FFY_RST
    );
  EncoderMonitor0_SerialResults_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0101,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_13_FFX_RST,
      O => EncoderMonitor0_SerialResults(13)
    );
  EncoderMonitor0_SerialResults_13_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_13_FFX_RST
    );
  EncoderMonitor0_SerialResults_140 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0230,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_141_FFY_RST,
      O => EncoderMonitor0_SerialResults(140)
    );
  EncoderMonitor0_SerialResults_141_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_141_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_141_FFY_RST
    );
  EncoderMonitor0_SerialResults_137 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0233,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_137_FFX_RST,
      O => EncoderMonitor0_SerialResults(137)
    );
  EncoderMonitor0_SerialResults_137_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_137_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_137_FFX_RST
    );
  EncoderMonitor0_SerialResults_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0102,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_13_FFY_RST,
      O => EncoderMonitor0_SerialResults(12)
    );
  EncoderMonitor0_SerialResults_13_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_13_FFY_RST
    );
  EncoderMonitor0_SerialResults_139 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0231,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_139_FFX_RST,
      O => EncoderMonitor0_SerialResults(139)
    );
  EncoderMonitor0_SerialResults_139_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_139_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_139_FFX_RST
    );
  EncoderMonitor0_SerialResults_132 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0238,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_133_FFY_RST,
      O => EncoderMonitor0_SerialResults(132)
    );
  EncoderMonitor0_SerialResults_133_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_133_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_133_FFY_RST
    );
  EncoderMonitor0_SerialResults_125 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0181,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_125_FFX_RST,
      O => EncoderMonitor0_SerialResults(125)
    );
  EncoderMonitor0_SerialResults_125_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_125_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_125_FFX_RST
    );
  EncoderMonitor0_SerialResults_129 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0241,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_129_FFX_RST,
      O => EncoderMonitor0_SerialResults(129)
    );
  EncoderMonitor0_SerialResults_129_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_129_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_129_FFX_RST
    );
  EncoderMonitor0_SerialResults_128 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0242,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_129_FFY_RST,
      O => EncoderMonitor0_SerialResults(128)
    );
  EncoderMonitor0_SerialResults_129_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_129_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_129_FFY_RST
    );
  EncoderMonitor0_SerialResults_130 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0240,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_131_FFY_RST,
      O => EncoderMonitor0_SerialResults(130)
    );
  EncoderMonitor0_SerialResults_131_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_131_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_131_FFY_RST
    );
  EncoderMonitor0_SerialResults_127 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0179,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_127_FFX_RST,
      O => EncoderMonitor0_SerialResults(127)
    );
  EncoderMonitor0_SerialResults_127_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_127_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_127_FFX_RST
    );
  EncoderMonitor0_SerialResults_138 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0232,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_139_FFY_RST,
      O => EncoderMonitor0_SerialResults(138)
    );
  EncoderMonitor0_SerialResults_139_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_139_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_139_FFY_RST
    );
  EncoderMonitor0_SerialResults_133 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0237,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_133_FFX_RST,
      O => EncoderMonitor0_SerialResults(133)
    );
  EncoderMonitor0_SerialResults_133_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_133_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_133_FFX_RST
    );
  EncoderMonitor0_SerialResults_135 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0235,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_135_FFX_RST,
      O => EncoderMonitor0_SerialResults(135)
    );
  EncoderMonitor0_SerialResults_135_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_135_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_135_FFX_RST
    );
  EncoderMonitor0_SerialResults_131 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0239,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_131_FFX_RST,
      O => EncoderMonitor0_SerialResults(131)
    );
  EncoderMonitor0_SerialResults_131_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_131_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_131_FFX_RST
    );
  EncoderMonitor0_SerialResults_136 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0234,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_137_FFY_RST,
      O => EncoderMonitor0_SerialResults(136)
    );
  EncoderMonitor0_SerialResults_137_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_137_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_137_FFY_RST
    );
  EncoderMonitor0_SerialResults_115 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0191,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_115_FFX_RST,
      O => EncoderMonitor0_SerialResults(115)
    );
  EncoderMonitor0_SerialResults_115_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_115_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_115_FFX_RST
    );
  EncoderMonitor0_SerialResults_116 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0190,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_117_FFY_RST,
      O => EncoderMonitor0_SerialResults(116)
    );
  EncoderMonitor0_SerialResults_117_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_117_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_117_FFY_RST
    );
  EncoderMonitor0_SerialResults_113 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0193,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_113_FFX_RST,
      O => EncoderMonitor0_SerialResults(113)
    );
  EncoderMonitor0_SerialResults_113_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_113_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_113_FFX_RST
    );
  EncoderMonitor0_SerialResults_114 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0192,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_115_FFY_RST,
      O => EncoderMonitor0_SerialResults(114)
    );
  EncoderMonitor0_SerialResults_115_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_115_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_115_FFY_RST
    );
  EncoderMonitor0_SerialResults_111 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0195,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_111_FFX_RST,
      O => EncoderMonitor0_SerialResults(111)
    );
  EncoderMonitor0_SerialResults_111_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_111_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_111_FFX_RST
    );
  EncoderMonitor0_SerialResults_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0104,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_11_FFY_RST,
      O => EncoderMonitor0_SerialResults(10)
    );
  EncoderMonitor0_SerialResults_11_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_11_FFY_RST
    );
  EncoderMonitor0_SerialResults_120 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0186,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_121_FFY_RST,
      O => EncoderMonitor0_SerialResults(120)
    );
  EncoderMonitor0_SerialResults_121_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_121_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_121_FFY_RST
    );
  EncoderMonitor0_SerialResults_117 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0189,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_117_FFX_RST,
      O => EncoderMonitor0_SerialResults(117)
    );
  EncoderMonitor0_SerialResults_117_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_117_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_117_FFX_RST
    );
  EncoderMonitor0_SerialResults_119 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0187,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_119_FFX_RST,
      O => EncoderMonitor0_SerialResults(119)
    );
  EncoderMonitor0_SerialResults_119_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_119_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_119_FFX_RST
    );
  EncoderMonitor0_SerialResults_122 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0184,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_123_FFY_RST,
      O => EncoderMonitor0_SerialResults(122)
    );
  EncoderMonitor0_SerialResults_123_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_123_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_123_FFY_RST
    );
  EncoderMonitor0_SerialResults_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0103,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_11_FFX_RST,
      O => EncoderMonitor0_SerialResults(11)
    );
  EncoderMonitor0_SerialResults_11_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_11_FFX_RST
    );
  EncoderMonitor0_SerialResults_126 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0180,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_127_FFY_RST,
      O => EncoderMonitor0_SerialResults(126)
    );
  EncoderMonitor0_SerialResults_127_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_127_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_127_FFY_RST
    );
  EncoderMonitor0_SerialResults_121 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0185,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_121_FFX_RST,
      O => EncoderMonitor0_SerialResults(121)
    );
  EncoderMonitor0_SerialResults_121_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_121_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_121_FFX_RST
    );
  EncoderMonitor0_SerialResults_123 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0183,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_123_FFX_RST,
      O => EncoderMonitor0_SerialResults(123)
    );
  EncoderMonitor0_SerialResults_123_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_123_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_123_FFX_RST
    );
  EncoderMonitor0_SerialResults_124 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0182,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_125_FFY_RST,
      O => EncoderMonitor0_SerialResults(124)
    );
  EncoderMonitor0_SerialResults_125_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_125_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_125_FFY_RST
    );
  EncoderMonitor0_SerialResults_101 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0205,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_101_FFX_RST,
      O => EncoderMonitor0_SerialResults(101)
    );
  EncoderMonitor0_SerialResults_101_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_101_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_101_FFX_RST
    );
  EncoderMonitor0_SelEncInc_1057 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_SelEncInc_F5MUX,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncInc_FFX_RST,
      O => EncoderMonitor0_SelEncInc
    );
  EncoderMonitor0_SelEncInc_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncInc_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncInc_FFX_RST
    );
  EncoderMonitor0_SerialResults_102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0204,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_103_FFY_RST,
      O => EncoderMonitor0_SerialResults(102)
    );
  EncoderMonitor0_SerialResults_103_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_103_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_103_FFY_RST
    );
  EncoderMonitor0_SelEncReset_1_1058 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0297,
      CE => EncoderMonitor0_n0452,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncReset_1_FFX_RST,
      O => EncoderMonitor0_SelEncReset_1
    );
  EncoderMonitor0_SelEncReset_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncReset_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncReset_1_FFX_RST
    );
  EncoderMonitor0_SerialResults_112 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0194,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_113_FFY_RST,
      O => EncoderMonitor0_SerialResults(112)
    );
  EncoderMonitor0_SerialResults_113_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_113_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_113_FFY_RST
    );
  EncoderMonitor0_SerialResults_109 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0197,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_109_FFX_RST,
      O => EncoderMonitor0_SerialResults(109)
    );
  EncoderMonitor0_SerialResults_109_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_109_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_109_FFX_RST
    );
  EncoderMonitor0_SerialResults_110 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0196,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_111_FFY_RST,
      O => EncoderMonitor0_SerialResults(110)
    );
  EncoderMonitor0_SerialResults_111_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_111_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_111_FFY_RST
    );
  EncoderMonitor0_SerialResults_107 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0199,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_107_FFX_RST,
      O => EncoderMonitor0_SerialResults(107)
    );
  EncoderMonitor0_SerialResults_107_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_107_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_107_FFX_RST
    );
  EncoderMonitor0_SerialResults_108 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0198,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_109_FFY_RST,
      O => EncoderMonitor0_SerialResults(108)
    );
  EncoderMonitor0_SerialResults_109_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_109_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_109_FFY_RST
    );
  EncoderMonitor0_SerialResults_105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0201,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_105_FFX_RST,
      O => EncoderMonitor0_SerialResults(105)
    );
  EncoderMonitor0_SerialResults_105_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_105_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_105_FFX_RST
    );
  EncoderMonitor0_SerialResults_106 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0200,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_107_FFY_RST,
      O => EncoderMonitor0_SerialResults(106)
    );
  EncoderMonitor0_SerialResults_107_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_107_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_107_FFY_RST
    );
  EncoderMonitor0_SerialResults_103 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0203,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_103_FFX_RST,
      O => EncoderMonitor0_SerialResults(103)
    );
  EncoderMonitor0_SerialResults_103_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_103_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_103_FFX_RST
    );
  EncoderMonitor0_IncHysterisis_1059 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0078,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_IncHysterisis_FFX_RST,
      O => EncoderMonitor0_IncHysterisis
    );
  EncoderMonitor0_IncHysterisis_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_IncHysterisis_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_IncHysterisis_FFX_RST
    );
  EncoderMonitor0_LastInputs_0_0_1060 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder0In(0),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_0_1_FFY_RST,
      O => EncoderMonitor0_LastInputs_0_0
    );
  EncoderMonitor0_LastInputs_0_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_0_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_0_1_FFY_RST
    );
  EncoderMonitor0_LatchData_1_1061 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_1_FFX_RST,
      O => EncoderMonitor0_LatchData_1
    );
  EncoderMonitor0_LatchData_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_1_FFX_RST
    );
  EncoderMonitor0_vTrigCountMin_1062 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => EncoderMonitor0_n0296,
      CE => VCC,
      CLK => LCLK,
      SET => EncoderMonitor0_LatchData_2_FFY_SET,
      RST => GND,
      O => EncoderMonitor0_vTrigCountMin
    );
  EncoderMonitor0_LatchData_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => EncoderMonitor0_LatchData_2_SRMUX_OUTPUTNOT,
      O => EncoderMonitor0_LatchData_2_FFY_SET
    );
  EncoderMonitor0_LatchData_1063 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_LatchData_1_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_1_FFY_RST,
      O => EncoderMonitor0_LatchData
    );
  EncoderMonitor0_LatchData_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_1_FFY_RST
    );
  EncoderMonitor0_LastInputs_2_1_1064 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder2In(1),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_2_1_FFX_RST,
      O => EncoderMonitor0_LastInputs_2_1
    );
  EncoderMonitor0_LastInputs_2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_2_1_FFX_RST
    );
  EncoderMonitor0_LastInputs_2_0_1065 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder2In(0),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_2_1_FFY_RST,
      O => EncoderMonitor0_LastInputs_2_0
    );
  EncoderMonitor0_LastInputs_2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_2_1_FFY_RST
    );
  EncoderMonitor0_LastInputs_1_1_1066 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder1In(1),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_1_1_FFX_RST,
      O => EncoderMonitor0_LastInputs_1_1
    );
  EncoderMonitor0_LastInputs_1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_1_1_FFX_RST
    );
  EncoderMonitor0_LastInputs_1_0_1067 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder1In(0),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_1_1_FFY_RST,
      O => EncoderMonitor0_LastInputs_1_0
    );
  EncoderMonitor0_LastInputs_1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_1_1_FFY_RST
    );
  EncoderMonitor0_LastInputs_0_1_1068 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => Encoder0In(1),
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LastInputs_0_1_FFX_RST,
      O => EncoderMonitor0_LastInputs_0_1
    );
  EncoderMonitor0_LastInputs_0_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LastInputs_0_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LastInputs_0_1_FFX_RST
    );
  EncoderMonitor0_LatchData_4_1069 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_4_FFX_RST,
      O => EncoderMonitor0_LatchData_4
    );
  EncoderMonitor0_LatchData_4_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_4_FFX_RST
    );
  EncoderMonitor0_LatchData_2_1070 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_2_FFX_RST,
      O => EncoderMonitor0_LatchData_2
    );
  EncoderMonitor0_LatchData_2_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_2_FFX_RST
    );
  EncoderMonitor0_LatchData_6_1071 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_6_FFX_RST,
      O => EncoderMonitor0_LatchData_6
    );
  EncoderMonitor0_LatchData_6_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_6_FFX_RST
    );
  EncoderMonitor0_SelEncInc_1_1072 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0071,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncInc_FFY_RST,
      O => EncoderMonitor0_SelEncInc_1
    );
  EncoderMonitor0_SelEncInc_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncInc_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncInc_FFY_RST
    );
  EncoderMonitor0_SelEncDec_1073 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0072,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncDec_FFX_RST,
      O => EncoderMonitor0_SelEncDec
    );
  EncoderMonitor0_SelEncDec_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncDec_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncDec_FFX_RST
    );
  EncoderMonitor0_vTemp_1074 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ClkEn1,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncDec_FFY_RST,
      O => EncoderMonitor0_vTemp
    );
  EncoderMonitor0_SelEncDec_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncDec_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncDec_FFY_RST
    );
  EncoderMonitor0_EncDec_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0288,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncDec_1_FFY_RST,
      O => EncoderMonitor0_EncDec(0)
    );
  EncoderMonitor0_EncDec_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncDec_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncDec_1_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_8_1075 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_28,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_8_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_8
    );
  EncoderMonitor0_EncCounts_2_8_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_8_FFX_RST
    );
  EncoderMonitor0_EncDec_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0289,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncDec_1_FFX_RST,
      O => EncoderMonitor0_EncDec(1)
    );
  EncoderMonitor0_EncDec_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncDec_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncDec_1_FFX_RST
    );
  EncoderMonitor0_EncInc_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncInc_0_1_GROM,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_0_1_FFY_RST,
      O => EncoderMonitor0_EncInc(0)
    );
  EncoderMonitor0_EncInc_0_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_0_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_0_1_FFY_RST
    );
  EncoderMonitor0_EncInc_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncInc_1_1_GROM,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_1_1_FFY_RST,
      O => EncoderMonitor0_EncInc(1)
    );
  EncoderMonitor0_EncInc_1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_1_1_FFY_RST
    );
  EncoderMonitor0_EncInc_2_1_1076 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0284,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_2_1_FFX_RST,
      O => EncoderMonitor0_EncInc_2_1
    );
  EncoderMonitor0_EncInc_2_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_2_1_FFX_RST
    );
  EncoderMonitor0_EncoderReset_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_pEncoderReset(0),
      CE => EncoderMonitor0_n0415,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncoderReset_0_FFY_RST,
      O => EncoderMonitor0_EncoderReset(0)
    );
  EncoderMonitor0_EncoderReset_0_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncoderReset_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncoderReset_0_FFY_RST
    );
  EncoderMonitor0_EncInc_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncInc_2_1_GROM,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_2_1_FFY_RST,
      O => EncoderMonitor0_EncInc(2)
    );
  EncoderMonitor0_EncInc_2_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_2_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_2_1_FFY_RST
    );
  EncoderMonitor0_EncInc_0_1_1077 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0282,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_0_1_FFX_RST,
      O => EncoderMonitor0_EncInc_0_1
    );
  EncoderMonitor0_EncInc_0_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_0_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_0_1_FFX_RST
    );
  EncoderMonitor0_EncInc_1_1_1078 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0283,
      CE => EncoderMonitor0_ClkEn1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncInc_1_1_FFX_RST,
      O => EncoderMonitor0_EncInc_1_1
    );
  EncoderMonitor0_EncInc_1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncInc_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncInc_1_1_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_35_1079 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_55,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_34_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_35
    );
  EncoderMonitor0_EncCounts_2_34_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_34_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_32_1080 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_52,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_32_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_32
    );
  EncoderMonitor0_EncCounts_2_32_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_32_FFX_RST
    );
  EncoderMonitor0_EncoderReset_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_pEncoderReset(1),
      CE => EncoderMonitor0_n0417,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncoderReset_1_FFY_RST,
      O => EncoderMonitor0_EncoderReset(1)
    );
  EncoderMonitor0_EncoderReset_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncoderReset_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncoderReset_1_FFY_RST
    );
  EncoderMonitor0_EncoderReset_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_pEncoderReset(2),
      CE => EncoderMonitor0_n0419,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncoderReset_2_FFY_RST,
      O => EncoderMonitor0_EncoderReset(2)
    );
  EncoderMonitor0_EncoderReset_2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncoderReset_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncoderReset_2_FFY_RST
    );
  EncoderMonitor0_DecHysterisis_1081 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => EncoderMonitor0_n0079,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => EncoderMonitor0_IncHysterisis_FFY_SET,
      RST => GND,
      O => EncoderMonitor0_DecHysterisis
    );
  EncoderMonitor0_IncHysterisis_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => EncoderMonitor0_IncHysterisis_SRMUX_OUTPUTNOT,
      O => EncoderMonitor0_IncHysterisis_FFY_SET
    );
  EncoderMonitor0_LatchData_3_1082 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_4_FFY_RST,
      O => EncoderMonitor0_LatchData_3
    );
  EncoderMonitor0_LatchData_4_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_4_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_30_1083 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_50,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_30_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_30
    );
  EncoderMonitor0_EncCounts_2_30_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_30_FFX_RST
    );
  EncoderMonitor0_LatchData_5_1084 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0081,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_LatchData_6_FFY_RST,
      O => EncoderMonitor0_LatchData_5
    );
  EncoderMonitor0_LatchData_6_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_LatchData_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_LatchData_6_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_37_1085 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_57,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_36_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_37
    );
  EncoderMonitor0_EncCounts_2_36_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_36_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_39_1086 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_59,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_38_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_39
    );
  EncoderMonitor0_EncCounts_2_38_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_38_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_36_1087 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_56,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_36_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_36
    );
  EncoderMonitor0_EncCounts_2_36_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_36_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_34_1088 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_54,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_34_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_34
    );
  EncoderMonitor0_EncCounts_2_34_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_34_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_9_1089 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_29,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_8_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_9
    );
  EncoderMonitor0_EncCounts_2_8_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_8_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_38_1090 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_58,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_38_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_38
    );
  EncoderMonitor0_EncCounts_2_38_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_38_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_27_1091 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_47,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_26_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_27
    );
  EncoderMonitor0_EncCounts_2_26_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_26_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_24_1092 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_44,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_24_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_24
    );
  EncoderMonitor0_EncCounts_2_24_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_24_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_29_1093 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_49,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_28_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_29
    );
  EncoderMonitor0_EncCounts_2_28_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_28_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_22_1094 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_42,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_22_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_22
    );
  EncoderMonitor0_EncCounts_2_22_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_22_FFX_RST
    );
  EncoderMonitor0_SerialResults_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0086,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_29_FFY_RST,
      O => EncoderMonitor0_SerialResults(28)
    );
  EncoderMonitor0_SerialResults_29_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_29_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_26_1095 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_46,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_26_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_26
    );
  EncoderMonitor0_EncCounts_2_26_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_26_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_31_1096 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_51,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_30_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_31
    );
  EncoderMonitor0_EncCounts_2_30_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_30_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_33_1097 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_53,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_32_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_33
    );
  EncoderMonitor0_EncCounts_2_32_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_32_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_28_1098 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_48,
      CE => EncoderMonitor0_n0437130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_28_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_28
    );
  EncoderMonitor0_EncCounts_2_28_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_28_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_21_1099 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_41,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_20_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_21
    );
  EncoderMonitor0_EncCounts_2_20_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_20_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_18_1100 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_38,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_18_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_18
    );
  EncoderMonitor0_EncCounts_2_18_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_18_FFX_RST
    );
  EncoderMonitor0_SerialResults_32 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0146,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_33_FFY_RST,
      O => EncoderMonitor0_SerialResults(32)
    );
  EncoderMonitor0_SerialResults_33_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_33_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_33_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_23_1101 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_43,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_22_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_23
    );
  EncoderMonitor0_EncCounts_2_22_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_22_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_16_1102 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_36,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_16_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_16
    );
  EncoderMonitor0_EncCounts_2_16_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_16_FFX_RST
    );
  EncoderMonitor0_SerialResults_88 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0154,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_89_FFY_RST,
      O => EncoderMonitor0_SerialResults(88)
    );
  EncoderMonitor0_SerialResults_89_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_89_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_89_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_25_1103 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_45,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_24_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_25
    );
  EncoderMonitor0_EncCounts_2_24_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_24_FFY_RST
    );
  EncoderMonitor0_SerialResults_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0094,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_21_FFY_RST,
      O => EncoderMonitor0_SerialResults(20)
    );
  EncoderMonitor0_SerialResults_21_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_21_FFY_RST
    );
  EncoderMonitor0_SerialResults_60 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0118,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_61_FFY_RST,
      O => EncoderMonitor0_SerialResults(60)
    );
  EncoderMonitor0_SerialResults_61_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_61_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_61_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_20_1104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_40,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_20_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_20
    );
  EncoderMonitor0_EncCounts_2_20_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_20_FFX_RST
    );
  EncoderMonitor0_SerialResults_118 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0188,
      CE => EncoderMonitor0_n04541_9,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_119_FFY_RST,
      O => EncoderMonitor0_SerialResults(118)
    );
  EncoderMonitor0_SerialResults_119_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_119_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_119_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_15_1105 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_35,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_14_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_15
    );
  EncoderMonitor0_EncCounts_2_14_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_14_FFY_RST
    );
  EncoderMonitor0_SerialResults_104 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0202,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_105_FFY_RST,
      O => EncoderMonitor0_SerialResults(104)
    );
  EncoderMonitor0_SerialResults_105_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_105_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_105_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_13_1106 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_33,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_12_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_13
    );
  EncoderMonitor0_EncCounts_2_12_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_12_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_10_1107 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_30,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_10_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_10
    );
  EncoderMonitor0_EncCounts_2_10_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_10_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_19_1108 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_39,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_18_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_19
    );
  EncoderMonitor0_EncCounts_2_18_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_18_FFY_RST
    );
  EncoderMonitor0_SerialResults_78 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0164,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_79_FFY_RST,
      O => EncoderMonitor0_SerialResults(78)
    );
  EncoderMonitor0_SerialResults_79_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_79_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_79_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_12_1109 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_32,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_12_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_12
    );
  EncoderMonitor0_EncCounts_2_12_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_12_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_17_1110 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_37,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_16_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_17
    );
  EncoderMonitor0_EncCounts_2_16_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_16_FFY_RST
    );
  EncoderMonitor0_SerialResults_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0109,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_6_FFY_RST,
      O => EncoderMonitor0_SerialResults(5)
    );
  EncoderMonitor0_SerialResults_6_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_6_FFY_RST
    );
  EncoderMonitor0_EncCounts_2_14_1111 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_34,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_14_FFX_RST,
      O => EncoderMonitor0_EncCounts_2_14
    );
  EncoderMonitor0_EncCounts_2_14_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_14_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_34_1112 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_54,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_34_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_34
    );
  EncoderMonitor0_EncCounts_1_34_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_34_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_9_1113 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_29,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_8_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_9
    );
  EncoderMonitor0_EncCounts_1_8_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_8_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_39_1114 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_59,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_38_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_39
    );
  EncoderMonitor0_EncCounts_1_38_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_38_FFY_RST
    );
  EncoderMonitor0_SerialResults_164 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0270,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_165_FFY_RST,
      O => EncoderMonitor0_SerialResults(164)
    );
  EncoderMonitor0_SerialResults_165_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_165_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_165_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_36_1115 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_56,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_36_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_36
    );
  EncoderMonitor0_EncCounts_1_36_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_36_FFX_RST
    );
  EncoderMonitor0_SerialResults_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0100,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_15_FFY_RST,
      O => EncoderMonitor0_SerialResults(14)
    );
  EncoderMonitor0_SerialResults_15_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_15_FFY_RST
    );
  EncoderMonitor0_SelEncReset_1116 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_SelEncReset_1_GROM,
      CE => EncoderMonitor0_n0452,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SelEncReset_1_FFY_RST,
      O => EncoderMonitor0_SelEncReset
    );
  EncoderMonitor0_SelEncReset_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SelEncReset_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SelEncReset_1_FFY_RST
    );
  EncoderMonitor0_SerialResults_100 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0206,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_101_FFY_RST,
      O => EncoderMonitor0_SerialResults(100)
    );
  EncoderMonitor0_SerialResults_101_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_101_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_101_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_38_1117 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_58,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_38_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_38
    );
  EncoderMonitor0_EncCounts_1_38_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_38_FFX_RST
    );
  EncoderMonitor0_EncCounts_2_11_1118 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_2_inst_sum_31,
      CE => EncoderMonitor0_n0437,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_2_10_FFY_RST,
      O => EncoderMonitor0_EncCounts_2_11
    );
  EncoderMonitor0_EncCounts_2_10_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_2_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_2_10_FFY_RST
    );
  EncoderMonitor0_SerialResults_144 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0226,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_145_FFY_RST,
      O => EncoderMonitor0_SerialResults(144)
    );
  EncoderMonitor0_SerialResults_145_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_145_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_145_FFY_RST
    );
  EncoderMonitor0_SerialResults_134 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0236,
      CE => EncoderMonitor0_n04541_8,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_135_FFY_RST,
      O => EncoderMonitor0_SerialResults(134)
    );
  EncoderMonitor0_SerialResults_135_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_135_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_135_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_8_1119 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_28,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_8_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_8
    );
  EncoderMonitor0_EncCounts_1_8_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_8_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_37_1120 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_57,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_36_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_37
    );
  EncoderMonitor0_EncCounts_1_36_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_36_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_35_1121 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_55,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_34_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_35
    );
  EncoderMonitor0_EncCounts_1_34_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_34_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_32_1122 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_52,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_32_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_32
    );
  EncoderMonitor0_EncCounts_1_32_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_32_FFX_RST
    );
  EncoderMonitor0_SerialResults_152 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0218,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_153_FFY_RST,
      O => EncoderMonitor0_SerialResults(152)
    );
  EncoderMonitor0_SerialResults_153_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_153_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_153_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_30_1123 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_50,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_30_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_30
    );
  EncoderMonitor0_EncCounts_1_30_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_30_FFX_RST
    );
  EncoderMonitor0_SerialResults_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0098,
      CE => EncoderMonitor0_n04541_7,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_16_FFY_RST,
      O => EncoderMonitor0_SerialResults(16)
    );
  EncoderMonitor0_SerialResults_16_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_16_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_33_1124 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_53,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_32_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_33
    );
  EncoderMonitor0_EncCounts_1_32_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_32_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_31_1125 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_51,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_30_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_31
    );
  EncoderMonitor0_EncCounts_1_30_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_30_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_28_1126 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_48,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_28_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_28
    );
  EncoderMonitor0_EncCounts_1_28_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_28_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_26_1127 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_46,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_26_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_26
    );
  EncoderMonitor0_EncCounts_1_26_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_26_FFX_RST
    );
  EncoderMonitor0_SerialResults_66 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0176,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_67_FFY_RST,
      O => EncoderMonitor0_SerialResults(66)
    );
  EncoderMonitor0_SerialResults_67_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_67_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_67_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_23_1128 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_43,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_22_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_23
    );
  EncoderMonitor0_EncCounts_1_22_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_22_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_21_1129 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_41,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_20_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_21
    );
  EncoderMonitor0_EncCounts_1_20_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_20_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_16_1130 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_36,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_16_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_16
    );
  EncoderMonitor0_EncCounts_1_16_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_16_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_18_1131 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_38,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_18_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_18
    );
  EncoderMonitor0_EncCounts_1_18_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_18_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_24_1132 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_44,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_24_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_24
    );
  EncoderMonitor0_EncCounts_1_24_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_24_FFX_RST
    );
  EncoderMonitor0_SerialResults_84 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0158,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_85_FFY_RST,
      O => EncoderMonitor0_SerialResults(84)
    );
  EncoderMonitor0_SerialResults_85_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_85_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_85_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_27_1133 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_47,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_26_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_27
    );
  EncoderMonitor0_EncCounts_1_26_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_26_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_29_1134 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_49,
      CE => EncoderMonitor0_n0433130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_28_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_29
    );
  EncoderMonitor0_EncCounts_1_28_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_28_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_20_1135 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_40,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_20_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_20
    );
  EncoderMonitor0_EncCounts_1_20_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_20_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_25_1136 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_45,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_24_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_25
    );
  EncoderMonitor0_EncCounts_1_24_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_24_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_22_1137 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_42,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_22_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_22
    );
  EncoderMonitor0_EncCounts_1_22_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_22_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_18_1138 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_38,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_18_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_18
    );
  EncoderMonitor0_EncCounts_0_18_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_18_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_23_1139 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_43,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_22_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_23
    );
  EncoderMonitor0_EncCounts_0_22_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_22_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_15_1140 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_35,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_14_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_15
    );
  EncoderMonitor0_EncCounts_1_14_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_14_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_13_1141 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_33,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_12_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_13
    );
  EncoderMonitor0_EncCounts_1_12_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_12_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_10_1142 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_30,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_10_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_10
    );
  EncoderMonitor0_EncCounts_1_10_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_10_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_19_1143 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_39,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_18_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_19
    );
  EncoderMonitor0_EncCounts_1_18_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_18_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_17_1144 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_37,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_16_FFY_RST,
      O => EncoderMonitor0_EncCounts_1_17
    );
  EncoderMonitor0_EncCounts_1_16_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_16_FFY_RST
    );
  EncoderMonitor0_EncCounts_1_14_1145 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_34,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_14_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_14
    );
  EncoderMonitor0_EncCounts_1_14_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_14_FFX_RST
    );
  EncoderMonitor0_EncCounts_1_12_1146 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_1_inst_sum_32,
      CE => EncoderMonitor0_n0433,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_1_12_FFX_RST,
      O => EncoderMonitor0_EncCounts_1_12
    );
  EncoderMonitor0_EncCounts_1_12_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_1_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_1_12_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_8_1147 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_28,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_8_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_8
    );
  EncoderMonitor0_EncCounts_0_8_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_8_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_38_1148 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_58,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_38_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_38
    );
  EncoderMonitor0_EncCounts_0_38_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_38_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_37_1149 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_57,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_36_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_37
    );
  EncoderMonitor0_EncCounts_0_36_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_36_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_32_1150 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_52,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_32_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_32
    );
  EncoderMonitor0_EncCounts_0_32_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_32_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_34_1151 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_54,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_34_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_34
    );
  EncoderMonitor0_EncCounts_0_34_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_34_FFX_RST
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(1),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(2)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFY_SET
    );
  EncoderMonitor0_EncCounts_0_36_1152 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_56,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_36_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_36
    );
  EncoderMonitor0_EncCounts_0_36_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_36_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_36_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_9_1153 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_29,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_8_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_9
    );
  EncoderMonitor0_EncCounts_0_8_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_8_FFY_RST
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_FeedbackBit,
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(0)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(1),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(2)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFY_SET
    );
  EncoderMonitor0_EncCounts_0_39_1154 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_59,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_38_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_39
    );
  EncoderMonitor0_EncCounts_0_38_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_38_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_38_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_22_1155 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_42,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_22_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_22
    );
  EncoderMonitor0_EncCounts_0_22_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_22_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_29_1156 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_49,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_28_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_29
    );
  EncoderMonitor0_EncCounts_0_28_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_28_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_27_1157 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_47,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_26_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_27
    );
  EncoderMonitor0_EncCounts_0_26_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_26_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_24_1158 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_44,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_24_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_24
    );
  EncoderMonitor0_EncCounts_0_24_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_24_FFX_RST
    );
  PerLBusInterface0_RegBank_19_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_6_FFY_RST,
      O => PerLBusInterface0_RegBank_19_5_Q
    );
  PerLBusInterface0_RegBank_19_6_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_6_FFY_RST
    );
  PerLBusInterface0_RegBank_19_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_8_FFY_RST,
      O => PerLBusInterface0_RegBank_19_7_Q
    );
  PerLBusInterface0_RegBank_19_8_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_8_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_31_1159 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_51,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_30_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_31
    );
  EncoderMonitor0_EncCounts_0_30_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_30_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_28_1160 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_48,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_28_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_28
    );
  EncoderMonitor0_EncCounts_0_28_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_28_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_33_1161 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_53,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_32_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_33
    );
  EncoderMonitor0_EncCounts_0_32_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_32_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_32_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_26_1162 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_46,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_26_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_26
    );
  EncoderMonitor0_EncCounts_0_26_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_26_FFX_RST
    );
  PerLBusInterface0_pGateDataSel_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_RegBank_16_2,
      CE => pnLReset_IBUF,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pGateDataSel_2_FFY_RST,
      O => PerLBusInterface0_pGateDataSel(2)
    );
  PerLBusInterface0_pGateDataSel_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_pGateDataSel_2_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_35_1163 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_55,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_34_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_35
    );
  EncoderMonitor0_EncCounts_0_34_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_34_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_34_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_30_1164 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_50,
      CE => EncoderMonitor0_n0428130_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_30_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_30
    );
  EncoderMonitor0_EncCounts_0_30_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_30_FFX_RST
    );
  PerLBusInterface0_RegBank_0_0_1165 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_1_FFY_RST,
      O => PerLBusInterface0_RegBank_0_0
    );
  PerLBusInterface0_RegBank_0_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_1_FFY_RST
    );
  PerLBusInterface0_RegBank_19_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_DoFocus,
      CE => PerLBusInterface0_n0508,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_31_FFY_RST,
      O => PerLBusInterface0_RegBank_19_31_Q
    );
  PerLBusInterface0_RegBank_19_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_31_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_25_1166 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_45,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_24_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_25
    );
  EncoderMonitor0_EncCounts_0_24_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_24_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_20_1167 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_40,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_20_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_20
    );
  EncoderMonitor0_EncCounts_0_20_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_20_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_15_1168 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_35,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_14_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_15
    );
  EncoderMonitor0_EncCounts_0_14_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_14_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_12_1169 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_32,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_12_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_12
    );
  EncoderMonitor0_EncCounts_0_12_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_12_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_17_1170 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_37,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_16_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_17
    );
  EncoderMonitor0_EncCounts_0_16_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_16_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_13_1171 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_33,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_12_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_13
    );
  EncoderMonitor0_EncCounts_0_12_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_12_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_10_1172 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_30,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_10_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_10
    );
  EncoderMonitor0_EncCounts_0_10_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_10_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_19_1173 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_39,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_18_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_19
    );
  EncoderMonitor0_EncCounts_0_18_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_18_FFY_RST
    );
  EncoderMonitor0_EncCounts_0_16_1174 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_36,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_16_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_16
    );
  EncoderMonitor0_EncCounts_0_16_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_16_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_14_1175 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_34,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_14_FFX_RST,
      O => EncoderMonitor0_EncCounts_0_14
    );
  EncoderMonitor0_EncCounts_0_14_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_14_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_21_1176 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_41,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_20_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_21
    );
  EncoderMonitor0_EncCounts_0_20_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_20_FFY_RST
    );
  EncoderMonitor0_ClkEnCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ClkEnCount_n0000(1),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEnCount_0_FFY_RST,
      O => EncoderMonitor0_ClkEnCount(1)
    );
  EncoderMonitor0_ClkEnCount_0_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEnCount_0_FFY_RST
    );
  EncoderMonitor0_ClkEn1_1177 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0281,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEn2_FFY_RST,
      O => EncoderMonitor0_ClkEn1
    );
  EncoderMonitor0_ClkEn2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEn2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEn2_FFY_RST
    );
  EncoderMonitor0_ClkEn2_1178 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_vTemp,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEn2_FFX_RST,
      O => EncoderMonitor0_ClkEn2
    );
  EncoderMonitor0_ClkEn2_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEn2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEn2_FFX_RST
    );
  EncoderMonitor0_EncCounts_0_11_1179 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_EncCounts_0_inst_sum_31,
      CE => EncoderMonitor0_n0428,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_EncCounts_0_10_FFY_RST,
      O => EncoderMonitor0_EncCounts_0_11
    );
  EncoderMonitor0_EncCounts_0_10_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_EncCounts_0_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_EncCounts_0_10_FFY_RST
    );
  EncoderMonitor0_ClkEnCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ClkEnCount_n0000(2),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEnCount_2_FFX_RST,
      O => EncoderMonitor0_ClkEnCount(2)
    );
  EncoderMonitor0_ClkEnCount_2_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEnCount_2_FFX_RST
    );
  EncoderMonitor0_ClkEnCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ClkEnCount_n0000(3),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEnCount_2_FFY_RST,
      O => EncoderMonitor0_ClkEnCount(3)
    );
  EncoderMonitor0_ClkEnCount_2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEnCount_2_FFY_RST
    );
  EncoderMonitor0_ClkEnCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ClkEnCount_Madd_n0000_inst_lut2_0,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ClkEnCount_0_FFX_RST,
      O => EncoderMonitor0_ClkEnCount(0)
    );
  EncoderMonitor0_ClkEnCount_0_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ClkEnCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ClkEnCount_0_FFX_RST
    );
  Encoder0In_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD0,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder0In_1_FFY_RST,
      O => Encoder0In(0)
    );
  Encoder0In_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Encoder0In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder0In_1_FFY_RST
    );
  Encoder1In_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD2,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder1In_1_FFY_RST,
      O => Encoder1In(0)
    );
  Encoder1In_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Encoder1In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder1In_1_FFY_RST
    );
  Encoder0In_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD1,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder0In_1_FFX_RST,
      O => Encoder0In(1)
    );
  Encoder0In_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Encoder0In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder0In_1_FFX_RST
    );
  PerLBusInterface0_IntAddr_5_1_1180 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_IntAddr_5_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_5_FFY_RST,
      O => PerLBusInterface0_IntAddr_5_1
    );
  PerLBusInterface0_IntAddr_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_5_FFY_RST
    );
  PerLBusInterface0_IntAddr_6_1_1181 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_IntAddr_6_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_6_FFY_RST,
      O => PerLBusInterface0_IntAddr_6_1
    );
  PerLBusInterface0_IntAddr_6_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_6_FFY_RST
    );
  PerLBusInterface0_IntAddr_7_1_1182 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50960,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_7_FFY_RST,
      O => PerLBusInterface0_IntAddr_7_1
    );
  PerLBusInterface0_IntAddr_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_7_FFY_RST
    );
  Encoder2In_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD4,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder2In_1_FFY_RST,
      O => Encoder2In(0)
    );
  Encoder2In_1_FFY_RSTOR : X_OR2
    port map (
      I0 => Encoder2In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder2In_1_FFY_RST
    );
  Encoder1In_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => IFD3,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => Encoder1In_1_FFX_RST,
      O => Encoder1In(1)
    );
  Encoder1In_1_FFX_RSTOR : X_OR2
    port map (
      I0 => Encoder1In_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => Encoder1In_1_FFX_RST
    );
  PerLBusInterface0_RegBank_0_24_1183 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49938,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_24_FFY_RST,
      O => PerLBusInterface0_RegBank_0_24
    );
  PerLBusInterface0_RegBank_0_24_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_24_FFY_RST
    );
  PerLBusInterface0_RegBank_14_26_1184 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(26),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_27_FFY_RST,
      O => PerLBusInterface0_RegBank_14_26
    );
  PerLBusInterface0_RegBank_14_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_27_FFY_RST
    );
  PerLBusInterface0_RegBank_14_20_1185 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(20),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_21_FFY_RST,
      O => PerLBusInterface0_RegBank_14_20
    );
  PerLBusInterface0_RegBank_14_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_21_FFY_RST
    );
  PerLBusInterface0_RegBank_14_6_1186 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(6),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_7_FFY_RST,
      O => PerLBusInterface0_RegBank_14_6
    );
  PerLBusInterface0_RegBank_14_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_7_FFY_RST
    );
  PerLBusInterface0_RegBank_19_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_2_FFY_RST,
      O => PerLBusInterface0_RegBank_19_1_Q
    );
  PerLBusInterface0_RegBank_19_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_2_FFY_RST
    );
  PerLBusInterface0_RegBank_0_10_1187 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_11_FFY_RST,
      O => PerLBusInterface0_RegBank_0_10
    );
  PerLBusInterface0_RegBank_0_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_11_FFY_RST
    );
  PerLBusInterface0_RegBank_0_18_1188 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49932,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_19_FFY_RST,
      O => PerLBusInterface0_RegBank_0_18
    );
  PerLBusInterface0_RegBank_0_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_19_FFY_RST
    );
  PerLBusInterface0_RegBank_14_16_1189 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(16),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_17_FFY_RST,
      O => PerLBusInterface0_RegBank_14_16
    );
  PerLBusInterface0_RegBank_14_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_17_FFY_RST
    );
  PerLBusInterface0_RegBank_0_20_1190 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49922,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_21_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_20
    );
  PerLBusInterface0_RegBank_0_21_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_21_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_21_FFY_SET
    );
  PerLBusInterface0_RegBank_0_22_1191 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49930,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_23_FFY_RST,
      O => PerLBusInterface0_RegBank_0_22
    );
  PerLBusInterface0_RegBank_0_23_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_23_FFY_RST
    );
  PerLBusInterface0_RegBank_15_20_1192 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(20),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_21_FFY_RST,
      O => PerLBusInterface0_RegBank_15_20
    );
  PerLBusInterface0_RegBank_15_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_21_FFY_RST
    );
  PerLBusInterface0_RegBank_15_30_1193 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(30),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_31_FFY_RST,
      O => PerLBusInterface0_RegBank_15_30
    );
  PerLBusInterface0_RegBank_15_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_31_FFY_RST
    );
  PerLBusInterface0_RegBank_15_26_1194 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(26),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_27_FFY_RST,
      O => PerLBusInterface0_RegBank_15_26
    );
  PerLBusInterface0_RegBank_15_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_27_FFY_RST
    );
  PerLBusInterface0_RegBank_14_10_1195 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(10),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_11_FFY_RST,
      O => PerLBusInterface0_RegBank_14_10
    );
  PerLBusInterface0_RegBank_14_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_11_FFY_RST
    );
  PerLBusInterface0_RegBank_7_10_1196 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_11_FFY_RST,
      O => PerLBusInterface0_RegBank_7_10
    );
  PerLBusInterface0_RegBank_7_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_11_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0317,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_20_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_20_Q
    );
  PerLBusInterface0_RegWriteEn_20_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_20_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0323,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_14_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_14_Q
    );
  PerLBusInterface0_RegWriteEn_14_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_14_FFY_RST
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_2 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_StrobeExtender0_CountLFSR(1),
      CE => PerLBusInterface0_StrobeExtender0_n0007,
      CLK => LCLK,
      SET => PerLBusInterface0_StrobeExtender0_CountLFSR_2_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR(2)
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_2_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_StrobeExtender0_CountLFSR_2_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_2_FFY_SET
    );
  TriggerDelay0_DelayActive_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayActive_1_GROM,
      CE => TriggerDelay0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayActive_1_FFY_RST,
      O => TriggerDelay0_DelayActive(1)
    );
  TriggerDelay0_DelayActive_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayActive_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayActive_1_FFY_RST
    );
  EncoderMonitor0_SerialResults_177 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0257,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_177_FFX_RST,
      O => EncoderMonitor0_SerialResults(177)
    );
  EncoderMonitor0_SerialResults_177_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_177_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_177_FFX_RST
    );
  EncoderMonitor0_SerialResults_175 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0259,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_175_FFX_RST,
      O => EncoderMonitor0_SerialResults(175)
    );
  EncoderMonitor0_SerialResults_175_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_175_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_175_FFX_RST
    );
  EncoderMonitor0_SerialResults_178 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0256,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_179_FFY_RST,
      O => EncoderMonitor0_SerialResults(178)
    );
  EncoderMonitor0_SerialResults_179_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_179_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_179_FFY_RST
    );
  EncoderMonitor0_SerialResults_180 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0254,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_181_FFY_RST,
      O => EncoderMonitor0_SerialResults(180)
    );
  EncoderMonitor0_SerialResults_181_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_181_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_181_FFY_RST
    );
  EncoderMonitor0_SerialResults_179 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0255,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_179_FFX_RST,
      O => EncoderMonitor0_SerialResults(179)
    );
  EncoderMonitor0_SerialResults_179_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_179_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_179_FFX_RST
    );
  EncoderMonitor0_SerialResults_182 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0252,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_183_FFY_RST,
      O => EncoderMonitor0_SerialResults(182)
    );
  EncoderMonitor0_SerialResults_183_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_183_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_183_FFY_RST
    );
  EncoderMonitor0_SerialResults_174 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0260,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_175_FFY_RST,
      O => EncoderMonitor0_SerialResults(174)
    );
  EncoderMonitor0_SerialResults_175_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_175_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_175_FFY_RST
    );
  EncoderMonitor0_SerialResults_171 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0263,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_171_FFX_RST,
      O => EncoderMonitor0_SerialResults(171)
    );
  EncoderMonitor0_SerialResults_171_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_171_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_171_FFX_RST
    );
  EncoderMonitor0_SerialResults_172 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0262,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_173_FFY_RST,
      O => EncoderMonitor0_SerialResults(172)
    );
  EncoderMonitor0_SerialResults_173_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_173_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_173_FFY_RST
    );
  EncoderMonitor0_SerialResults_170 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0264,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_171_FFY_RST,
      O => EncoderMonitor0_SerialResults(170)
    );
  EncoderMonitor0_SerialResults_171_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_171_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_171_FFY_RST
    );
  EncoderMonitor0_SerialResults_173 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0261,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_173_FFX_RST,
      O => EncoderMonitor0_SerialResults(173)
    );
  EncoderMonitor0_SerialResults_173_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_173_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_173_FFX_RST
    );
  EncoderMonitor0_SerialResults_176 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0258,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_177_FFY_RST,
      O => EncoderMonitor0_SerialResults(176)
    );
  EncoderMonitor0_SerialResults_177_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_177_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_177_FFY_RST
    );
  EncoderMonitor0_SerialResults_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0097,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_18_FFY_RST,
      O => EncoderMonitor0_SerialResults(17)
    );
  EncoderMonitor0_SerialResults_18_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_18_FFY_RST
    );
  EncoderMonitor0_SerialResults_187 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0247,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_187_FFX_RST,
      O => EncoderMonitor0_SerialResults(187)
    );
  EncoderMonitor0_SerialResults_187_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_187_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_187_FFX_RST
    );
  EncoderMonitor0_SerialResults_188 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0246,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_189_FFY_RST,
      O => EncoderMonitor0_SerialResults(188)
    );
  EncoderMonitor0_SerialResults_189_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_189_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_189_FFY_RST
    );
  EncoderMonitor0_SerialResults_185 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0249,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_185_FFX_RST,
      O => EncoderMonitor0_SerialResults(185)
    );
  EncoderMonitor0_SerialResults_185_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_185_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_185_FFX_RST
    );
  EncoderMonitor0_SerialResults_186 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0248,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_187_FFY_RST,
      O => EncoderMonitor0_SerialResults(186)
    );
  EncoderMonitor0_SerialResults_187_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_187_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_187_FFY_RST
    );
  EncoderMonitor0_SerialResults_183 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0251,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_183_FFX_RST,
      O => EncoderMonitor0_SerialResults(183)
    );
  EncoderMonitor0_SerialResults_183_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_183_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_183_FFX_RST
    );
  EncoderMonitor0_SerialResults_184 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0250,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_185_FFY_RST,
      O => EncoderMonitor0_SerialResults(184)
    );
  EncoderMonitor0_SerialResults_185_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_185_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_185_FFY_RST
    );
  EncoderMonitor0_SerialResults_181 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0253,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_181_FFX_RST,
      O => EncoderMonitor0_SerialResults(181)
    );
  EncoderMonitor0_SerialResults_181_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_181_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_181_FFX_RST
    );
  EncoderMonitor0_SerialResults_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0087,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_27_FFX_RST,
      O => EncoderMonitor0_SerialResults(27)
    );
  EncoderMonitor0_SerialResults_27_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_27_FFX_RST
    );
  EncoderMonitor0_SerialResults_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0084,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_31_FFY_RST,
      O => EncoderMonitor0_SerialResults(30)
    );
  EncoderMonitor0_SerialResults_31_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_31_FFY_RST
    );
  BScanCtrl0_BScanActive_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_BScanActive_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_BScanActive_FFY_RST
    );
  BScanCtrl0_BScanActive_1197 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_BScanTrigger,
      CE => BScanCtrl0_n0084,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_BScanActive_FFY_RST,
      O => BScanCtrl0_BScanActive
    );
  BScanCtrl0_BScanActive_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_BScanActive_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_BScanTrigger_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_BScanTrigger_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_BScanTrigger_FFY_RST
    );
  BScanCtrl0_BScanTrigger_1198 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0063,
      CE => BScanCtrl0_n0080,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_BScanTrigger_FFY_RST,
      O => BScanCtrl0_BScanTrigger
    );
  BScanCtrl0_n00801 : X_LUT4
    generic map(
      INIT => X"AABA"
    )
    port map (
      ADR0 => BScanCtrl0_ClkEn,
      ADR1 => BScanCtrl0_RxActive,
      ADR2 => BScanCtrl0_vBScanTrigger(1),
      ADR3 => BScanCtrl0_vBScanTrigger(2),
      O => BScanCtrl0_BScanTrigger_FROM
    );
  BScanCtrl0_n00631 : X_LUT4
    generic map(
      INIT => X"0300"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_vBScanTrigger(2),
      ADR2 => BScanCtrl0_RxActive,
      ADR3 => BScanCtrl0_vBScanTrigger(1),
      O => BScanCtrl0_n0063
    );
  BScanCtrl0_BScanTrigger_XUSED : X_BUF
    port map (
      I => BScanCtrl0_BScanTrigger_FROM,
      O => BScanCtrl0_n0080
    );
  BScanCtrl0_BScanTrigger_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_BScanTrigger_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ClkEn_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ClkEn_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ClkEn_FFY_RST
    );
  BScanCtrl0_ClkEn_1199 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0037,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ClkEn_FFY_RST,
      O => BScanCtrl0_ClkEn
    );
  BScanCtrl0_n00371 : X_LUT4
    generic map(
      INIT => X"1100"
    )
    port map (
      ADR0 => BScanCtrl0_vCount(0),
      ADR1 => BScanCtrl0_vCount(1),
      ADR2 => VCC,
      ADR3 => BScanCtrl0_vCount(2),
      O => BScanCtrl0_n0037
    );
  BScanCtrl0_ClkEn_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_ClkEn_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_IncRxCount2_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_IncRxCount2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_IncRxCount2_FFY_RST
    );
  BScanCtrl0_IncRxCount_1200 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0034,
      CE => BScanCtrl0_ClkEn,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_IncRxCount2_FFY_RST,
      O => BScanCtrl0_IncRxCount
    );
  BScanCtrl0_IncRxCount2_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_IncRxCount2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_IncRxCount2_FFX_RST
    );
  BScanCtrl0_IncRxCount2_1201 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_IncRxCount,
      CE => BScanCtrl0_ClkEn,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_IncRxCount2_FFX_RST,
      O => BScanCtrl0_IncRxCount2
    );
  BScanCtrl0_n0034135_SW0 : X_LUT4
    generic map(
      INIT => X"CC88"
    )
    port map (
      ADR0 => CHOICE648,
      ADR1 => CHOICE667,
      ADR2 => VCC,
      ADR3 => CHOICE659,
      O => BScanCtrl0_IncRxCount2_FROM
    );
  BScanCtrl0_n0034135 : X_LUT4
    generic map(
      INIT => X"0A08"
    )
    port map (
      ADR0 => BScanCtrl0_IncScanCount,
      ADR1 => CHOICE674,
      ADR2 => BScanCtrl0_BScanTrigger,
      ADR3 => N50611,
      O => BScanCtrl0_n0034
    );
  BScanCtrl0_IncRxCount2_XUSED : X_BUF
    port map (
      I => BScanCtrl0_IncRxCount2_FROM,
      O => N50611
    );
  BScanCtrl0_IncRxCount2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_IncRxCount2_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_IncScanCount_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_IncScanCount_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_IncScanCount_FFY_RST
    );
  BScanCtrl0_IncScanCount_1202 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0024,
      CE => BScanCtrl0_ClkEn,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_IncScanCount_FFY_RST,
      O => BScanCtrl0_IncScanCount
    );
  BScanCtrl0_n00851 : X_LUT4
    generic map(
      INIT => X"EC00"
    )
    port map (
      ADR0 => BScanCtrl0_RxActive,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_vRxCountDone,
      ADR3 => BScanCtrl0_ClkEn,
      O => BScanCtrl0_IncScanCount_FROM
    );
  BScanCtrl0_n00241 : X_LUT4
    generic map(
      INIT => X"EECC"
    )
    port map (
      ADR0 => BScanCtrl0_n0045,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RxActive,
      O => BScanCtrl0_n0024
    );
  BScanCtrl0_IncScanCount_XUSED : X_BUF
    port map (
      I => BScanCtrl0_IncScanCount_FROM,
      O => BScanCtrl0_n0085
    );
  BScanCtrl0_IncScanCount_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_IncScanCount_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ONE_1203 : X_ONE
    port map (
      O => BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ONE
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ZERO_1204 : X_ZERO
    port map (
      O => BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ZERO
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_70_1205 : X_MUX2
    port map (
      IA => BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ONE,
      SEL => BScanCtrl0_Mcompar_n0040_inst_lut4_40,
      O => BScanCtrl0_Mcompar_n0040_inst_cy_70
    );
  BScanCtrl0_Mcompar_n0040_inst_lut4_401 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_1,
      ADR1 => BScanCtrl0_ScanCount_40,
      ADR2 => BScanCtrl0_ScanCount_41,
      ADR3 => PerLBusInterface0_RegBank_5_0,
      O => BScanCtrl0_Mcompar_n0040_inst_lut4_40
    );
  BScanCtrl0_Mcompar_n0040_inst_lut4_411 : X_LUT4
    generic map(
      INIT => X"8421"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_5_3,
      ADR1 => BScanCtrl0_ScanCount_42,
      ADR2 => BScanCtrl0_ScanCount_43,
      ADR3 => PerLBusInterface0_RegBank_5_2,
      O => BScanCtrl0_Mcompar_n0040_inst_lut4_41
    );
  BScanCtrl0_Mcompar_n0040_inst_cy_71 : X_MUX2
    port map (
      IA => BScanCtrl0_Mcompar_n0040_inst_cy_71_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0040_inst_cy_70,
      SEL => BScanCtrl0_Mcompar_n0040_inst_lut4_41,
      O => BScanCtrl0_Mcompar_n0040_inst_cy_71_CYMUXG
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ONE_1206 : X_ONE
    port map (
      O => BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ONE
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ZERO_1207 : X_ZERO
    port map (
      O => BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ZERO
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_70_1208 : X_MUX2
    port map (
      IA => BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ONE,
      SEL => BScanCtrl0_Mcompar_n0041_inst_lut4_40,
      O => BScanCtrl0_Mcompar_n0041_inst_cy_70
    );
  BScanCtrl0_Mcompar_n0041_inst_lut4_401 : X_LUT4
    generic map(
      INIT => X"9009"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(0),
      ADR1 => PerLBusInterface0_RegBank_5_0,
      ADR2 => BScanCtrl0_RxCount(1),
      ADR3 => PerLBusInterface0_RegBank_5_1,
      O => BScanCtrl0_Mcompar_n0041_inst_lut4_40
    );
  BScanCtrl0_Mcompar_n0041_inst_lut4_411 : X_LUT4
    generic map(
      INIT => X"8241"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(2),
      ADR1 => BScanCtrl0_RxCount(3),
      ADR2 => PerLBusInterface0_RegBank_5_3,
      ADR3 => PerLBusInterface0_RegBank_5_2,
      O => BScanCtrl0_Mcompar_n0041_inst_lut4_41
    );
  BScanCtrl0_Mcompar_n0041_inst_cy_71 : X_MUX2
    port map (
      IA => BScanCtrl0_Mcompar_n0041_inst_cy_71_LOGIC_ZERO,
      IB => BScanCtrl0_Mcompar_n0041_inst_cy_70,
      SEL => BScanCtrl0_Mcompar_n0041_inst_lut4_41,
      O => BScanCtrl0_Mcompar_n0041_inst_cy_71_CYMUXG
    );
  BScanCtrl0_RepCount_11_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_11_FFX_RST
    );
  BScanCtrl0_RepCount_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_11_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_11_FFX_RST,
      O => BScanCtrl0_RepCount(11)
    );
  BScanCtrl0_RepCount_11_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_11_FFY_RST
    );
  BScanCtrl0_RepCount_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_10_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_11_FFY_RST,
      O => BScanCtrl0_RepCount(10)
    );
  BScanCtrl0_Mmux_n0023_Result_11_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => BScanCtrl0_n0088(11),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_11,
      O => BScanCtrl0_Mmux_n0023_Result_11_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_10_1 : X_LUT4
    generic map(
      INIT => X"AAF0"
    )
    port map (
      ADR0 => BScanCtrl0_n0088(10),
      ADR1 => VCC,
      ADR2 => PerLBusInterface0_RegBank_4_10,
      ADR3 => BScanCtrl0_n0058,
      O => BScanCtrl0_Mmux_n0023_Result_10_1_O
    );
  BScanCtrl0_RepCount_11_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_11_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_13_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_13_FFX_RST
    );
  BScanCtrl0_RepCount_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_13_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_13_FFX_RST,
      O => BScanCtrl0_RepCount(13)
    );
  BScanCtrl0_RepCount_13_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_13_FFY_RST
    );
  BScanCtrl0_RepCount_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_12_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_13_FFY_RST,
      O => BScanCtrl0_RepCount(12)
    );
  BScanCtrl0_Mmux_n0023_Result_13_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => BScanCtrl0_n0088(13),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_13,
      O => BScanCtrl0_Mmux_n0023_Result_13_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_12_1 : X_LUT4
    generic map(
      INIT => X"E4E4"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => PerLBusInterface0_RegBank_4_12,
      ADR2 => BScanCtrl0_n0088(12),
      ADR3 => VCC,
      O => BScanCtrl0_Mmux_n0023_Result_12_1_O
    );
  BScanCtrl0_RepCount_13_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_13_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_15_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_15_FFY_RST
    );
  BScanCtrl0_RepCount_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_14_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_15_FFY_RST,
      O => BScanCtrl0_RepCount(14)
    );
  BScanCtrl0_RepCount_15_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_15_FFX_RST
    );
  BScanCtrl0_RepCount_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_15_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_15_FFX_RST,
      O => BScanCtrl0_RepCount(15)
    );
  BScanCtrl0_Mmux_n0023_Result_15_1 : X_LUT4
    generic map(
      INIT => X"CCF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_n0088(15),
      ADR2 => PerLBusInterface0_RegBank_4_15,
      ADR3 => BScanCtrl0_n0058,
      O => BScanCtrl0_Mmux_n0023_Result_15_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_14_1 : X_LUT4
    generic map(
      INIT => X"BB88"
    )
    port map (
      ADR0 => BScanCtrl0_n0088(14),
      ADR1 => BScanCtrl0_n0058,
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_14,
      O => BScanCtrl0_Mmux_n0023_Result_14_1_O
    );
  BScanCtrl0_RepCount_15_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_15_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_16_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_16_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_16_FFY_RST
    );
  BScanCtrl0_RepCount_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_16_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_16_FFY_RST,
      O => BScanCtrl0_RepCount(16)
    );
  BScanCtrl0_Msub_n0044_inst_sum_83 : X_XOR2
    port map (
      I0 => BScanCtrl0_RepCount_16_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_43,
      O => BScanCtrl0_RepCount_16_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_431 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(16),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_43
    );
  BScanCtrl0_Mmux_n0023_Result_16_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => BScanCtrl0_n0088(16),
      ADR1 => PerLBusInterface0_RegBank_4_16,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_n0058,
      O => BScanCtrl0_Mmux_n0023_Result_16_1_O
    );
  BScanCtrl0_RepCount_16_XUSED : X_BUF
    port map (
      I => BScanCtrl0_RepCount_16_XORF,
      O => BScanCtrl0_n0088(16)
    );
  BScanCtrl0_RepCount_16_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_16_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_16_CYINIT_1209 : X_BUF
    port map (
      I => BScanCtrl0_n0088_14_CYMUXG,
      O => BScanCtrl0_RepCount_16_CYINIT
    );
  BScanCtrl0_RepCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_1_FFY_RST
    );
  BScanCtrl0_RepCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_0_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_1_FFY_RST,
      O => BScanCtrl0_RepCount(0)
    );
  BScanCtrl0_RepCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_1_FFX_RST
    );
  BScanCtrl0_RepCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_1_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_1_FFX_RST,
      O => BScanCtrl0_RepCount(1)
    );
  BScanCtrl0_Mmux_n0023_Result_1_1 : X_LUT4
    generic map(
      INIT => X"FC30"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_n0058,
      ADR2 => PerLBusInterface0_RegBank_4_1,
      ADR3 => BScanCtrl0_n0088(1),
      O => BScanCtrl0_Mmux_n0023_Result_1_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_0_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_n0088(0),
      ADR2 => BScanCtrl0_n0058,
      ADR3 => PerLBusInterface0_RegBank_4_0,
      O => BScanCtrl0_Mmux_n0023_Result_0_1_O
    );
  BScanCtrl0_RepCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_1_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_3_FFY_RST
    );
  BScanCtrl0_RepCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_2_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_3_FFY_RST,
      O => BScanCtrl0_RepCount(2)
    );
  BScanCtrl0_RepCount_3_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_3_FFX_RST
    );
  BScanCtrl0_RepCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_3_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_3_FFX_RST,
      O => BScanCtrl0_RepCount(3)
    );
  BScanCtrl0_Mmux_n0023_Result_3_1 : X_LUT4
    generic map(
      INIT => X"E2E2"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_4_3,
      ADR1 => BScanCtrl0_n0058,
      ADR2 => BScanCtrl0_n0088(3),
      ADR3 => VCC,
      O => BScanCtrl0_Mmux_n0023_Result_3_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_2_1 : X_LUT4
    generic map(
      INIT => X"F5A0"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_n0088(2),
      ADR3 => PerLBusInterface0_RegBank_4_2,
      O => BScanCtrl0_Mmux_n0023_Result_2_1_O
    );
  BScanCtrl0_RepCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_3_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_5_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_5_FFY_RST
    );
  BScanCtrl0_RepCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_4_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_5_FFY_RST,
      O => BScanCtrl0_RepCount(4)
    );
  BScanCtrl0_RepCount_5_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_5_FFX_RST
    );
  BScanCtrl0_RepCount_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_5_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_5_FFX_RST,
      O => BScanCtrl0_RepCount(5)
    );
  BScanCtrl0_Mmux_n0023_Result_5_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => BScanCtrl0_n0088(5),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_5,
      O => BScanCtrl0_Mmux_n0023_Result_5_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_4_1 : X_LUT4
    generic map(
      INIT => X"CCAA"
    )
    port map (
      ADR0 => PerLBusInterface0_RegBank_4_4,
      ADR1 => BScanCtrl0_n0088(4),
      ADR2 => VCC,
      ADR3 => BScanCtrl0_n0058,
      O => BScanCtrl0_Mmux_n0023_Result_4_1_O
    );
  BScanCtrl0_RepCount_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_5_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_7_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_7_FFX_RST
    );
  BScanCtrl0_RepCount_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_7_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_7_FFX_RST,
      O => BScanCtrl0_RepCount(7)
    );
  BScanCtrl0_RepCount_7_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_7_FFY_RST
    );
  BScanCtrl0_RepCount_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_6_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_7_FFY_RST,
      O => BScanCtrl0_RepCount(6)
    );
  BScanCtrl0_Mmux_n0023_Result_7_1 : X_LUT4
    generic map(
      INIT => X"D8D8"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => BScanCtrl0_n0088(7),
      ADR2 => PerLBusInterface0_RegBank_4_7,
      ADR3 => VCC,
      O => BScanCtrl0_Mmux_n0023_Result_7_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_6_1 : X_LUT4
    generic map(
      INIT => X"DD88"
    )
    port map (
      ADR0 => BScanCtrl0_n0058,
      ADR1 => BScanCtrl0_n0088(6),
      ADR2 => VCC,
      ADR3 => PerLBusInterface0_RegBank_4_6,
      O => BScanCtrl0_Mmux_n0023_Result_6_1_O
    );
  BScanCtrl0_RepCount_7_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_7_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RepCount_9_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_9_FFY_RST
    );
  BScanCtrl0_RepCount_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_8_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_9_FFY_RST,
      O => BScanCtrl0_RepCount(8)
    );
  BScanCtrl0_RepCount_9_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RepCount_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RepCount_9_FFX_RST
    );
  BScanCtrl0_RepCount_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_Mmux_n0023_Result_9_1_O,
      CE => BScanCtrl0_n0081,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RepCount_9_FFX_RST,
      O => BScanCtrl0_RepCount(9)
    );
  BScanCtrl0_Mmux_n0023_Result_9_1 : X_LUT4
    generic map(
      INIT => X"CFC0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_n0088(9),
      ADR2 => BScanCtrl0_n0058,
      ADR3 => PerLBusInterface0_RegBank_4_9,
      O => BScanCtrl0_Mmux_n0023_Result_9_1_O
    );
  BScanCtrl0_Mmux_n0023_Result_8_1 : X_LUT4
    generic map(
      INIT => X"AACC"
    )
    port map (
      ADR0 => BScanCtrl0_n0088(8),
      ADR1 => PerLBusInterface0_RegBank_4_8,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_n0058,
      O => BScanCtrl0_Mmux_n0023_Result_8_1_O
    );
  BScanCtrl0_RepCount_9_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RepCount_9_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RxActive_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxActive_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxActive_FFY_RST
    );
  BScanCtrl0_RxActive_1210 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0031,
      CE => BScanCtrl0_n0085,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxActive_FFY_RST,
      O => BScanCtrl0_RxActive
    );
  BScanCtrl0_RxActive_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_RxActive_FROM
    );
  BScanCtrl0_n00311 : X_LUT4
    generic map(
      INIT => X"3F3F"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_vRxCountDone,
      ADR2 => BScanCtrl0_RxActive,
      ADR3 => VCC,
      O => BScanCtrl0_n0031
    );
  BScanCtrl0_RxActive_XUSED : X_BUF
    port map (
      I => BScanCtrl0_RxActive_FROM,
      O => BScanCtrl0_RxActive_X
    );
  BScanCtrl0_RxActive_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RxActive_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RxCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_1_FFY_RST
    );
  BScanCtrl0_RxCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(0),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_1_FFY_RST,
      O => BScanCtrl0_RxCount(0)
    );
  BScanCtrl0_RxCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_1_FFX_RST
    );
  BScanCtrl0_RxCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(1),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_1_FFX_RST,
      O => BScanCtrl0_RxCount(1)
    );
  BScanCtrl0_n0033_1_1 : X_LUT4
    generic map(
      INIT => X"C0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_IncRxCount2,
      ADR2 => BScanCtrl0_n0048(1),
      ADR3 => VCC,
      O => BScanCtrl0_n0033(1)
    );
  BScanCtrl0_n0033_0_1 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(0),
      ADR1 => VCC,
      ADR2 => BScanCtrl0_IncRxCount2,
      ADR3 => VCC,
      O => BScanCtrl0_n0033(0)
    );
  BScanCtrl0_RxCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RxCount_1_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RxCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_3_FFY_RST
    );
  BScanCtrl0_RxCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(2),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_3_FFY_RST,
      O => BScanCtrl0_RxCount(2)
    );
  BScanCtrl0_RxCount_3_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_3_FFX_RST
    );
  BScanCtrl0_RxCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(3),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_3_FFX_RST,
      O => BScanCtrl0_RxCount(3)
    );
  BScanCtrl0_n0033_3_1 : X_LUT4
    generic map(
      INIT => X"A0A0"
    )
    port map (
      ADR0 => BScanCtrl0_n0048(3),
      ADR1 => VCC,
      ADR2 => BScanCtrl0_IncRxCount2,
      ADR3 => VCC,
      O => BScanCtrl0_n0033(3)
    );
  BScanCtrl0_n0033_2_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => BScanCtrl0_IncRxCount2,
      ADR1 => BScanCtrl0_n0048(2),
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_n0033(2)
    );
  BScanCtrl0_RxCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RxCount_3_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RxCount_5_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_5_FFY_RST
    );
  BScanCtrl0_RxCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(4),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_5_FFY_RST,
      O => BScanCtrl0_RxCount(4)
    );
  BScanCtrl0_RxCount_5_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_5_FFX_RST
    );
  BScanCtrl0_RxCount_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(5),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_5_FFX_RST,
      O => BScanCtrl0_RxCount(5)
    );
  BScanCtrl0_n0033_5_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_IncRxCount2,
      ADR3 => BScanCtrl0_n0048(5),
      O => BScanCtrl0_n0033(5)
    );
  BScanCtrl0_n0033_4_1 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_n0048(4),
      ADR3 => BScanCtrl0_IncRxCount2,
      O => BScanCtrl0_n0033(4)
    );
  BScanCtrl0_RxCount_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RxCount_5_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_RxCount_6_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_RxCount_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_RxCount_6_FFY_RST
    );
  BScanCtrl0_RxCount_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0033(6),
      CE => BScanCtrl0_n0087,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_RxCount_6_FFY_RST,
      O => BScanCtrl0_RxCount(6)
    );
  BScanCtrl0_n00871 : X_LUT4
    generic map(
      INIT => X"F0C0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_ClkEn,
      ADR3 => BScanCtrl0_IncRxCount2,
      O => BScanCtrl0_RxCount_6_FROM
    );
  BScanCtrl0_n0033_6_1 : X_LUT4
    generic map(
      INIT => X"8888"
    )
    port map (
      ADR0 => BScanCtrl0_n0048(6),
      ADR1 => BScanCtrl0_IncRxCount2,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_n0033(6)
    );
  BScanCtrl0_RxCount_6_XUSED : X_BUF
    port map (
      I => BScanCtrl0_RxCount_6_FROM,
      O => BScanCtrl0_n0087
    );
  BScanCtrl0_RxCount_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_RxCount_6_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ScanCount_40_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_40_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_40_FFY_RST
    );
  BScanCtrl0_ScanCount_40_1211 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_84,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_40_FFY_RST,
      O => BScanCtrl0_ScanCount_40
    );
  BScanCtrl0_ScanCount_40_LOGIC_ZERO_1212 : X_ZERO
    port map (
      O => BScanCtrl0_ScanCount_40_LOGIC_ZERO
    );
  BScanCtrl0_ScanCount_inst_cy_98_1213 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => BScanCtrl0_ScanCount_40_LOGIC_ZERO,
      SEL => BScanCtrl0_BScanTrigger_rt,
      O => BScanCtrl0_ScanCount_inst_cy_98
    );
  BScanCtrl0_BScanTrigger_rt_1214 : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_BScanTrigger,
      O => BScanCtrl0_BScanTrigger_rt
    );
  BScanCtrl0_ScanCount_inst_lut3_111 : X_LUT4
    generic map(
      INIT => X"00F0"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => BScanCtrl0_ScanCount_40,
      ADR3 => BScanCtrl0_BScanTrigger,
      O => BScanCtrl0_ScanCount_inst_lut3_11
    );
  BScanCtrl0_ScanCount_inst_cy_99 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => BScanCtrl0_ScanCount_inst_cy_98,
      SEL => BScanCtrl0_ScanCount_inst_lut3_11,
      O => BScanCtrl0_ScanCount_40_CYMUXG
    );
  BScanCtrl0_ScanCount_inst_sum_84_1215 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_inst_cy_98,
      I1 => BScanCtrl0_ScanCount_inst_lut3_11,
      O => BScanCtrl0_ScanCount_inst_sum_84
    );
  BScanCtrl0_ScanCount_40_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_ScanCount_40_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ScanCount_41_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_41_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_41_FFY_RST
    );
  BScanCtrl0_ScanCount_42_1216 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_86,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_41_FFY_RST,
      O => BScanCtrl0_ScanCount_42
    );
  BScanCtrl0_ScanCount_41_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_41_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_41_FFX_RST
    );
  BScanCtrl0_ScanCount_41_1217 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_85,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_41_FFX_RST,
      O => BScanCtrl0_ScanCount_41
    );
  BScanCtrl0_ScanCount_41_LOGIC_ZERO_1218 : X_ZERO
    port map (
      O => BScanCtrl0_ScanCount_41_LOGIC_ZERO
    );
  BScanCtrl0_ScanCount_inst_cy_100_1219 : X_MUX2
    port map (
      IA => BScanCtrl0_ScanCount_41_LOGIC_ZERO,
      IB => BScanCtrl0_ScanCount_41_CYINIT,
      SEL => BScanCtrl0_ScanCount_inst_lut3_12,
      O => BScanCtrl0_ScanCount_inst_cy_100
    );
  BScanCtrl0_ScanCount_inst_sum_85_1220 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_41_CYINIT,
      I1 => BScanCtrl0_ScanCount_inst_lut3_12,
      O => BScanCtrl0_ScanCount_inst_sum_85
    );
  BScanCtrl0_ScanCount_inst_lut3_121 : X_LUT4
    generic map(
      INIT => X"5500"
    )
    port map (
      ADR0 => BScanCtrl0_BScanTrigger,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_ScanCount_41,
      O => BScanCtrl0_ScanCount_inst_lut3_12
    );
  BScanCtrl0_ScanCount_inst_lut3_131 : X_LUT4
    generic map(
      INIT => X"3030"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_ScanCount_42,
      ADR3 => VCC,
      O => BScanCtrl0_ScanCount_inst_lut3_13
    );
  BScanCtrl0_ScanCount_inst_cy_101 : X_MUX2
    port map (
      IA => BScanCtrl0_ScanCount_41_LOGIC_ZERO,
      IB => BScanCtrl0_ScanCount_inst_cy_100,
      SEL => BScanCtrl0_ScanCount_inst_lut3_13,
      O => BScanCtrl0_ScanCount_41_CYMUXG
    );
  BScanCtrl0_ScanCount_inst_sum_86_1221 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_inst_cy_100,
      I1 => BScanCtrl0_ScanCount_inst_lut3_13,
      O => BScanCtrl0_ScanCount_inst_sum_86
    );
  BScanCtrl0_ScanCount_41_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_ScanCount_41_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ScanCount_41_CYINIT_1222 : X_BUF
    port map (
      I => BScanCtrl0_ScanCount_40_CYMUXG,
      O => BScanCtrl0_ScanCount_41_CYINIT
    );
  BScanCtrl0_ScanCount_43_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_43_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_43_FFY_RST
    );
  BScanCtrl0_ScanCount_44_1223 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_88,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_43_FFY_RST,
      O => BScanCtrl0_ScanCount_44
    );
  BScanCtrl0_ScanCount_43_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_43_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_43_FFX_RST
    );
  BScanCtrl0_ScanCount_43_1224 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_87,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_43_FFX_RST,
      O => BScanCtrl0_ScanCount_43
    );
  BScanCtrl0_ScanCount_43_LOGIC_ZERO_1225 : X_ZERO
    port map (
      O => BScanCtrl0_ScanCount_43_LOGIC_ZERO
    );
  BScanCtrl0_ScanCount_inst_cy_102_1226 : X_MUX2
    port map (
      IA => BScanCtrl0_ScanCount_43_LOGIC_ZERO,
      IB => BScanCtrl0_ScanCount_43_CYINIT,
      SEL => BScanCtrl0_ScanCount_inst_lut3_14,
      O => BScanCtrl0_ScanCount_inst_cy_102
    );
  BScanCtrl0_ScanCount_inst_sum_87_1227 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_43_CYINIT,
      I1 => BScanCtrl0_ScanCount_inst_lut3_14,
      O => BScanCtrl0_ScanCount_inst_sum_87
    );
  BScanCtrl0_ScanCount_inst_lut3_141 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => BScanCtrl0_BScanTrigger,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_ScanCount_43,
      ADR3 => VCC,
      O => BScanCtrl0_ScanCount_inst_lut3_14
    );
  BScanCtrl0_ScanCount_inst_lut3_151 : X_LUT4
    generic map(
      INIT => X"4444"
    )
    port map (
      ADR0 => BScanCtrl0_BScanTrigger,
      ADR1 => BScanCtrl0_ScanCount_44,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_ScanCount_inst_lut3_15
    );
  BScanCtrl0_ScanCount_inst_cy_103 : X_MUX2
    port map (
      IA => BScanCtrl0_ScanCount_43_LOGIC_ZERO,
      IB => BScanCtrl0_ScanCount_inst_cy_102,
      SEL => BScanCtrl0_ScanCount_inst_lut3_15,
      O => BScanCtrl0_ScanCount_43_CYMUXG
    );
  BScanCtrl0_ScanCount_inst_sum_88_1228 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_inst_cy_102,
      I1 => BScanCtrl0_ScanCount_inst_lut3_15,
      O => BScanCtrl0_ScanCount_inst_sum_88
    );
  BScanCtrl0_ScanCount_43_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_ScanCount_43_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ScanCount_43_CYINIT_1229 : X_BUF
    port map (
      I => BScanCtrl0_ScanCount_41_CYMUXG,
      O => BScanCtrl0_ScanCount_43_CYINIT
    );
  BScanCtrl0_ScanCount_45_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_45_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_45_FFX_RST
    );
  BScanCtrl0_ScanCount_45_1230 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_89,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_45_FFX_RST,
      O => BScanCtrl0_ScanCount_45
    );
  BScanCtrl0_ScanCount_45_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_ScanCount_45_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_ScanCount_45_FFY_RST
    );
  BScanCtrl0_ScanCount_46_1231 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_inst_sum_90,
      CE => BScanCtrl0_n0082,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_ScanCount_45_FFY_RST,
      O => BScanCtrl0_ScanCount_46
    );
  BScanCtrl0_ScanCount_45_LOGIC_ZERO_1232 : X_ZERO
    port map (
      O => BScanCtrl0_ScanCount_45_LOGIC_ZERO
    );
  BScanCtrl0_ScanCount_inst_cy_104_1233 : X_MUX2
    port map (
      IA => BScanCtrl0_ScanCount_45_LOGIC_ZERO,
      IB => BScanCtrl0_ScanCount_45_CYINIT,
      SEL => BScanCtrl0_ScanCount_inst_lut3_16,
      O => BScanCtrl0_ScanCount_inst_cy_104
    );
  BScanCtrl0_ScanCount_inst_sum_89_1234 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_45_CYINIT,
      I1 => BScanCtrl0_ScanCount_inst_lut3_16,
      O => BScanCtrl0_ScanCount_inst_sum_89
    );
  BScanCtrl0_ScanCount_inst_lut3_161 : X_LUT4
    generic map(
      INIT => X"5050"
    )
    port map (
      ADR0 => BScanCtrl0_BScanTrigger,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_ScanCount_45,
      ADR3 => VCC,
      O => BScanCtrl0_ScanCount_inst_lut3_16
    );
  BScanCtrl0_ScanCount_inst_lut3_171 : X_LUT4
    generic map(
      INIT => X"00AA"
    )
    port map (
      ADR0 => BScanCtrl0_ScanCount_46,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_BScanTrigger,
      O => BScanCtrl0_ScanCount_inst_lut3_17
    );
  BScanCtrl0_ScanCount_inst_sum_90_1235 : X_XOR2
    port map (
      I0 => BScanCtrl0_ScanCount_inst_cy_104,
      I1 => BScanCtrl0_ScanCount_inst_lut3_17,
      O => BScanCtrl0_ScanCount_inst_sum_90
    );
  BScanCtrl0_ScanCount_45_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_ScanCount_45_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_ScanCount_45_CYINIT_1236 : X_BUF
    port map (
      I => BScanCtrl0_ScanCount_43_CYMUXG,
      O => BScanCtrl0_ScanCount_45_CYINIT
    );
  BScanCtrl0_n004584 : X_LUT4
    generic map(
      INIT => X"8000"
    )
    port map (
      ADR0 => CHOICE793,
      ADR1 => CHOICE817,
      ADR2 => CHOICE808,
      ADR3 => CHOICE800,
      O => BScanCtrl0_n0045_FROM
    );
  BScanCtrl0_n00811 : X_LUT4
    generic map(
      INIT => X"A8AA"
    )
    port map (
      ADR0 => BScanCtrl0_ClkEn,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_RxActive,
      ADR3 => BScanCtrl0_n0045,
      O => BScanCtrl0_n0045_GROM
    );
  BScanCtrl0_n0045_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0045_FROM,
      O => BScanCtrl0_n0045
    );
  BScanCtrl0_n0045_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0045_GROM,
      O => BScanCtrl0_n0081
    );
  BScanCtrl0_n004526 : X_LUT4
    generic map(
      INIT => X"CC00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => CHOICE793,
      ADR2 => VCC,
      ADR3 => CHOICE800,
      O => BScanCtrl0_n004526_O_FROM
    );
  BScanCtrl0_n00581 : X_LUT4
    generic map(
      INIT => X"070F"
    )
    port map (
      ADR0 => CHOICE808,
      ADR1 => CHOICE817,
      ADR2 => BScanCtrl0_BScanTrigger,
      ADR3 => BScanCtrl0_n004526_O,
      O => BScanCtrl0_n004526_O_GROM
    );
  BScanCtrl0_n004526_O_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n004526_O_FROM,
      O => BScanCtrl0_n004526_O
    );
  BScanCtrl0_n004526_O_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n004526_O_GROM,
      O => BScanCtrl0_n0058
    );
  BScanCtrl0_n004553 : X_LUT4
    generic map(
      INIT => X"1111"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(16),
      ADR1 => BScanCtrl0_RepCount(9),
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_n004553_O_FROM
    );
  BScanCtrl0_n004567 : X_LUT4
    generic map(
      INIT => X"0100"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(1),
      ADR1 => BScanCtrl0_RepCount(14),
      ADR2 => BScanCtrl0_RepCount(0),
      ADR3 => BScanCtrl0_n004553_O,
      O => BScanCtrl0_n004553_O_GROM
    );
  BScanCtrl0_n004553_O_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n004553_O_FROM,
      O => BScanCtrl0_n004553_O
    );
  BScanCtrl0_n004553_O_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n004553_O_GROM,
      O => CHOICE817
    );
  BScanCtrl0_n0048_1_LOGIC_ZERO_1237 : X_ZERO
    port map (
      O => BScanCtrl0_n0048_1_LOGIC_ZERO
    );
  BScanCtrl0_Madd_n0048_inst_cy_74_1238 : X_MUX2
    port map (
      IA => pLED_D9_OBUF,
      IB => BScanCtrl0_n0048_1_LOGIC_ZERO,
      SEL => BScanCtrl0_Madd_n0048_inst_lut2_20,
      O => BScanCtrl0_Madd_n0048_inst_cy_74
    );
  BScanCtrl0_Madd_n0048_inst_lut2_201 : X_LUT4
    generic map(
      INIT => X"00FF"
    )
    port map (
      ADR0 => pLED_D9_OBUF,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RxCount(0),
      O => BScanCtrl0_Madd_n0048_inst_lut2_20
    );
  BScanCtrl0_n0048_1_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RxCount(1),
      O => BScanCtrl0_n0048_1_GROM
    );
  BScanCtrl0_n0048_1_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_1_XORG,
      O => BScanCtrl0_n0048(1)
    );
  BScanCtrl0_Madd_n0048_inst_cy_75 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => BScanCtrl0_Madd_n0048_inst_cy_74,
      SEL => BScanCtrl0_n0048_1_GROM,
      O => BScanCtrl0_n0048_1_CYMUXG
    );
  BScanCtrl0_Madd_n0048_inst_sum_61 : X_XOR2
    port map (
      I0 => BScanCtrl0_Madd_n0048_inst_cy_74,
      I1 => BScanCtrl0_n0048_1_GROM,
      O => BScanCtrl0_n0048_1_XORG
    );
  BScanCtrl0_n0048_2_LOGIC_ZERO_1239 : X_ZERO
    port map (
      O => BScanCtrl0_n0048_2_LOGIC_ZERO
    );
  BScanCtrl0_Madd_n0048_inst_cy_76_1240 : X_MUX2
    port map (
      IA => BScanCtrl0_n0048_2_LOGIC_ZERO,
      IB => BScanCtrl0_n0048_2_CYINIT,
      SEL => BScanCtrl0_n0048_2_FROM,
      O => BScanCtrl0_Madd_n0048_inst_cy_76
    );
  BScanCtrl0_Madd_n0048_inst_sum_62 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0048_2_CYINIT,
      I1 => BScanCtrl0_n0048_2_FROM,
      O => BScanCtrl0_n0048_2_XORF
    );
  BScanCtrl0_n0048_2_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RxCount(2),
      O => BScanCtrl0_n0048_2_FROM
    );
  BScanCtrl0_n0048_2_G : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_RxCount(3),
      ADR3 => VCC,
      O => BScanCtrl0_n0048_2_GROM
    );
  BScanCtrl0_n0048_2_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_2_XORF,
      O => BScanCtrl0_n0048(2)
    );
  BScanCtrl0_n0048_2_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_2_XORG,
      O => BScanCtrl0_n0048(3)
    );
  BScanCtrl0_Madd_n0048_inst_cy_77 : X_MUX2
    port map (
      IA => BScanCtrl0_n0048_2_LOGIC_ZERO,
      IB => BScanCtrl0_Madd_n0048_inst_cy_76,
      SEL => BScanCtrl0_n0048_2_GROM,
      O => BScanCtrl0_n0048_2_CYMUXG
    );
  BScanCtrl0_Madd_n0048_inst_sum_63 : X_XOR2
    port map (
      I0 => BScanCtrl0_Madd_n0048_inst_cy_76,
      I1 => BScanCtrl0_n0048_2_GROM,
      O => BScanCtrl0_n0048_2_XORG
    );
  BScanCtrl0_n0048_2_CYINIT_1241 : X_BUF
    port map (
      I => BScanCtrl0_n0048_1_CYMUXG,
      O => BScanCtrl0_n0048_2_CYINIT
    );
  BScanCtrl0_n0048_4_LOGIC_ZERO_1242 : X_ZERO
    port map (
      O => BScanCtrl0_n0048_4_LOGIC_ZERO
    );
  BScanCtrl0_Madd_n0048_inst_cy_78_1243 : X_MUX2
    port map (
      IA => BScanCtrl0_n0048_4_LOGIC_ZERO,
      IB => BScanCtrl0_n0048_4_CYINIT,
      SEL => BScanCtrl0_n0048_4_FROM,
      O => BScanCtrl0_Madd_n0048_inst_cy_78
    );
  BScanCtrl0_Madd_n0048_inst_sum_64 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0048_4_CYINIT,
      I1 => BScanCtrl0_n0048_4_FROM,
      O => BScanCtrl0_n0048_4_XORF
    );
  BScanCtrl0_n0048_4_F : X_LUT4
    generic map(
      INIT => X"F0F0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_RxCount(4),
      ADR3 => VCC,
      O => BScanCtrl0_n0048_4_FROM
    );
  BScanCtrl0_n0048_4_G : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RxCount(5),
      O => BScanCtrl0_n0048_4_GROM
    );
  BScanCtrl0_n0048_4_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_4_XORF,
      O => BScanCtrl0_n0048(4)
    );
  BScanCtrl0_n0048_4_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_4_XORG,
      O => BScanCtrl0_n0048(5)
    );
  BScanCtrl0_Madd_n0048_inst_cy_79 : X_MUX2
    port map (
      IA => BScanCtrl0_n0048_4_LOGIC_ZERO,
      IB => BScanCtrl0_Madd_n0048_inst_cy_78,
      SEL => BScanCtrl0_n0048_4_GROM,
      O => BScanCtrl0_n0048_4_CYMUXG
    );
  BScanCtrl0_Madd_n0048_inst_sum_65 : X_XOR2
    port map (
      I0 => BScanCtrl0_Madd_n0048_inst_cy_78,
      I1 => BScanCtrl0_n0048_4_GROM,
      O => BScanCtrl0_n0048_4_XORG
    );
  BScanCtrl0_n0048_4_CYINIT_1244 : X_BUF
    port map (
      I => BScanCtrl0_n0048_2_CYMUXG,
      O => BScanCtrl0_n0048_4_CYINIT
    );
  BScanCtrl0_Madd_n0048_inst_sum_66 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0048_6_CYINIT,
      I1 => BScanCtrl0_RxCount_6_rt,
      O => BScanCtrl0_n0048_6_XORF
    );
  BScanCtrl0_RxCount_6_rt_1245 : X_LUT4
    generic map(
      INIT => X"AAAA"
    )
    port map (
      ADR0 => BScanCtrl0_RxCount(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_RxCount_6_rt
    );
  BScanCtrl0_n0048_6_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0048_6_XORF,
      O => BScanCtrl0_n0048(6)
    );
  BScanCtrl0_n0048_6_CYINIT_1246 : X_BUF
    port map (
      I => BScanCtrl0_n0048_4_CYMUXG,
      O => BScanCtrl0_n0048_6_CYINIT
    );
  BScanCtrl0_n0088_0_LOGIC_ONE_1247 : X_ONE
    port map (
      O => BScanCtrl0_n0088_0_LOGIC_ONE
    );
  BScanCtrl0_Msub_n0044_inst_cy_81_1248 : X_MUX2
    port map (
      IA => EncoderMonitor0_EncoderReset(3),
      IB => BScanCtrl0_n0088_0_CYINIT,
      SEL => BScanCtrl0_n0088_0_FROM,
      O => BScanCtrl0_Msub_n0044_inst_cy_81
    );
  BScanCtrl0_Msub_n0044_inst_sum_67 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_0_CYINIT,
      I1 => BScanCtrl0_n0088_0_FROM,
      O => BScanCtrl0_n0088_0_XORF
    );
  BScanCtrl0_n0088_0_F : X_LUT4
    generic map(
      INIT => X"FF00"
    )
    port map (
      ADR0 => EncoderMonitor0_EncoderReset(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => BScanCtrl0_RepCount(0),
      O => BScanCtrl0_n0088_0_FROM
    );
  BScanCtrl0_Msub_n0044_inst_lut2_281 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(1),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_28
    );
  BScanCtrl0_n0088_0_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_0_XORF,
      O => BScanCtrl0_n0088(0)
    );
  BScanCtrl0_n0088_0_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_0_XORG,
      O => BScanCtrl0_n0088(1)
    );
  BScanCtrl0_Msub_n0044_inst_cy_82 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(1),
      IB => BScanCtrl0_Msub_n0044_inst_cy_81,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_28,
      O => BScanCtrl0_n0088_0_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_68 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_81,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_28,
      O => BScanCtrl0_n0088_0_XORG
    );
  BScanCtrl0_n0088_0_CYINIT_1249 : X_BUF
    port map (
      I => BScanCtrl0_n0088_0_LOGIC_ONE,
      O => BScanCtrl0_n0088_0_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_91_1250 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(10),
      IB => BScanCtrl0_n0088_10_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_37,
      O => BScanCtrl0_Msub_n0044_inst_cy_91
    );
  BScanCtrl0_Msub_n0044_inst_sum_77 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_10_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_37,
      O => BScanCtrl0_n0088_10_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_371 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(10),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_37
    );
  BScanCtrl0_Msub_n0044_inst_lut2_381 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(11),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_38
    );
  BScanCtrl0_n0088_10_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_10_XORF,
      O => BScanCtrl0_n0088(10)
    );
  BScanCtrl0_n0088_10_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_10_XORG,
      O => BScanCtrl0_n0088(11)
    );
  BScanCtrl0_Msub_n0044_inst_cy_92 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(11),
      IB => BScanCtrl0_Msub_n0044_inst_cy_91,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_38,
      O => BScanCtrl0_n0088_10_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_78 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_91,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_38,
      O => BScanCtrl0_n0088_10_XORG
    );
  BScanCtrl0_n0088_10_CYINIT_1251 : X_BUF
    port map (
      I => BScanCtrl0_n0088_8_CYMUXG,
      O => BScanCtrl0_n0088_10_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_93_1252 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(12),
      IB => BScanCtrl0_n0088_12_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_39,
      O => BScanCtrl0_Msub_n0044_inst_cy_93
    );
  BScanCtrl0_Msub_n0044_inst_sum_79 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_12_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_39,
      O => BScanCtrl0_n0088_12_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_391 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(12),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_39
    );
  BScanCtrl0_Msub_n0044_inst_lut2_401 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(13),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_40
    );
  BScanCtrl0_n0088_12_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_12_XORF,
      O => BScanCtrl0_n0088(12)
    );
  BScanCtrl0_n0088_12_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_12_XORG,
      O => BScanCtrl0_n0088(13)
    );
  BScanCtrl0_Msub_n0044_inst_cy_94 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(13),
      IB => BScanCtrl0_Msub_n0044_inst_cy_93,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_40,
      O => BScanCtrl0_n0088_12_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_80 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_93,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_40,
      O => BScanCtrl0_n0088_12_XORG
    );
  BScanCtrl0_n0088_12_CYINIT_1253 : X_BUF
    port map (
      I => BScanCtrl0_n0088_10_CYMUXG,
      O => BScanCtrl0_n0088_12_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_95_1254 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(14),
      IB => BScanCtrl0_n0088_14_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_41,
      O => BScanCtrl0_Msub_n0044_inst_cy_95
    );
  BScanCtrl0_Msub_n0044_inst_sum_81 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_14_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_41,
      O => BScanCtrl0_n0088_14_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_411 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(14),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_41
    );
  BScanCtrl0_Msub_n0044_inst_lut2_421 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(15),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_42
    );
  BScanCtrl0_n0088_14_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_14_XORF,
      O => BScanCtrl0_n0088(14)
    );
  BScanCtrl0_n0088_14_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_14_XORG,
      O => BScanCtrl0_n0088(15)
    );
  BScanCtrl0_Msub_n0044_inst_cy_96 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(15),
      IB => BScanCtrl0_Msub_n0044_inst_cy_95,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_42,
      O => BScanCtrl0_n0088_14_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_82 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_95,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_42,
      O => BScanCtrl0_n0088_14_XORG
    );
  BScanCtrl0_n0088_14_CYINIT_1255 : X_BUF
    port map (
      I => BScanCtrl0_n0088_12_CYMUXG,
      O => BScanCtrl0_n0088_14_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_83_1256 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(2),
      IB => BScanCtrl0_n0088_2_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_29,
      O => BScanCtrl0_Msub_n0044_inst_cy_83
    );
  BScanCtrl0_Msub_n0044_inst_sum_69 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_2_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_29,
      O => BScanCtrl0_n0088_2_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_291 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(2),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_29
    );
  BScanCtrl0_Msub_n0044_inst_lut2_301 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(3),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_30
    );
  BScanCtrl0_n0088_2_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_2_XORF,
      O => BScanCtrl0_n0088(2)
    );
  BScanCtrl0_n0088_2_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_2_XORG,
      O => BScanCtrl0_n0088(3)
    );
  BScanCtrl0_Msub_n0044_inst_cy_84 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(3),
      IB => BScanCtrl0_Msub_n0044_inst_cy_83,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_30,
      O => BScanCtrl0_n0088_2_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_70 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_83,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_30,
      O => BScanCtrl0_n0088_2_XORG
    );
  BScanCtrl0_n0088_2_CYINIT_1257 : X_BUF
    port map (
      I => BScanCtrl0_n0088_0_CYMUXG,
      O => BScanCtrl0_n0088_2_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_85_1258 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(4),
      IB => BScanCtrl0_n0088_4_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_31,
      O => BScanCtrl0_Msub_n0044_inst_cy_85
    );
  BScanCtrl0_Msub_n0044_inst_sum_71 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_4_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_31,
      O => BScanCtrl0_n0088_4_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_311 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(4),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_31
    );
  BScanCtrl0_Msub_n0044_inst_lut2_321 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(5),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_32
    );
  BScanCtrl0_n0088_4_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_4_XORF,
      O => BScanCtrl0_n0088(4)
    );
  BScanCtrl0_n0088_4_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_4_XORG,
      O => BScanCtrl0_n0088(5)
    );
  BScanCtrl0_Msub_n0044_inst_cy_86 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(5),
      IB => BScanCtrl0_Msub_n0044_inst_cy_85,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_32,
      O => BScanCtrl0_n0088_4_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_72 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_85,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_32,
      O => BScanCtrl0_n0088_4_XORG
    );
  BScanCtrl0_n0088_4_CYINIT_1259 : X_BUF
    port map (
      I => BScanCtrl0_n0088_2_CYMUXG,
      O => BScanCtrl0_n0088_4_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_87_1260 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(6),
      IB => BScanCtrl0_n0088_6_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_33,
      O => BScanCtrl0_Msub_n0044_inst_cy_87
    );
  BScanCtrl0_Msub_n0044_inst_sum_73 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_6_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_33,
      O => BScanCtrl0_n0088_6_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_331 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(6),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_33
    );
  BScanCtrl0_Msub_n0044_inst_lut2_341 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(7),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_34
    );
  BScanCtrl0_n0088_6_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_6_XORF,
      O => BScanCtrl0_n0088(6)
    );
  BScanCtrl0_n0088_6_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_6_XORG,
      O => BScanCtrl0_n0088(7)
    );
  BScanCtrl0_Msub_n0044_inst_cy_88 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(7),
      IB => BScanCtrl0_Msub_n0044_inst_cy_87,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_34,
      O => BScanCtrl0_n0088_6_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_74 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_87,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_34,
      O => BScanCtrl0_n0088_6_XORG
    );
  BScanCtrl0_n0088_6_CYINIT_1261 : X_BUF
    port map (
      I => BScanCtrl0_n0088_4_CYMUXG,
      O => BScanCtrl0_n0088_6_CYINIT
    );
  BScanCtrl0_Msub_n0044_inst_cy_89_1262 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(8),
      IB => BScanCtrl0_n0088_8_CYINIT,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_35,
      O => BScanCtrl0_Msub_n0044_inst_cy_89
    );
  BScanCtrl0_Msub_n0044_inst_sum_75 : X_XOR2
    port map (
      I0 => BScanCtrl0_n0088_8_CYINIT,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_35,
      O => BScanCtrl0_n0088_8_XORF
    );
  BScanCtrl0_Msub_n0044_inst_lut2_351 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(8),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_35
    );
  BScanCtrl0_Msub_n0044_inst_lut2_361 : X_LUT4
    generic map(
      INIT => X"5555"
    )
    port map (
      ADR0 => BScanCtrl0_RepCount(9),
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_Msub_n0044_inst_lut2_36
    );
  BScanCtrl0_n0088_8_XUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_8_XORF,
      O => BScanCtrl0_n0088(8)
    );
  BScanCtrl0_n0088_8_YUSED : X_BUF
    port map (
      I => BScanCtrl0_n0088_8_XORG,
      O => BScanCtrl0_n0088(9)
    );
  BScanCtrl0_Msub_n0044_inst_cy_90 : X_MUX2
    port map (
      IA => BScanCtrl0_RepCount(9),
      IB => BScanCtrl0_Msub_n0044_inst_cy_89,
      SEL => BScanCtrl0_Msub_n0044_inst_lut2_36,
      O => BScanCtrl0_n0088_8_CYMUXG
    );
  BScanCtrl0_Msub_n0044_inst_sum_76 : X_XOR2
    port map (
      I0 => BScanCtrl0_Msub_n0044_inst_cy_89,
      I1 => BScanCtrl0_Msub_n0044_inst_lut2_36,
      O => BScanCtrl0_n0088_8_XORG
    );
  BScanCtrl0_n0088_8_CYINIT_1263 : X_BUF
    port map (
      I => BScanCtrl0_n0088_6_CYMUXG,
      O => BScanCtrl0_n0088_8_CYINIT
    );
  BScanCtrl0_pTriggerOut_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTriggerOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTriggerOut_FFY_RST
    );
  BScanCtrl0_pTriggerOut_1264 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0035,
      CE => BScanCtrl0_ClkEn,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTriggerOut_FFY_RST,
      O => BScanCtrl0_pTriggerOut
    );
  BScanCtrl0_n00861 : X_LUT4
    generic map(
      INIT => X"0C00"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_ClkEn,
      ADR2 => BScanCtrl0_BScanTrigger,
      ADR3 => BScanCtrl0_IncScanCount,
      O => BScanCtrl0_pTriggerOut_FROM
    );
  BScanCtrl0_n00351 : X_LUT4
    generic map(
      INIT => X"F000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_IncScanCount,
      ADR3 => BScanCtrl0_BScanActive,
      O => BScanCtrl0_n0035
    );
  BScanCtrl0_pTriggerOut_XUSED : X_BUF
    port map (
      I => BScanCtrl0_pTriggerOut_FROM,
      O => BScanCtrl0_n0086
    );
  BScanCtrl0_pTriggerOut_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_pTriggerOut_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_pTxCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_1_FFY_RST
    );
  BScanCtrl0_pTxCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_40,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_1_FFY_RST,
      O => BScanCtrl0_pTxCount(0)
    );
  BScanCtrl0_pTxCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_1_FFX_RST
    );
  BScanCtrl0_pTxCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_41,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_1_FFX_RST,
      O => BScanCtrl0_pTxCount(1)
    );
  BScanCtrl0_pTxCount_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_pTxCount_1_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_pTxCount_3_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_3_FFX_RST
    );
  BScanCtrl0_pTxCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_43,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_3_FFX_RST,
      O => BScanCtrl0_pTxCount(3)
    );
  BScanCtrl0_pTxCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_3_FFY_RST
    );
  BScanCtrl0_pTxCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_42,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_3_FFY_RST,
      O => BScanCtrl0_pTxCount(2)
    );
  BScanCtrl0_pTxCount_3_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_pTxCount_3_FROM
    );
  BScanCtrl0_pTxCount_3_G : X_LUT4
    generic map(
      INIT => X"FFFF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_pTxCount_3_GROM
    );
  BScanCtrl0_pTxCount_3_XUSED : X_BUF
    port map (
      I => BScanCtrl0_pTxCount_3_FROM,
      O => BScanCtrl0_pTxCount_3_X
    );
  BScanCtrl0_pTxCount_3_YUSED : X_BUF
    port map (
      I => BScanCtrl0_pTxCount_3_GROM,
      O => BScanCtrl0_pTxCount_3_Y
    );
  BScanCtrl0_pTxCount_3_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_pTxCount_3_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_pTxCount_5_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_5_FFX_RST
    );
  BScanCtrl0_pTxCount_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_45,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_5_FFX_RST,
      O => BScanCtrl0_pTxCount(5)
    );
  BScanCtrl0_pTxCount_5_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_5_FFY_RST
    );
  BScanCtrl0_pTxCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_44,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_5_FFY_RST,
      O => BScanCtrl0_pTxCount(4)
    );
  BScanCtrl0_pTxCount_5_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_pTxCount_5_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_pTxCount_6_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_pTxCount_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_pTxCount_6_FFY_RST
    );
  BScanCtrl0_pTxCount_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_ScanCount_46,
      CE => BScanCtrl0_n0086,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_pTxCount_6_FFY_RST,
      O => BScanCtrl0_pTxCount(6)
    );
  BScanCtrl0_pTxCount_6_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_pTxCount_6_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_vBScanTrigger_1_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_vBScanTrigger_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_vBScanTrigger_1_FFX_RST
    );
  BScanCtrl0_vBScanTrigger_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_vBScanTrigger(0),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vBScanTrigger_1_FFX_RST,
      O => BScanCtrl0_vBScanTrigger(1)
    );
  BScanCtrl0_vBScanTrigger_1_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_vBScanTrigger_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_vBScanTrigger_1_FFY_RST
    );
  BScanCtrl0_vBScanTrigger_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => DoBScan,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vBScanTrigger_1_FFY_RST,
      O => BScanCtrl0_vBScanTrigger(0)
    );
  DoBScan1 : X_LUT4
    generic map(
      INIT => X"FCFC"
    )
    port map (
      ADR0 => VCC,
      ADR1 => PerLBusInterface0_StrobeExtender0_pStrobeOut,
      ADR2 => EncoderMonitor0_pBScanTrigger,
      ADR3 => VCC,
      O => DoBScan
    );
  BScanCtrl0_vBScanTrigger_1_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_vBScanTrigger_1_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_vBScanTrigger_2_FFY_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_vBScanTrigger_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_vBScanTrigger_2_FFY_RST
    );
  FocusUnitCtrl0_StartDelay_1265 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0048,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vBScanTrigger_2_FFY_RST,
      O => FocusUnitCtrl0_StartDelay
    );
  BScanCtrl0_vBScanTrigger_2_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_vBScanTrigger_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_vBScanTrigger_2_FFX_RST
    );
  BScanCtrl0_vBScanTrigger_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_vBScanTrigger(1),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vBScanTrigger_2_FFX_RST,
      O => BScanCtrl0_vBScanTrigger(2)
    );
  FocusUnitCtrl0_n004812 : X_LUT4
    generic map(
      INIT => X"AEEE"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28945,
      ADR1 => FocusUnitCtrl0_N28939,
      ADR2 => PerLBusInterface0_RegBank_5_11,
      ADR3 => PerLBusInterface0_RegBank_5_10,
      O => BScanCtrl0_vBScanTrigger_2_FROM
    );
  FocusUnitCtrl0_n004815 : X_LUT4
    generic map(
      INIT => X"FFE0"
    )
    port map (
      ADR0 => FocusUnitCtrl0_N28902,
      ADR1 => CHOICE600,
      ADR2 => FocusUnitCtrl0_DelayDone,
      ADR3 => CHOICE604,
      O => FocusUnitCtrl0_n0048
    );
  BScanCtrl0_vBScanTrigger_2_XUSED : X_BUF
    port map (
      I => BScanCtrl0_vBScanTrigger_2_FROM,
      O => CHOICE604
    );
  BScanCtrl0_vBScanTrigger_2_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_vBScanTrigger_2_SRMUX_OUTPUTNOT
    );
  BScanCtrl0_vCount_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => BScanCtrl0_vCount_1_FFY_RST
    );
  BScanCtrl0_vCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0019(0),
      CE => pnLReset_IBUF,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vCount_1_FFY_RST,
      O => BScanCtrl0_vCount(0)
    );
  BScanCtrl0_vCount_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => BScanCtrl0_vCount_1_FFX_RST
    );
  BScanCtrl0_vCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0019(1),
      CE => pnLReset_IBUF,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vCount_1_FFX_RST,
      O => BScanCtrl0_vCount(1)
    );
  BScanCtrl0_n0019_1_1 : X_LUT4
    generic map(
      INIT => X"0FF0"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => BScanCtrl0_vCount(0),
      ADR3 => BScanCtrl0_vCount(1),
      O => BScanCtrl0_n0019(1)
    );
  BScanCtrl0_n0019_0_1 : X_LUT4
    generic map(
      INIT => X"00CF"
    )
    port map (
      ADR0 => VCC,
      ADR1 => BScanCtrl0_vCount(1),
      ADR2 => BScanCtrl0_vCount(2),
      ADR3 => BScanCtrl0_vCount(0),
      O => BScanCtrl0_n0019(0)
    );
  BScanCtrl0_vCount_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => BScanCtrl0_vCount_2_FFY_RST
    );
  BScanCtrl0_vCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0019(2),
      CE => pnLReset_IBUF,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vCount_2_FFY_RST,
      O => BScanCtrl0_vCount(2)
    );
  BScanCtrl0_n0019_2_1 : X_LUT4
    generic map(
      INIT => X"5AA0"
    )
    port map (
      ADR0 => BScanCtrl0_vCount(0),
      ADR1 => VCC,
      ADR2 => BScanCtrl0_vCount(2),
      ADR3 => BScanCtrl0_vCount(1),
      O => BScanCtrl0_n0019(2)
    );
  BScanCtrl0_vRxCountDone_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => BScanCtrl0_vRxCountDone_FFX_RST
    );
  BScanCtrl0_vRxCountDone_1266 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0041_rt,
      CE => pnLReset_IBUF,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vRxCountDone_FFX_RST,
      O => BScanCtrl0_vRxCountDone
    );
  BScanCtrl0_n0041_rt_1267 : X_XOR2
    port map (
      I0 => BScanCtrl0_vRxCountDone_CYINIT,
      I1 => BScanCtrl0_vRxCountDone_FROM,
      O => BScanCtrl0_n0041_rt
    );
  BScanCtrl0_vRxCountDone_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => BScanCtrl0_vRxCountDone_FROM
    );
  BScanCtrl0_vRxCountDone_CYINIT_1268 : X_BUF
    port map (
      I => PerLBusInterface0_RegBank_5_8_CYMUXG,
      O => BScanCtrl0_vRxCountDone_CYINIT
    );
  BScanCtrl0_vScanCountDone_FFX_RSTOR : X_OR2
    port map (
      I0 => BScanCtrl0_vScanCountDone_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => BScanCtrl0_vScanCountDone_FFX_RST
    );
  BScanCtrl0_vScanCountDone_1269 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_n0040,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => BScanCtrl0_vScanCountDone_FFX_RST,
      O => BScanCtrl0_vScanCountDone
    );
  BScanCtrl0_n00821 : X_LUT4
    generic map(
      INIT => X"C0E0"
    )
    port map (
      ADR0 => BScanCtrl0_IncScanCount,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_ClkEn,
      ADR3 => BScanCtrl0_vScanCountDone,
      O => BScanCtrl0_vScanCountDone_FROM
    );
  BScanCtrl0_n00841 : X_LUT4
    generic map(
      INIT => X"EC00"
    )
    port map (
      ADR0 => BScanCtrl0_IncScanCount,
      ADR1 => BScanCtrl0_BScanTrigger,
      ADR2 => BScanCtrl0_vScanCountDone,
      ADR3 => BScanCtrl0_ClkEn,
      O => BScanCtrl0_vScanCountDone_GROM
    );
  BScanCtrl0_vScanCountDone_XUSED : X_BUF
    port map (
      I => BScanCtrl0_vScanCountDone_FROM,
      O => BScanCtrl0_n0082
    );
  BScanCtrl0_vScanCountDone_YUSED : X_BUF
    port map (
      I => BScanCtrl0_vScanCountDone_GROM,
      O => BScanCtrl0_n0084
    );
  BScanCtrl0_vScanCountDone_SRMUX : X_INV
    port map (
      I => pnLReset_IBUF,
      O => BScanCtrl0_vScanCountDone_SRMUX_OUTPUTNOT
    );
  EncoderMonitor0_n029625 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(6),
      ADR1 => EncoderMonitor0_TrigCount(5),
      ADR2 => EncoderMonitor0_TrigCount(7),
      ADR3 => EncoderMonitor0_TrigCount(4),
      O => CHOICE269_GROM
    );
  CHOICE269_YUSED : X_BUF
    port map (
      I => CHOICE269_GROM,
      O => CHOICE269
    );
  EncoderMonitor0_n029649 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(8),
      ADR1 => EncoderMonitor0_TrigCount(10),
      ADR2 => EncoderMonitor0_TrigCount(11),
      ADR3 => EncoderMonitor0_TrigCount(9),
      O => CHOICE277_GROM
    );
  CHOICE277_YUSED : X_BUF
    port map (
      I => CHOICE277_GROM,
      O => CHOICE277
    );
  EncoderMonitor0_n029662 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => EncoderMonitor0_TrigCount(12),
      ADR1 => EncoderMonitor0_TrigCount(13),
      ADR2 => EncoderMonitor0_TrigCount(15),
      ADR3 => EncoderMonitor0_TrigCount(14),
      O => CHOICE284_GROM
    );
  CHOICE284_YUSED : X_BUF
    port map (
      I => CHOICE284_GROM,
      O => CHOICE284
    );
  CHOICE367_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE367_FROM
    );
  EncoderMonitor0_n039412 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftCount(3),
      ADR1 => EncoderMonitor0_ShiftCount(0),
      ADR2 => EncoderMonitor0_ShiftCount(2),
      ADR3 => EncoderMonitor0_ShiftCount(1),
      O => CHOICE367_GROM
    );
  CHOICE367_XUSED : X_BUF
    port map (
      I => CHOICE367_FROM,
      O => CHOICE367_X
    );
  CHOICE367_YUSED : X_BUF
    port map (
      I => CHOICE367_GROM,
      O => CHOICE367
    );
  EncoderMonitor0_n039425 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => EncoderMonitor0_ShiftCount(7),
      ADR1 => EncoderMonitor0_ShiftCount(6),
      ADR2 => EncoderMonitor0_ShiftCount(5),
      ADR3 => EncoderMonitor0_ShiftCount(4),
      O => CHOICE374_FROM
    );
  EncoderMonitor0_n06471 : X_LUT4
    generic map(
      INIT => X"DDFF"
    )
    port map (
      ADR0 => CHOICE367,
      ADR1 => EncoderMonitor0_BeginShift,
      ADR2 => VCC,
      ADR3 => CHOICE374,
      O => CHOICE374_GROM
    );
  CHOICE374_XUSED : X_BUF
    port map (
      I => CHOICE374_FROM,
      O => CHOICE374
    );
  CHOICE374_YUSED : X_BUF
    port map (
      I => CHOICE374_GROM,
      O => EncoderMonitor0_n0647
    );
  TriggerDelay0_n004925 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_62,
      ADR1 => TriggerDelay0_DelayCount_2_61,
      ADR2 => TriggerDelay0_DelayCount_2_64,
      ADR3 => TriggerDelay0_DelayCount_2_63,
      O => CHOICE488_GROM
    );
  CHOICE488_YUSED : X_BUF
    port map (
      I => CHOICE488_GROM,
      O => CHOICE488
    );
  CHOICE496_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE496_FROM
    );
  TriggerDelay0_n004949 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_65,
      ADR1 => TriggerDelay0_DelayCount_2_66,
      ADR2 => TriggerDelay0_DelayCount_2_68,
      ADR3 => TriggerDelay0_DelayCount_2_67,
      O => CHOICE496_GROM
    );
  CHOICE496_XUSED : X_BUF
    port map (
      I => CHOICE496_FROM,
      O => CHOICE496_X
    );
  CHOICE496_YUSED : X_BUF
    port map (
      I => CHOICE496_GROM,
      O => CHOICE496
    );
  TriggerDelay0_n004962 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_2_72,
      ADR1 => TriggerDelay0_DelayCount_2_71,
      ADR2 => TriggerDelay0_DelayCount_2_70,
      ADR3 => TriggerDelay0_DelayCount_2_69,
      O => CHOICE503_GROM
    );
  CHOICE503_YUSED : X_BUF
    port map (
      I => CHOICE503_GROM,
      O => CHOICE503
    );
  CHOICE519_F : X_LUT4
    generic map(
      INIT => X"0000"
    )
    port map (
      ADR0 => VCC,
      ADR1 => VCC,
      ADR2 => VCC,
      ADR3 => VCC,
      O => CHOICE519_FROM
    );
  TriggerDelay0_n004825 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_3_64,
      ADR1 => TriggerDelay0_DelayCount_3_63,
      ADR2 => TriggerDelay0_DelayCount_3_62,
      ADR3 => TriggerDelay0_DelayCount_3_61,
      O => CHOICE519_GROM
    );
  CHOICE519_XUSED : X_BUF
    port map (
      I => CHOICE519_FROM,
      O => CHOICE519_X
    );
  CHOICE519_YUSED : X_BUF
    port map (
      I => CHOICE519_GROM,
      O => CHOICE519
    );
  TriggerDelay0_n004849 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_3_68,
      ADR1 => TriggerDelay0_DelayCount_3_65,
      ADR2 => TriggerDelay0_DelayCount_3_66,
      ADR3 => TriggerDelay0_DelayCount_3_67,
      O => CHOICE527_GROM
    );
  CHOICE527_YUSED : X_BUF
    port map (
      I => CHOICE527_GROM,
      O => CHOICE527
    );
  TriggerDelay0_n004862 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_3_69,
      ADR1 => TriggerDelay0_DelayCount_3_71,
      ADR2 => TriggerDelay0_DelayCount_3_70,
      ADR3 => TriggerDelay0_DelayCount_3_72,
      O => CHOICE534_GROM
    );
  CHOICE534_YUSED : X_BUF
    port map (
      I => CHOICE534_GROM,
      O => CHOICE534
    );
  TriggerDelay0_n005025 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_62,
      ADR1 => TriggerDelay0_DelayCount_1_63,
      ADR2 => TriggerDelay0_DelayCount_1_61,
      ADR3 => TriggerDelay0_DelayCount_1_64,
      O => CHOICE550_GROM
    );
  CHOICE550_YUSED : X_BUF
    port map (
      I => CHOICE550_GROM,
      O => CHOICE550
    );
  TriggerDelay0_n005049 : X_LUT4
    generic map(
      INIT => X"0001"
    )
    port map (
      ADR0 => TriggerDelay0_DelayCount_1_67,
      ADR1 => TriggerDelay0_DelayCount_1_65,
      ADR2 => TriggerDelay0_DelayCount_1_66,
      ADR3 => TriggerDelay0_DelayCount_1_68,
      O => CHOICE558_GROM
    );
  CHOICE558_YUSED : X_BUF
    port map (
      I => CHOICE558_GROM,
      O => CHOICE558
    );
  EncoderMonitor0_SerialResults_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0091,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_23_FFX_RST,
      O => EncoderMonitor0_SerialResults(23)
    );
  EncoderMonitor0_SerialResults_23_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_23_FFX_RST
    );
  EncoderMonitor0_SerialResults_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0090,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_25_FFY_RST,
      O => EncoderMonitor0_SerialResults(24)
    );
  EncoderMonitor0_SerialResults_25_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_25_FFY_RST
    );
  EncoderMonitor0_SerialResults_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0093,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_21_FFX_RST,
      O => EncoderMonitor0_SerialResults(21)
    );
  EncoderMonitor0_SerialResults_21_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_21_FFX_RST
    );
  EncoderMonitor0_SerialResults_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0092,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_23_FFY_RST,
      O => EncoderMonitor0_SerialResults(22)
    );
  EncoderMonitor0_SerialResults_23_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_23_FFY_RST
    );
  EncoderMonitor0_SerialResults_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0088,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_27_FFY_RST,
      O => EncoderMonitor0_SerialResults(26)
    );
  EncoderMonitor0_SerialResults_27_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_27_FFY_RST
    );
  EncoderMonitor0_SerialResults_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0089,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_25_FFX_RST,
      O => EncoderMonitor0_SerialResults(25)
    );
  EncoderMonitor0_SerialResults_25_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_25_FFX_RST
    );
  EncoderMonitor0_SerialResults_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0113,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_1_FFX_RST,
      O => EncoderMonitor0_SerialResults(1)
    );
  EncoderMonitor0_SerialResults_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_1_FFX_RST
    );
  EncoderMonitor0_SerialResults_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0095,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_19_FFY_RST,
      O => EncoderMonitor0_SerialResults(19)
    );
  EncoderMonitor0_SerialResults_19_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_19_FFY_RST
    );
  EncoderMonitor0_SerialResults_191 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0243,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_191_FFX_RST,
      O => EncoderMonitor0_SerialResults(191)
    );
  EncoderMonitor0_SerialResults_191_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_191_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_191_FFX_RST
    );
  EncoderMonitor0_SerialResults_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0114,
      CE => EncoderMonitor0_n0454,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_1_FFY_RST,
      O => EncoderMonitor0_SerialResults(0)
    );
  EncoderMonitor0_SerialResults_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_1_FFY_RST
    );
  EncoderMonitor0_SerialResults_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0096,
      CE => EncoderMonitor0_n04541_6,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_18_FFX_RST,
      O => EncoderMonitor0_SerialResults(18)
    );
  EncoderMonitor0_SerialResults_18_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_18_FFX_RST
    );
  EncoderMonitor0_SerialResults_189 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0245,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_189_FFX_RST,
      O => EncoderMonitor0_SerialResults(189)
    );
  EncoderMonitor0_SerialResults_189_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_189_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_189_FFX_RST
    );
  EncoderMonitor0_SerialResults_190 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0244,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_191_FFY_RST,
      O => EncoderMonitor0_SerialResults(190)
    );
  EncoderMonitor0_SerialResults_191_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_191_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_191_FFY_RST
    );
  EncoderMonitor0_SerialResults_87 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0155,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_87_FFX_RST,
      O => EncoderMonitor0_SerialResults(87)
    );
  EncoderMonitor0_SerialResults_87_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_87_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_87_FFX_RST
    );
  EncoderMonitor0_SerialResults_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0107,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_8_FFY_RST,
      O => EncoderMonitor0_SerialResults(7)
    );
  EncoderMonitor0_SerialResults_8_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_8_FFY_RST
    );
  EncoderMonitor0_SerialResults_89 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0153,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_89_FFX_RST,
      O => EncoderMonitor0_SerialResults(89)
    );
  EncoderMonitor0_SerialResults_89_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_89_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_89_FFX_RST
    );
  EncoderMonitor0_SerialResults_90 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0152,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_91_FFY_RST,
      O => EncoderMonitor0_SerialResults(90)
    );
  EncoderMonitor0_SerialResults_91_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_91_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_91_FFY_RST
    );
  EncoderMonitor0_SerialResults_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0106,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_8_FFX_RST,
      O => EncoderMonitor0_SerialResults(8)
    );
  EncoderMonitor0_SerialResults_8_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_8_FFX_RST
    );
  EncoderMonitor0_SerialResults_92 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0150,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_93_FFY_RST,
      O => EncoderMonitor0_SerialResults(92)
    );
  EncoderMonitor0_SerialResults_93_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_93_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_93_FFY_RST
    );
  EncoderMonitor0_SerialResults_91 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0151,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_91_FFX_RST,
      O => EncoderMonitor0_SerialResults(91)
    );
  EncoderMonitor0_SerialResults_91_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_91_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_91_FFX_RST
    );
  EncoderMonitor0_SerialResults_94 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0148,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_95_FFY_RST,
      O => EncoderMonitor0_SerialResults(94)
    );
  EncoderMonitor0_SerialResults_95_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_95_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_95_FFY_RST
    );
  EncoderMonitor0_SerialResults_93 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0149,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_93_FFX_RST,
      O => EncoderMonitor0_SerialResults(93)
    );
  EncoderMonitor0_SerialResults_93_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_93_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_93_FFX_RST
    );
  EncoderMonitor0_SerialResults_96 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0210,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_97_FFY_RST,
      O => EncoderMonitor0_SerialResults(96)
    );
  EncoderMonitor0_SerialResults_97_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_97_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_97_FFY_RST
    );
  EncoderMonitor0_SerialResults_34 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0144,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_35_FFY_RST,
      O => EncoderMonitor0_SerialResults(34)
    );
  EncoderMonitor0_SerialResults_35_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_35_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_35_FFY_RST
    );
  EncoderMonitor0_SerialResults_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0083,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_31_FFX_RST,
      O => EncoderMonitor0_SerialResults(31)
    );
  EncoderMonitor0_SerialResults_31_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_31_FFX_RST
    );
  EncoderMonitor0_SerialResults_33 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0145,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_33_FFX_RST,
      O => EncoderMonitor0_SerialResults(33)
    );
  EncoderMonitor0_SerialResults_33_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_33_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_33_FFX_RST
    );
  EncoderMonitor0_SerialResults_36 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0142,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_37_FFY_RST,
      O => EncoderMonitor0_SerialResults(36)
    );
  EncoderMonitor0_SerialResults_37_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_37_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_37_FFY_RST
    );
  EncoderMonitor0_SerialResults_35 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0143,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_35_FFX_RST,
      O => EncoderMonitor0_SerialResults(35)
    );
  EncoderMonitor0_SerialResults_35_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_35_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_35_FFX_RST
    );
  EncoderMonitor0_SerialResults_38 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0140,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_39_FFY_RST,
      O => EncoderMonitor0_SerialResults(38)
    );
  EncoderMonitor0_SerialResults_39_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_39_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_39_FFY_RST
    );
  EncoderMonitor0_SerialResults_37 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0141,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_37_FFX_RST,
      O => EncoderMonitor0_SerialResults(37)
    );
  EncoderMonitor0_SerialResults_37_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_37_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_37_FFX_RST
    );
  EncoderMonitor0_SerialResults_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0112,
      CE => EncoderMonitor0_n04541_5,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_3_FFY_RST,
      O => EncoderMonitor0_SerialResults(2)
    );
  EncoderMonitor0_SerialResults_3_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_3_FFY_RST
    );
  EncoderMonitor0_SerialResults_39 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0139,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_39_FFX_RST,
      O => EncoderMonitor0_SerialResults(39)
    );
  EncoderMonitor0_SerialResults_39_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_39_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_39_FFX_RST
    );
  EncoderMonitor0_SerialResults_40 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0138,
      CE => EncoderMonitor0_n04541_4,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_41_FFY_RST,
      O => EncoderMonitor0_SerialResults(40)
    );
  EncoderMonitor0_SerialResults_41_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_41_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_41_FFY_RST
    );
  EncoderMonitor0_SerialResults_49 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0129,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_49_FFX_RST,
      O => EncoderMonitor0_SerialResults(49)
    );
  EncoderMonitor0_SerialResults_49_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_49_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_49_FFX_RST
    );
  EncoderMonitor0_SerialResults_50 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0128,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_51_FFY_RST,
      O => EncoderMonitor0_SerialResults(50)
    );
  EncoderMonitor0_SerialResults_51_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_51_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_51_FFY_RST
    );
  EncoderMonitor0_SerialResults_52 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0126,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_53_FFY_RST,
      O => EncoderMonitor0_SerialResults(52)
    );
  EncoderMonitor0_SerialResults_53_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_53_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_53_FFY_RST
    );
  EncoderMonitor0_SerialResults_51 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0127,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_51_FFX_RST,
      O => EncoderMonitor0_SerialResults(51)
    );
  EncoderMonitor0_SerialResults_51_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_51_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_51_FFX_RST
    );
  EncoderMonitor0_SerialResults_54 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0124,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_55_FFY_RST,
      O => EncoderMonitor0_SerialResults(54)
    );
  EncoderMonitor0_SerialResults_55_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_55_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_55_FFY_RST
    );
  EncoderMonitor0_SerialResults_53 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0125,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_53_FFX_RST,
      O => EncoderMonitor0_SerialResults(53)
    );
  EncoderMonitor0_SerialResults_53_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_53_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_53_FFX_RST
    );
  EncoderMonitor0_SerialResults_56 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0122,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_57_FFY_RST,
      O => EncoderMonitor0_SerialResults(56)
    );
  EncoderMonitor0_SerialResults_57_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_57_FFY_RST
    );
  EncoderMonitor0_SerialResults_55 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0123,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_55_FFX_RST,
      O => EncoderMonitor0_SerialResults(55)
    );
  EncoderMonitor0_SerialResults_55_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_55_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_55_FFX_RST
    );
  EncoderMonitor0_SerialResults_58 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0120,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_59_FFY_RST,
      O => EncoderMonitor0_SerialResults(58)
    );
  EncoderMonitor0_SerialResults_59_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_59_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_59_FFY_RST
    );
  EncoderMonitor0_SerialResults_57 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0121,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_57_FFX_RST,
      O => EncoderMonitor0_SerialResults(57)
    );
  EncoderMonitor0_SerialResults_57_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_57_FFX_RST
    );
  EncoderMonitor0_TrigCount_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_10_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_10_FFY_RST,
      O => EncoderMonitor0_TrigCount(10)
    );
  EncoderMonitor0_TrigCount_10_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_10_FFY_RST
    );
  EncoderMonitor0_TrigCount_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_11_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_11_FFY_RST,
      O => EncoderMonitor0_TrigCount(11)
    );
  EncoderMonitor0_TrigCount_11_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_11_FFY_RST
    );
  EncoderMonitor0_TrigCount_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_12_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_12_FFY_RST,
      O => EncoderMonitor0_TrigCount(12)
    );
  EncoderMonitor0_TrigCount_12_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_12_FFY_RST
    );
  EncoderMonitor0_TrigCount_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_13_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_13_FFY_RST,
      O => EncoderMonitor0_TrigCount(13)
    );
  EncoderMonitor0_TrigCount_13_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_13_FFY_RST
    );
  EncoderMonitor0_TrigCount_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_14_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_14_FFY_RST,
      O => EncoderMonitor0_TrigCount(14)
    );
  EncoderMonitor0_TrigCount_14_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_14_FFY_RST
    );
  EncoderMonitor0_TrigCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_1_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_1_FFY_RST,
      O => EncoderMonitor0_TrigCount(1)
    );
  EncoderMonitor0_TrigCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_1_FFY_RST
    );
  EncoderMonitor0_TrigCount_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_15_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_15_FFY_RST,
      O => EncoderMonitor0_TrigCount(15)
    );
  EncoderMonitor0_TrigCount_15_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_15_FFY_RST
    );
  EncoderMonitor0_SerialResults_59 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0119,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_59_FFX_RST,
      O => EncoderMonitor0_SerialResults(59)
    );
  EncoderMonitor0_SerialResults_59_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_59_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_59_FFX_RST
    );
  EncoderMonitor0_SerialResults_62 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0116,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_63_FFY_RST,
      O => EncoderMonitor0_SerialResults(62)
    );
  EncoderMonitor0_SerialResults_63_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_63_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_63_FFY_RST
    );
  EncoderMonitor0_SerialResults_61 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0117,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_61_FFX_RST,
      O => EncoderMonitor0_SerialResults(61)
    );
  EncoderMonitor0_SerialResults_61_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_61_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_61_FFX_RST
    );
  EncoderMonitor0_SerialResults_64 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0178,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_64_FFY_RST,
      O => EncoderMonitor0_SerialResults(64)
    );
  EncoderMonitor0_SerialResults_64_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_64_FFY_RST
    );
  EncoderMonitor0_SerialResults_63 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0115,
      CE => EncoderMonitor0_n04541_3,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_63_FFX_RST,
      O => EncoderMonitor0_SerialResults(63)
    );
  EncoderMonitor0_SerialResults_63_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_63_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_63_FFX_RST
    );
  EncoderMonitor0_SerialResults_65 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0177,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_65_FFY_RST,
      O => EncoderMonitor0_SerialResults(65)
    );
  EncoderMonitor0_SerialResults_65_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_65_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_65_FFY_RST
    );
  EncoderMonitor0_SerialResults_68 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0174,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_69_FFY_RST,
      O => EncoderMonitor0_SerialResults(68)
    );
  EncoderMonitor0_SerialResults_69_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_69_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_69_FFY_RST
    );
  EncoderMonitor0_SerialResults_77 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0165,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_77_FFX_RST,
      O => EncoderMonitor0_SerialResults(77)
    );
  EncoderMonitor0_SerialResults_77_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_77_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_77_FFX_RST
    );
  EncoderMonitor0_SerialResults_80 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0162,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_81_FFY_RST,
      O => EncoderMonitor0_SerialResults(80)
    );
  EncoderMonitor0_SerialResults_81_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_81_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_81_FFY_RST
    );
  EncoderMonitor0_SerialResults_79 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0163,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_79_FFX_RST,
      O => EncoderMonitor0_SerialResults(79)
    );
  EncoderMonitor0_SerialResults_79_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_79_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_79_FFX_RST
    );
  EncoderMonitor0_SerialResults_82 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0160,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_83_FFY_RST,
      O => EncoderMonitor0_SerialResults(82)
    );
  EncoderMonitor0_SerialResults_83_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_83_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_83_FFY_RST
    );
  EncoderMonitor0_SerialResults_81 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0161,
      CE => EncoderMonitor0_n04541_2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_81_FFX_RST,
      O => EncoderMonitor0_SerialResults(81)
    );
  EncoderMonitor0_SerialResults_81_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_81_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_81_FFX_RST
    );
  EncoderMonitor0_SerialResults_86 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0156,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_87_FFY_RST,
      O => EncoderMonitor0_SerialResults(86)
    );
  EncoderMonitor0_SerialResults_87_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_87_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_87_FFY_RST
    );
  EncoderMonitor0_SerialResults_83 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0159,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_83_FFX_RST,
      O => EncoderMonitor0_SerialResults(83)
    );
  EncoderMonitor0_SerialResults_83_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_83_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_83_FFX_RST
    );
  EncoderMonitor0_SerialResults_85 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0157,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_85_FFX_RST,
      O => EncoderMonitor0_SerialResults(85)
    );
  EncoderMonitor0_SerialResults_85_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_85_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_85_FFX_RST
    );
  EncoderMonitor0_SerialResults_98 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0208,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_99_FFY_RST,
      O => EncoderMonitor0_SerialResults(98)
    );
  EncoderMonitor0_SerialResults_99_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_99_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_99_FFY_RST
    );
  EncoderMonitor0_SerialResults_95 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0147,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_95_FFX_RST,
      O => EncoderMonitor0_SerialResults(95)
    );
  EncoderMonitor0_SerialResults_95_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_95_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_95_FFX_RST
    );
  EncoderMonitor0_SerialResults_97 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0209,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_97_FFX_RST,
      O => EncoderMonitor0_SerialResults(97)
    );
  EncoderMonitor0_SerialResults_97_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_97_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_97_FFX_RST
    );
  EncoderMonitor0_SerialResults_99 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0207,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_99_FFX_RST,
      O => EncoderMonitor0_SerialResults(99)
    );
  EncoderMonitor0_SerialResults_99_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_99_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_99_FFX_RST
    );
  EncoderMonitor0_SerialResults_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0105,
      CE => EncoderMonitor0_n04541_1,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_SerialResults_9_FFY_RST,
      O => EncoderMonitor0_SerialResults(9)
    );
  EncoderMonitor0_SerialResults_9_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_SerialResults_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_SerialResults_9_FFY_RST
    );
  EncoderMonitor0_ShiftCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_20,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_0_FFY_RST,
      O => EncoderMonitor0_ShiftCount(0)
    );
  EncoderMonitor0_ShiftCount_0_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_0_FFY_RST
    );
  EncoderMonitor0_ShiftCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_22,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_1_FFY_RST,
      O => EncoderMonitor0_ShiftCount(2)
    );
  EncoderMonitor0_ShiftCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_1_FFY_RST
    );
  EncoderMonitor0_ShiftCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_24,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_3_FFY_RST,
      O => EncoderMonitor0_ShiftCount(4)
    );
  EncoderMonitor0_ShiftCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_3_FFY_RST
    );
  EncoderMonitor0_ShiftCount_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_27,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_7_FFX_RST,
      O => EncoderMonitor0_ShiftCount(7)
    );
  EncoderMonitor0_ShiftCount_7_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_7_FFX_RST
    );
  EncoderMonitor0_ShiftResults_1_1270 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_2_FFY_RST,
      O => EncoderMonitor0_ShiftResults_1
    );
  EncoderMonitor0_ShiftResults_2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_2_FFY_RST
    );
  EncoderMonitor0_ShiftResults_2_1271 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_2_FFX_RST,
      O => EncoderMonitor0_ShiftResults_2
    );
  EncoderMonitor0_ShiftResults_2_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_2_FFX_RST
    );
  EncoderMonitor0_ShiftResults_3_1272 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_4_FFY_RST,
      O => EncoderMonitor0_ShiftResults_3
    );
  EncoderMonitor0_ShiftResults_4_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_4_FFY_RST
    );
  EncoderMonitor0_ShiftResults_4_1273 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_4_FFX_RST,
      O => EncoderMonitor0_ShiftResults_4
    );
  EncoderMonitor0_ShiftResults_4_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_4_FFX_RST
    );
  EncoderMonitor0_ShiftResults_5_1274 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_6_FFY_RST,
      O => EncoderMonitor0_ShiftResults_5
    );
  EncoderMonitor0_ShiftResults_6_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_6_FFY_RST
    );
  EncoderMonitor0_TrigCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077(0),
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_0_FFX_RST,
      O => EncoderMonitor0_TrigCount(0)
    );
  EncoderMonitor0_TrigCount_0_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_0_FFX_RST
    );
  EncoderMonitor0_ShiftResults_6_1275 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_6_FFX_RST,
      O => EncoderMonitor0_ShiftResults_6
    );
  EncoderMonitor0_ShiftResults_6_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_6_FFX_RST
    );
  EncoderMonitor0_TrigCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_2_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_2_FFY_RST,
      O => EncoderMonitor0_TrigCount(2)
    );
  EncoderMonitor0_TrigCount_2_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_2_FFY_RST
    );
  EncoderMonitor0_TrigCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_3_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_3_FFY_RST,
      O => EncoderMonitor0_TrigCount(3)
    );
  EncoderMonitor0_TrigCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_3_FFY_RST
    );
  EncoderMonitor0_TrigCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_4_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_4_FFY_RST,
      O => EncoderMonitor0_TrigCount(4)
    );
  EncoderMonitor0_TrigCount_4_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_4_FFY_RST
    );
  EncoderMonitor0_TrigCount_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_5_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_5_FFY_RST,
      O => EncoderMonitor0_TrigCount(5)
    );
  EncoderMonitor0_TrigCount_5_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_5_FFY_RST
    );
  EncoderMonitor0_TrigCount_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_6_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_6_FFY_RST,
      O => EncoderMonitor0_TrigCount(6)
    );
  EncoderMonitor0_TrigCount_6_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_6_FFY_RST
    );
  EncoderMonitor0_TrigCount_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_7_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_7_FFY_RST,
      O => EncoderMonitor0_TrigCount(7)
    );
  EncoderMonitor0_TrigCount_7_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_7_FFY_RST
    );
  FocusUnitCtrl0_DelayValAddr_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0050(2),
      CE => FocusUnitCtrl0_n0065,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValAddr_3_FFY_RST,
      O => FocusUnitCtrl0_DelayValAddr(2)
    );
  FocusUnitCtrl0_DelayValAddr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValAddr_3_FFY_RST
    );
  FocusUnitCtrl0_DelayValAddr_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0050(3),
      CE => FocusUnitCtrl0_n0065,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValAddr_3_FFX_RST,
      O => FocusUnitCtrl0_DelayValAddr(3)
    );
  FocusUnitCtrl0_DelayValAddr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValAddr_3_FFX_RST
    );
  FocusUnitCtrl0_DelayValInc_1276 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0045,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValInc_FFY_RST,
      O => FocusUnitCtrl0_DelayValInc
    );
  FocusUnitCtrl0_DelayValInc_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValInc_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValInc_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd13_1277 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd13_In,
      CE => VCC,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_DelayValRst_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_CtrlState_FFd13
    );
  FocusUnitCtrl0_DelayValRst_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_DelayValRst_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_DelayValRst_FFY_SET
    );
  FocusUnitCtrl0_DelayValRst_1278 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd13,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_DelayValRst_FFX_RST,
      O => FocusUnitCtrl0_DelayValRst
    );
  FocusUnitCtrl0_DelayValRst_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_DelayValRst_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_DelayValRst_FFX_RST
    );
  FocusUnitCtrl0_CtrlState_FFd1_1279 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd1_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_ProbeTx_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd1
    );
  FocusUnitCtrl0_ProbeTx_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_ProbeTx_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_ProbeTx_FFY_RST
    );
  FocusUnitCtrl0_Rx_nTx_1280 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0047,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_Rx_nTx_FFY_RST,
      O => FocusUnitCtrl0_Rx_nTx
    );
  FocusUnitCtrl0_Rx_nTx_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_Rx_nTx_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_Rx_nTx_FFY_RST
    );
  EncoderMonitor0_ShiftCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_21,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_1_FFX_RST,
      O => EncoderMonitor0_ShiftCount(1)
    );
  EncoderMonitor0_ShiftCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_1_FFX_RST
    );
  EncoderMonitor0_ShiftCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_23,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_3_FFX_RST,
      O => EncoderMonitor0_ShiftCount(3)
    );
  EncoderMonitor0_ShiftCount_3_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_3_FFX_RST
    );
  EncoderMonitor0_ShiftCount_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_26,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_5_FFY_RST,
      O => EncoderMonitor0_ShiftCount(6)
    );
  EncoderMonitor0_ShiftCount_5_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_5_FFY_RST
    );
  EncoderMonitor0_ShiftResults_1281 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_BeginShift,
      CE => EncoderMonitor0_n0649,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftResults_FFY_RST,
      O => EncoderMonitor0_ShiftResults
    );
  EncoderMonitor0_ShiftResults_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftResults_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftResults_FFY_RST
    );
  EncoderMonitor0_ShiftCount_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftCount_inst_sum_25,
      CE => EncoderMonitor0_n0647,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_ShiftCount_5_FFX_RST,
      O => EncoderMonitor0_ShiftCount(5)
    );
  EncoderMonitor0_ShiftCount_5_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_ShiftCount_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_ShiftCount_5_FFX_RST
    );
  EncoderMonitor0_TrigCount_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_8_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_8_FFY_RST,
      O => EncoderMonitor0_TrigCount(8)
    );
  EncoderMonitor0_TrigCount_8_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_8_FFY_RST
    );
  EncoderMonitor0_TrigCount_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0077_9_O,
      CE => EncoderMonitor0_n0453,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_TrigCount_9_FFY_RST,
      O => EncoderMonitor0_TrigCount(9)
    );
  EncoderMonitor0_TrigCount_9_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_TrigCount_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_TrigCount_9_FFY_RST
    );
  FocusUnitCtrl0_StrobeExtender1_pStrobeOut_1282 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_StartDelay,
      CE => FocusUnitCtrl0_StrobeExtender1_n0025,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FFY_RST,
      O => FocusUnitCtrl0_StrobeExtender1_pStrobeOut
    );
  FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_StrobeExtender1_pStrobeOut_FFY_RST
    );
  FocusUnitCtrl0_pProbeCtrl_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0044_0_Q,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeCtrl_0_FFY_RST,
      O => FocusUnitCtrl0_pProbeCtrl_0_Q
    );
  FocusUnitCtrl0_pProbeCtrl_0_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeCtrl_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeCtrl_0_FFY_RST
    );
  FocusUnitCtrl0_pProbeCtrl_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0044_2_Q,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeCtrl_2_FFY_RST,
      O => FocusUnitCtrl0_pProbeCtrl_2_Q
    );
  FocusUnitCtrl0_pProbeCtrl_2_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeCtrl_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeCtrl_2_FFY_RST
    );
  PerLBusInterface0_BlkRamWrite_1283 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_BlkRamWrite_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_BlkRamWrite_FFY_RST,
      O => PerLBusInterface0_BlkRamWrite
    );
  PerLBusInterface0_BlkRamWrite_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_BlkRamWrite_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_BlkRamWrite_FFY_RST
    );
  PerLBusInterface0_CalClkEn1_1284 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0310,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalClkEn2_FFY_RST,
      O => PerLBusInterface0_CalClkEn1
    );
  PerLBusInterface0_CalClkEn2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalClkEn2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalClkEn2_FFY_RST
    );
  PerLBusInterface0_CalDacActive_1285 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_CalDacStart,
      CE => PerLBusInterface0_n0535,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacActive_FFY_RST,
      O => PerLBusInterface0_CalDacActive
    );
  PerLBusInterface0_CalDacActive_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacActive_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacActive_FFY_RST
    );
  PerLBusInterface0_CalClkEn2_1286 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_N35406,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalClkEn2_FFX_RST,
      O => PerLBusInterface0_CalClkEn2
    );
  PerLBusInterface0_CalClkEn2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalClkEn2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalClkEn2_FFX_RST
    );
  EncoderMonitor0_pBScanTrigger_1287 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0080,
      CE => EncoderMonitor0_ClkEn2,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_pBScanTrigger_FFY_RST,
      O => EncoderMonitor0_pBScanTrigger
    );
  EncoderMonitor0_pBScanTrigger_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_pBScanTrigger_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_pBScanTrigger_FFY_RST
    );
  EncoderMonitor0_pSerialOut_1288 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_SerialResults(191),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_pSerialOut_FFY_RST,
      O => EncoderMonitor0_pSerialOut
    );
  EncoderMonitor0_pSerialOut_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_pSerialOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_pSerialOut_FFY_RST
    );
  FocusUnitCtrl0_ProbeTx_1289 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd10,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_ProbeTx_FFX_RST,
      O => FocusUnitCtrl0_ProbeTx
    );
  FocusUnitCtrl0_ProbeTx_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_ProbeTx_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_ProbeTx_FFX_RST
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_FeedbackBit,
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(0)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(0),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(1)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_1_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(2),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(3)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_3_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(3),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(4)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(4),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(5)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_5_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender0_CountLFSR(5),
      CE => FocusUnitCtrl0_StrobeExtender0_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR(6)
    );
  FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender0_CountLFSR_6_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender0_pStrobeOut_1290 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_ProbeTx,
      CE => FocusUnitCtrl0_StrobeExtender0_n0021,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FFY_RST,
      O => FocusUnitCtrl0_StrobeExtender0_pStrobeOut
    );
  FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_StrobeExtender0_pStrobeOut_FFY_RST
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_4 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(3),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(4)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(0),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(1)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_1_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_3 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(2),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(3)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_3_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_5 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(4),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(5)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_5_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_6 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(5),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(6)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFY_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_7 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(6),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFX_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(7)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_7_FFX_SET
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_8 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => FocusUnitCtrl0_StrobeExtender1_CountLFSR(7),
      CE => FocusUnitCtrl0_StrobeExtender1_n0007,
      CLK => SampleClk,
      SET => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FFY_SET,
      RST => GND,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR(8)
    );
  FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_SRMUX_OUTPUTNOT,
      O => FocusUnitCtrl0_StrobeExtender1_CountLFSR_8_FFY_SET
    );
  EncoderMonitor0_pSerialOutEn_1291 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_ShiftResults_2,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_pSerialOutEn_FFY_RST,
      O => EncoderMonitor0_pSerialOutEn
    );
  EncoderMonitor0_pSerialOutEn_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_pSerialOutEn_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_pSerialOutEn_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0321,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_vTrigCountMax_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_16_Q
    );
  EncoderMonitor0_vTrigCountMax_FFY_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_vTrigCountMax_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_vTrigCountMax_FFY_RST
    );
  EncoderMonitor0_vTrigCountMax_1292 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => EncoderMonitor0_n0295,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => EncoderMonitor0_vTrigCountMax_FFX_RST,
      O => EncoderMonitor0_vTrigCountMax
    );
  EncoderMonitor0_vTrigCountMax_FFX_RSTOR : X_OR2
    port map (
      I0 => EncoderMonitor0_vTrigCountMax_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => EncoderMonitor0_vTrigCountMax_FFX_RST
    );
  FocusUnitCtrl0_CtrlState_FFd9_1293 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd9_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd10_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd9
    );
  FocusUnitCtrl0_CtrlState_FFd10_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd10_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd10_1294 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd10_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd10_FFX_RST,
      O => FocusUnitCtrl0_CtrlState_FFd10
    );
  FocusUnitCtrl0_CtrlState_FFd10_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd10_FFX_RST
    );
  FocusUnitCtrl0_CtrlState_FFd11_1295 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd11_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd11_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd11
    );
  FocusUnitCtrl0_CtrlState_FFd11_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd11_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd2_1296 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd2_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd3_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd2
    );
  FocusUnitCtrl0_CtrlState_FFd3_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd3_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd4_1297 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50048,
      CE => FocusUnitCtrl0_DelayDone,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_CtrlState_FFd4_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd4
    );
  FocusUnitCtrl0_CtrlState_FFd4_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_CtrlState_FFd4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_CtrlState_FFd4_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_6_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_6_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(6)
    );
  FocusUnitCtrl0_pProbeData_6_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_6_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_7_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_7_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(7)
    );
  FocusUnitCtrl0_pProbeData_7_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_7_FFY_RST
    );
  FocusUnitCtrl0_CtrlState_FFd12_1298 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_CtrlState_FFd12_In,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_vLastTrigger_FFY_RST,
      O => FocusUnitCtrl0_CtrlState_FFd12
    );
  FocusUnitCtrl0_vLastTrigger_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_vLastTrigger_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_vLastTrigger_FFY_RST
    );
  FocusUnitCtrl0_vLastTrigger_1299 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => BScanCtrl0_pTriggerOut,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_vLastTrigger_FFX_RST,
      O => FocusUnitCtrl0_vLastTrigger
    );
  FocusUnitCtrl0_vLastTrigger_FFX_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_vLastTrigger_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_vLastTrigger_FFX_RST
    );
  FocusUnitCtrl0_pProbeDClock_1300 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0041,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeDClock_FFY_RST,
      O => FocusUnitCtrl0_pProbeDClock
    );
  FocusUnitCtrl0_pProbeDClock_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeDClock_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeDClock_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_0_13_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_0_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(0)
    );
  FocusUnitCtrl0_pProbeData_0_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_0_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_1_13_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_1_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(1)
    );
  FocusUnitCtrl0_pProbeData_1_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_1_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_2_13_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_2_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(2)
    );
  FocusUnitCtrl0_pProbeData_2_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_2_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_3_13_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_3_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(3)
    );
  FocusUnitCtrl0_pProbeData_3_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_3_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_5_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_5_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(5)
    );
  FocusUnitCtrl0_pProbeData_5_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_5_FFY_RST
    );
  FocusUnitCtrl0_pProbeData_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => FocusUnitCtrl0_n0046_4_O,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => FocusUnitCtrl0_pProbeData_4_FFY_RST,
      O => FocusUnitCtrl0_pProbeData(4)
    );
  FocusUnitCtrl0_pProbeData_4_FFY_RSTOR : X_OR2
    port map (
      I0 => FocusUnitCtrl0_pProbeData_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => FocusUnitCtrl0_pProbeData_4_FFY_RST
    );
  PerLBusInterface0_CalDacCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0275(2),
      CE => PerLBusInterface0_n0536,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacCount_3_FFY_RST,
      O => PerLBusInterface0_CalDacCount(2)
    );
  PerLBusInterface0_CalDacCount_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacCount_3_FFY_RST
    );
  PerLBusInterface0_CalDacCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0275(0),
      CE => PerLBusInterface0_n0536,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacCount_1_FFY_RST,
      O => PerLBusInterface0_CalDacCount(0)
    );
  PerLBusInterface0_CalDacCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacCount_1_FFY_RST
    );
  PerLBusInterface0_CalDacCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0275(1),
      CE => PerLBusInterface0_n0536,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacCount_1_FFX_RST,
      O => PerLBusInterface0_CalDacCount(1)
    );
  PerLBusInterface0_CalDacCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacCount_1_FFX_RST
    );
  PerLBusInterface0_CalDacCount_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0275(3),
      CE => PerLBusInterface0_n0536,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacCount_3_FFX_RST,
      O => PerLBusInterface0_CalDacCount(3)
    );
  PerLBusInterface0_CalDacCount_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacCount_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacCount_3_FFX_RST
    );
  PerLBusInterface0_CalDacCount_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0275(4),
      CE => PerLBusInterface0_n0536,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacCount_4_FFY_RST,
      O => PerLBusInterface0_CalDacCount(4)
    );
  PerLBusInterface0_CalDacCount_4_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacCount_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacCount_4_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(0),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_0_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(0)
    );
  PerLBusInterface0_CalDacShiftReg_0_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_0_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(10),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_10_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(10)
    );
  PerLBusInterface0_CalDacShiftReg_10_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_10_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(11),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_11_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(11)
    );
  PerLBusInterface0_CalDacShiftReg_11_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_11_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(7),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_7_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(7)
    );
  PerLBusInterface0_CalDacShiftReg_7_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_7_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(8),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_8_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(8)
    );
  PerLBusInterface0_CalDacShiftReg_8_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_8_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(9),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_9_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(9)
    );
  PerLBusInterface0_CalDacShiftReg_9_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_9_FFY_RST
    );
  PerLBusInterface0_CalDacStart_1301 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_CalDacStart_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacStart_FFY_RST,
      O => PerLBusInterface0_CalDacStart
    );
  PerLBusInterface0_CalDacStart_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_CalDacStart_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_CalDacStart_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0249,
      CE => PerLBusInterface0_n0458,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_0_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(0)
    );
  PerLBusInterface0_DelayValAddr_0_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_0_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0248,
      CE => PerLBusInterface0_n0458,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_1_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(1)
    );
  PerLBusInterface0_DelayValAddr_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_1_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0244,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_5_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(4)
    );
  PerLBusInterface0_DelayValAddr_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_5_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0246,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_3_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(2)
    );
  PerLBusInterface0_DelayValAddr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_3_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(12),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_12_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(12)
    );
  PerLBusInterface0_CalDacShiftReg_12_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_12_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(13),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_13_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(13)
    );
  PerLBusInterface0_CalDacShiftReg_13_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_13_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(1),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_1_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(1)
    );
  PerLBusInterface0_CalDacShiftReg_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_1_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(2),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_2_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(2)
    );
  PerLBusInterface0_CalDacShiftReg_2_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_2_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(3),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_3_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(3)
    );
  PerLBusInterface0_CalDacShiftReg_3_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_3_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(4),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_4_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(4)
    );
  PerLBusInterface0_CalDacShiftReg_4_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_4_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(5),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_5_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(5)
    );
  PerLBusInterface0_CalDacShiftReg_5_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_5_FFY_RST
    );
  PerLBusInterface0_CalDacShiftReg_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0280(6),
      CE => PerLBusInterface0_n0196,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_CalDacShiftReg_6_FFY_RST,
      O => PerLBusInterface0_CalDacShiftReg(6)
    );
  PerLBusInterface0_CalDacShiftReg_6_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_CalDacShiftReg_6_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0245,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_3_FFX_RST,
      O => PerLBusInterface0_DelayValAddr(3)
    );
  PerLBusInterface0_DelayValAddr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_3_FFX_RST
    );
  PerLBusInterface0_DelayValAddr_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0243,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_5_FFX_RST,
      O => PerLBusInterface0_DelayValAddr(5)
    );
  PerLBusInterface0_DelayValAddr_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_5_FFX_RST
    );
  PerLBusInterface0_DelayValAddr_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0242,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_7_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(6)
    );
  PerLBusInterface0_DelayValAddr_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_7_FFY_RST
    );
  PerLBusInterface0_DelayValAddr_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0241,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_7_FFX_RST,
      O => PerLBusInterface0_DelayValAddr(7)
    );
  PerLBusInterface0_DelayValAddr_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_7_FFX_RST
    );
  PerLBusInterface0_DelayValAddr_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0240,
      CE => PerLBusInterface0_n0450,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddr_8_FFY_RST,
      O => PerLBusInterface0_DelayValAddr(8)
    );
  PerLBusInterface0_DelayValAddr_8_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddr_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddr_8_FFY_RST
    );
  PerLBusInterface0_DelayValAddrRst_1302 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_DelayValAddrRst_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DelayValAddrRst_FFY_RST,
      O => PerLBusInterface0_DelayValAddrRst
    );
  PerLBusInterface0_DelayValAddrRst_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DelayValAddrRst_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DelayValAddrRst_FFY_RST
    );
  PerLBusInterface0_FocusCount_53_1303 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_FocusCount_inst_sum_124,
      CE => PerLBusInterface0_n0502,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusCount_53_FFY_RST,
      O => PerLBusInterface0_FocusCount_53
    );
  PerLBusInterface0_FocusCount_53_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusCount_53_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusCount_53_FFY_RST
    );
  PerLBusInterface0_FocusWrite_1304 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_DoFocus,
      CE => PerLBusInterface0_n0504,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusWrite_FFY_RST,
      O => PerLBusInterface0_FocusWrite
    );
  PerLBusInterface0_FocusWrite_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusWrite_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusWrite_FFY_RST
    );
  PerLBusInterface0_ForceBScan_1305 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0337,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ForceBScan_FFY_RST,
      O => PerLBusInterface0_ForceBScan
    );
  PerLBusInterface0_ForceBScan_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ForceBScan_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ForceBScan_FFY_RST
    );
  PerLBusInterface0_GateDataCount_47_1306 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_118,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_47_FFY_RST,
      O => PerLBusInterface0_GateDataCount_47
    );
  PerLBusInterface0_GateDataCount_47_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_47_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_47_FFY_RST
    );
  PerLBusInterface0_GateDataCount_49_1307 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_120,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_48_FFY_RST,
      O => PerLBusInterface0_GateDataCount_49
    );
  PerLBusInterface0_GateDataCount_48_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_48_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_48_FFY_RST
    );
  PerLBusInterface0_GateDataCount_51_1308 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_122,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_50_FFY_RST,
      O => PerLBusInterface0_GateDataCount_51
    );
  PerLBusInterface0_GateDataCount_50_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_50_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_50_FFY_RST
    );
  PerLBusInterface0_DoFocus_1309 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_DoFocus_FROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_DoFocus_FFX_RST,
      O => PerLBusInterface0_DoFocus
    );
  PerLBusInterface0_DoFocus_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_DoFocus_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_DoFocus_FFX_RST
    );
  PerLBusInterface0_FocusCount_55_1310 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_FocusCount_inst_sum_126,
      CE => PerLBusInterface0_n0502,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusCount_54_FFY_RST,
      O => PerLBusInterface0_FocusCount_55
    );
  PerLBusInterface0_FocusCount_54_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusCount_54_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusCount_54_FFY_RST
    );
  PerLBusInterface0_FocusCount_56_1311 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_FocusCount_inst_sum_127,
      CE => PerLBusInterface0_n0502,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusCount_56_FFX_RST,
      O => PerLBusInterface0_FocusCount_56
    );
  PerLBusInterface0_FocusCount_56_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusCount_56_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusCount_56_FFX_RST
    );
  PerLBusInterface0_FocusCount_54_1312 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_FocusCount_inst_sum_125,
      CE => PerLBusInterface0_n0502,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusCount_54_FFX_RST,
      O => PerLBusInterface0_FocusCount_54
    );
  PerLBusInterface0_FocusCount_54_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusCount_54_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusCount_54_FFX_RST
    );
  PerLBusInterface0_FocusCtrl_1313 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0264,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_FocusCtrl_FFY_RST,
      O => PerLBusInterface0_FocusCtrl
    );
  PerLBusInterface0_FocusCtrl_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_FocusCtrl_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_FocusCtrl_FFY_RST
    );
  PerLBusInterface0_GateDataCount_48_1314 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_119,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_48_FFX_RST,
      O => PerLBusInterface0_GateDataCount_48
    );
  PerLBusInterface0_GateDataCount_48_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_48_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_48_FFX_RST
    );
  PerLBusInterface0_GateDataCount_52_1315 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_123,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_52_FFX_RST,
      O => PerLBusInterface0_GateDataCount_52
    );
  PerLBusInterface0_GateDataCount_52_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_52_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_52_FFX_RST
    );
  PerLBusInterface0_GateDataCount_50_1316 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataCount_inst_sum_121,
      CE => PerLBusInterface0_n0499,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataCount_50_FFX_RST,
      O => PerLBusInterface0_GateDataCount_50
    );
  PerLBusInterface0_GateDataCount_50_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataCount_50_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataCount_50_FFX_RST
    );
  PerLBusInterface0_GateDataOut_1317 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataStart,
      CE => PerLBusInterface0_n0501,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataOut_FFY_RST,
      O => PerLBusInterface0_GateDataOut
    );
  PerLBusInterface0_GateDataOut_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataOut_FFY_RST
    );
  PerLBusInterface0_GateDataStart_1318 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataStart_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataStart_FFY_RST,
      O => PerLBusInterface0_GateDataStart
    );
  PerLBusInterface0_GateDataStart_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataStart_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataStart_FFY_RST
    );
  PerLBusInterface0_GateDataOut_1_1319 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataStart,
      CE => PerLBusInterface0_n0501,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_GateDataOut_1_FFY_RST,
      O => PerLBusInterface0_GateDataOut_1
    );
  PerLBusInterface0_GateDataOut_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_GateDataOut_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_GateDataOut_1_FFY_RST
    );
  PerLBusInterface0_IntAddr_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0218,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_FFY_RST,
      O => PerLBusInterface0_IntAddr(2)
    );
  PerLBusInterface0_IntAddr_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_FFY_RST
    );
  PerLBusInterface0_IntAddr_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0216,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_4_FFY_RST,
      O => PerLBusInterface0_IntAddr(4)
    );
  PerLBusInterface0_IntAddr_4_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_4_FFY_RST
    );
  PerLBusInterface0_IntAddr_3_1_1320 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_IntAddr_3_2_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_2_FFY_RST,
      O => PerLBusInterface0_IntAddr_3_1
    );
  PerLBusInterface0_IntAddr_3_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_2_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_63 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0316,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_3_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_63_Q
    );
  PerLBusInterface0_IntAddr_3_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_3_FFY_RST
    );
  PerLBusInterface0_IntAddr_3_2_1321 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0217,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_2_FFX_RST,
      O => PerLBusInterface0_IntAddr_3_2
    );
  PerLBusInterface0_IntAddr_3_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_2_FFX_RST
    );
  PerLBusInterface0_IntAddr_3_3_1322 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0217,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_3_FFX_RST,
      O => PerLBusInterface0_IntAddr_3_3
    );
  PerLBusInterface0_IntAddr_3_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_3_FFX_RST
    );
  PerLBusInterface0_IntAddr_4_1_1323 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_IntAddr_4_2_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_4_2_FFY_RST,
      O => PerLBusInterface0_IntAddr_4_1
    );
  PerLBusInterface0_IntAddr_4_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_4_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_4_2_FFY_RST
    );
  PerLBusInterface0_IntAddr_5_2_1324 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50978,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_5_2_FFY_RST,
      O => PerLBusInterface0_IntAddr_5_2
    );
  PerLBusInterface0_IntAddr_5_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_5_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_5_2_FFY_RST
    );
  PerLBusInterface0_IntAddr_4_2_1325 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0216,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_4_2_FFX_RST,
      O => PerLBusInterface0_IntAddr_4_2
    );
  PerLBusInterface0_IntAddr_4_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_4_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_4_2_FFX_RST
    );
  PerLBusInterface0_IntAddr_6_2_1326 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N51000,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_6_2_FFY_RST,
      O => PerLBusInterface0_IntAddr_6_2
    );
  PerLBusInterface0_IntAddr_6_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_6_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_6_2_FFY_RST
    );
  PerLBusInterface0_IntAddr_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0217,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_3_FFX_RST,
      O => PerLBusInterface0_IntAddr(3)
    );
  PerLBusInterface0_IntAddr_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_3_FFX_RST
    );
  PerLBusInterface0_IntAddr_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0215,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_5_FFX_RST,
      O => PerLBusInterface0_IntAddr(5)
    );
  PerLBusInterface0_IntAddr_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_5_FFX_RST
    );
  PerLBusInterface0_IntAddr_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0214,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_6_FFX_RST,
      O => PerLBusInterface0_IntAddr(6)
    );
  PerLBusInterface0_IntAddr_6_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_6_FFX_RST
    );
  PerLBusInterface0_IntAddr_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0213,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_7_FFX_RST,
      O => PerLBusInterface0_IntAddr(7)
    );
  PerLBusInterface0_IntAddr_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_7_FFX_RST
    );
  PerLBusInterface0_IntAddr_2_1_1327 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_IntAddr_2_2_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_2_2_FFY_RST,
      O => PerLBusInterface0_IntAddr_2_1
    );
  PerLBusInterface0_IntAddr_2_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_2_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_2_2_FFY_RST
    );
  PerLBusInterface0_IntAddr_2_3_1328 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0218,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_2_3_FFY_RST,
      O => PerLBusInterface0_IntAddr_2_3
    );
  PerLBusInterface0_IntAddr_2_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_2_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_2_3_FFY_RST
    );
  PerLBusInterface0_IntAddr_2_2_1329 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0218,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_IntAddr_2_2_FFX_RST,
      O => PerLBusInterface0_IntAddr_2_2
    );
  PerLBusInterface0_IntAddr_2_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_IntAddr_2_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_IntAddr_2_2_FFX_RST
    );
  PerLBusInterface0_ReadRegMask_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(29),
      CE => PerLBusInterface0_ReadRegMask_29_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_29_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(29)
    );
  PerLBusInterface0_ReadRegMask_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_29_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(2),
      CE => PerLBusInterface0_ReadRegMask_2_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_2_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(2)
    );
  PerLBusInterface0_ReadRegMask_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_2_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(30),
      CE => PerLBusInterface0_ReadRegMask_30_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_30_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(30)
    );
  PerLBusInterface0_ReadRegMask_30_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_30_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_30_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(3),
      CE => PerLBusInterface0_ReadRegMask_3_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_3_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(3)
    );
  PerLBusInterface0_ReadRegMask_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_3_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(4),
      CE => PerLBusInterface0_ReadRegMask_4_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_4_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(4)
    );
  PerLBusInterface0_ReadRegMask_4_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_4_FFY_RST
    );
  PerLBusInterface0_RegBank_19_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_6_FFX_RST,
      O => PerLBusInterface0_RegBank_19_6_Q
    );
  PerLBusInterface0_RegBank_19_6_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_6_FFX_RST
    );
  PerLBusInterface0_RegBank_19_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_8_FFX_RST,
      O => PerLBusInterface0_RegBank_19_8_Q
    );
  PerLBusInterface0_RegBank_19_8_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_8_FFX_RST
    );
  PerLBusInterface0_RegBank_0_12_1330 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_13_FFY_RST,
      O => PerLBusInterface0_RegBank_0_12
    );
  PerLBusInterface0_RegBank_0_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_13_FFY_RST
    );
  PerLBusInterface0_RegBank_0_1_1331 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_1_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_1
    );
  PerLBusInterface0_RegBank_0_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_1_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_1_FFX_SET
    );
  PerLBusInterface0_RegBank_0_11_1332 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_11_FFX_RST,
      O => PerLBusInterface0_RegBank_0_11
    );
  PerLBusInterface0_RegBank_0_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_11_FFX_RST
    );
  PerLBusInterface0_RegBank_0_13_1333 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_13_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_13
    );
  PerLBusInterface0_RegBank_0_13_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_13_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_13_FFX_SET
    );
  PerLBusInterface0_RegBank_0_14_1334 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_15_FFY_RST,
      O => PerLBusInterface0_RegBank_0_14
    );
  PerLBusInterface0_RegBank_0_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_15_FFY_RST
    );
  PerLBusInterface0_ReadRegData_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(18),
      CE => PerLBusInterface0_ReadRegData_19_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_19_FFY_RST,
      O => PerLBusInterface0_ReadRegData(18)
    );
  PerLBusInterface0_ReadRegData_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_19_FFY_RST
    );
  PerLBusInterface0_ReadRegData_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(17),
      CE => PerLBusInterface0_ReadRegData_17_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_17_FFX_RST,
      O => PerLBusInterface0_ReadRegData(17)
    );
  PerLBusInterface0_ReadRegData_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_17_FFX_RST
    );
  PerLBusInterface0_ReadRegData_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(0),
      CE => PerLBusInterface0_ReadRegData_1_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_1_FFY_RST,
      O => PerLBusInterface0_ReadRegData(0)
    );
  PerLBusInterface0_ReadRegData_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_1_FFY_RST
    );
  PerLBusInterface0_ReadRegData_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(19),
      CE => PerLBusInterface0_ReadRegData_19_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_19_FFX_RST,
      O => PerLBusInterface0_ReadRegData(19)
    );
  PerLBusInterface0_ReadRegData_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_19_FFX_RST
    );
  PerLBusInterface0_ReadRegData_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(20),
      CE => PerLBusInterface0_ReadRegData_21_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_21_FFY_RST,
      O => PerLBusInterface0_ReadRegData(20)
    );
  PerLBusInterface0_ReadRegData_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_21_FFY_RST
    );
  PerLBusInterface0_ReadRegData_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(1),
      CE => PerLBusInterface0_ReadRegData_1_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_1_FFX_RST,
      O => PerLBusInterface0_ReadRegData(1)
    );
  PerLBusInterface0_ReadRegData_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_1_FFX_RST
    );
  PerLBusInterface0_ReadRegData_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(24),
      CE => PerLBusInterface0_ReadRegData_25_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_25_FFY_RST,
      O => PerLBusInterface0_ReadRegData(24)
    );
  PerLBusInterface0_ReadRegData_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_25_FFY_RST
    );
  PerLBusInterface0_ReadRegData_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(22),
      CE => PerLBusInterface0_ReadRegData_23_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_23_FFY_RST,
      O => PerLBusInterface0_ReadRegData(22)
    );
  PerLBusInterface0_ReadRegData_23_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_23_FFY_RST
    );
  PerLBusInterface0_ReadRegData_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(21),
      CE => PerLBusInterface0_ReadRegData_21_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_21_FFX_RST,
      O => PerLBusInterface0_ReadRegData(21)
    );
  PerLBusInterface0_ReadRegData_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_21_FFX_RST
    );
  PerLBusInterface0_ReadRegData_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(10),
      CE => PerLBusInterface0_ReadRegData_11_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_11_FFY_RST,
      O => PerLBusInterface0_ReadRegData(10)
    );
  PerLBusInterface0_ReadRegData_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_11_FFY_RST
    );
  PerLBusInterface0_ReadRegData_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(12),
      CE => PerLBusInterface0_ReadRegData_13_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_13_FFY_RST,
      O => PerLBusInterface0_ReadRegData(12)
    );
  PerLBusInterface0_ReadRegData_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_13_FFY_RST
    );
  PerLBusInterface0_ReadRegData_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(11),
      CE => PerLBusInterface0_ReadRegData_11_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_11_FFX_RST,
      O => PerLBusInterface0_ReadRegData(11)
    );
  PerLBusInterface0_ReadRegData_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_11_FFX_RST
    );
  PerLBusInterface0_ReadRegData_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(14),
      CE => PerLBusInterface0_ReadRegData_15_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_15_FFY_RST,
      O => PerLBusInterface0_ReadRegData(14)
    );
  PerLBusInterface0_ReadRegData_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_15_FFY_RST
    );
  PerLBusInterface0_ReadRegData_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(13),
      CE => PerLBusInterface0_ReadRegData_13_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_13_FFX_RST,
      O => PerLBusInterface0_ReadRegData(13)
    );
  PerLBusInterface0_ReadRegData_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_13_FFX_RST
    );
  PerLBusInterface0_ReadRegData_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(16),
      CE => PerLBusInterface0_ReadRegData_17_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_17_FFY_RST,
      O => PerLBusInterface0_ReadRegData(16)
    );
  PerLBusInterface0_ReadRegData_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_17_FFY_RST
    );
  PerLBusInterface0_ReadRegData_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(15),
      CE => PerLBusInterface0_ReadRegData_15_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_15_FFX_RST,
      O => PerLBusInterface0_ReadRegData(15)
    );
  PerLBusInterface0_ReadRegData_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_15_FFX_RST
    );
  PerLBusInterface0_ReadRegData_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(23),
      CE => PerLBusInterface0_ReadRegData_23_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_23_FFX_RST,
      O => PerLBusInterface0_ReadRegData(23)
    );
  PerLBusInterface0_ReadRegData_23_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_23_FFX_RST
    );
  PerLBusInterface0_ReadRegData_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(26),
      CE => PerLBusInterface0_ReadRegData_27_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_27_FFY_RST,
      O => PerLBusInterface0_ReadRegData(26)
    );
  PerLBusInterface0_ReadRegData_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_27_FFY_RST
    );
  PerLBusInterface0_ReadRegData_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(25),
      CE => PerLBusInterface0_ReadRegData_25_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_25_FFX_RST,
      O => PerLBusInterface0_ReadRegData(25)
    );
  PerLBusInterface0_ReadRegData_25_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_25_FFX_RST
    );
  PerLBusInterface0_ReadRegData_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(28),
      CE => PerLBusInterface0_ReadRegData_29_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_29_FFY_RST,
      O => PerLBusInterface0_ReadRegData(28)
    );
  PerLBusInterface0_ReadRegData_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_29_FFY_RST
    );
  PerLBusInterface0_ReadRegData_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(27),
      CE => PerLBusInterface0_ReadRegData_27_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_27_FFX_RST,
      O => PerLBusInterface0_ReadRegData(27)
    );
  PerLBusInterface0_ReadRegData_27_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_27_FFX_RST
    );
  PerLBusInterface0_ReadRegData_30 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(30),
      CE => PerLBusInterface0_ReadRegData_31_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_31_FFY_RST,
      O => PerLBusInterface0_ReadRegData(30)
    );
  PerLBusInterface0_ReadRegData_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_31_FFY_RST
    );
  PerLBusInterface0_ReadRegData_29 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(29),
      CE => PerLBusInterface0_ReadRegData_29_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_29_FFX_RST,
      O => PerLBusInterface0_ReadRegData(29)
    );
  PerLBusInterface0_ReadRegData_29_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_29_FFX_RST
    );
  PerLBusInterface0_ReadRegData_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(2),
      CE => PerLBusInterface0_ReadRegData_3_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_3_FFY_RST,
      O => PerLBusInterface0_ReadRegData(2)
    );
  PerLBusInterface0_ReadRegData_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_3_FFY_RST
    );
  PerLBusInterface0_ReadRegData_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(31),
      CE => PerLBusInterface0_ReadRegData_31_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_31_FFX_RST,
      O => PerLBusInterface0_ReadRegData(31)
    );
  PerLBusInterface0_ReadRegData_31_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_31_FFX_RST
    );
  PerLBusInterface0_ReadRegData_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(4),
      CE => PerLBusInterface0_ReadRegData_5_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_5_FFY_RST,
      O => PerLBusInterface0_ReadRegData(4)
    );
  PerLBusInterface0_ReadRegData_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_5_FFY_RST
    );
  PerLBusInterface0_ReadRegData_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(3),
      CE => PerLBusInterface0_ReadRegData_3_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_3_FFX_RST,
      O => PerLBusInterface0_ReadRegData(3)
    );
  PerLBusInterface0_ReadRegData_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_3_FFX_RST
    );
  PerLBusInterface0_ReadRegData_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(6),
      CE => PerLBusInterface0_ReadRegData_7_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_7_FFY_RST,
      O => PerLBusInterface0_ReadRegData(6)
    );
  PerLBusInterface0_ReadRegData_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_7_FFY_RST
    );
  PerLBusInterface0_ReadRegData_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(5),
      CE => PerLBusInterface0_ReadRegData_5_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_5_FFX_RST,
      O => PerLBusInterface0_ReadRegData(5)
    );
  PerLBusInterface0_ReadRegData_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_5_FFX_RST
    );
  PerLBusInterface0_ReadRegData_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(8),
      CE => PerLBusInterface0_ReadRegData_9_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_9_FFY_RST,
      O => PerLBusInterface0_ReadRegData(8)
    );
  PerLBusInterface0_ReadRegData_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_9_FFY_RST
    );
  PerLBusInterface0_ReadRegData_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(7),
      CE => PerLBusInterface0_ReadRegData_7_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_7_FFX_RST,
      O => PerLBusInterface0_ReadRegData(7)
    );
  PerLBusInterface0_ReadRegData_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_7_FFX_RST
    );
  PerLBusInterface0_ReadRegMask_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(0),
      CE => PerLBusInterface0_ReadRegMask_0_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_0_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(0)
    );
  PerLBusInterface0_ReadRegMask_0_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_0_FFY_RST
    );
  PerLBusInterface0_ReadRegData_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ReadRegDataMux(9),
      CE => PerLBusInterface0_ReadRegData_9_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegData_9_FFX_RST,
      O => PerLBusInterface0_ReadRegData(9)
    );
  PerLBusInterface0_ReadRegData_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegData_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegData_9_FFX_RST
    );
  PerLBusInterface0_RegBank_1_1_1335 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_1_FFX_RST,
      O => PerLBusInterface0_RegBank_1_1
    );
  PerLBusInterface0_RegBank_1_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_1_FFX_RST
    );
  PerLBusInterface0_RegBank_1_11_1336 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_11_FFX_RST,
      O => PerLBusInterface0_RegBank_1_11
    );
  PerLBusInterface0_RegBank_1_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_11_FFX_RST
    );
  PerLBusInterface0_RegBank_1_12_1337 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_13_FFY_RST,
      O => PerLBusInterface0_RegBank_1_12
    );
  PerLBusInterface0_RegBank_1_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_13_FFY_RST
    );
  PerLBusInterface0_RegBank_1_13_1338 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_13_FFX_RST,
      O => PerLBusInterface0_RegBank_1_13
    );
  PerLBusInterface0_RegBank_1_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_13_FFX_RST
    );
  PerLBusInterface0_RegBank_1_14_1339 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_15_FFY_RST,
      O => PerLBusInterface0_RegBank_1_14
    );
  PerLBusInterface0_RegBank_1_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_15_FFY_RST
    );
  PerLBusInterface0_RegBank_1_15_1340 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_15_FFX_RST,
      O => PerLBusInterface0_RegBank_1_15
    );
  PerLBusInterface0_RegBank_1_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_15_FFX_RST
    );
  PerLBusInterface0_RegBank_1_16_1341 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49924,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_1_16_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_1_16
    );
  PerLBusInterface0_RegBank_1_16_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_1_16_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_1_16_FFY_SET
    );
  PerLBusInterface0_RegBank_1_2_1342 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_3_FFY_RST,
      O => PerLBusInterface0_RegBank_1_2
    );
  PerLBusInterface0_RegBank_1_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_3_FFY_RST
    );
  PerLBusInterface0_RegBank_1_3_1343 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_3_FFX_RST,
      O => PerLBusInterface0_RegBank_1_3
    );
  PerLBusInterface0_RegBank_1_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_3_FFX_RST
    );
  PerLBusInterface0_RegBank_1_4_1344 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_5_FFY_RST,
      O => PerLBusInterface0_RegBank_1_4
    );
  PerLBusInterface0_RegBank_1_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_5_FFY_RST
    );
  PerLBusInterface0_RegBank_1_5_1345 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_5_FFX_RST,
      O => PerLBusInterface0_RegBank_1_5
    );
  PerLBusInterface0_RegBank_1_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_5_FFX_RST
    );
  PerLBusInterface0_RegBank_1_6_1346 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_7_FFY_RST,
      O => PerLBusInterface0_RegBank_1_6
    );
  PerLBusInterface0_RegBank_1_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_7_FFY_RST
    );
  PerLBusInterface0_RegBank_1_7_1347 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_7_FFX_RST,
      O => PerLBusInterface0_RegBank_1_7
    );
  PerLBusInterface0_RegBank_1_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_7_FFX_RST
    );
  PerLBusInterface0_RegBank_1_8_1348 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_9_FFY_RST,
      O => PerLBusInterface0_RegBank_1_8
    );
  PerLBusInterface0_RegBank_1_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_9_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_24 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(24),
      CE => PerLBusInterface0_ReadRegMask_24_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_24_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(24)
    );
  PerLBusInterface0_ReadRegMask_24_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_24_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_24_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_25 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(25),
      CE => PerLBusInterface0_ReadRegMask_25_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_25_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(25)
    );
  PerLBusInterface0_ReadRegMask_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_25_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_26 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(26),
      CE => PerLBusInterface0_ReadRegMask_26_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_26_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(26)
    );
  PerLBusInterface0_ReadRegMask_26_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_26_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_26_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_27 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(27),
      CE => PerLBusInterface0_ReadRegMask_27_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_27_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(27)
    );
  PerLBusInterface0_ReadRegMask_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_27_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_28 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(28),
      CE => PerLBusInterface0_ReadRegMask_28_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_28_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(28)
    );
  PerLBusInterface0_ReadRegMask_28_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_28_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_28_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(10),
      CE => PerLBusInterface0_ReadRegMask_10_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_10_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(10)
    );
  PerLBusInterface0_ReadRegMask_10_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_10_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_11 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(11),
      CE => PerLBusInterface0_ReadRegMask_11_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_11_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(11)
    );
  PerLBusInterface0_ReadRegMask_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_11_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_12 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(12),
      CE => PerLBusInterface0_ReadRegMask_12_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_12_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(12)
    );
  PerLBusInterface0_ReadRegMask_12_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_12_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_12_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_13 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(13),
      CE => PerLBusInterface0_ReadRegMask_13_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_13_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(13)
    );
  PerLBusInterface0_ReadRegMask_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_13_FFY_RST
    );
  PerLBusInterface0_RegBank_14_15_1349 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(15),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_15_FFX_RST,
      O => PerLBusInterface0_RegBank_14_15
    );
  PerLBusInterface0_RegBank_14_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_15_FFX_RST
    );
  PerLBusInterface0_RegBank_14_18_1350 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(18),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_19_FFY_RST,
      O => PerLBusInterface0_RegBank_14_18
    );
  PerLBusInterface0_RegBank_14_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_19_FFY_RST
    );
  PerLBusInterface0_RegBank_14_17_1351 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(17),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_17_FFX_RST,
      O => PerLBusInterface0_RegBank_14_17
    );
  PerLBusInterface0_RegBank_14_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_17_FFX_RST
    );
  PerLBusInterface0_RegBank_14_22_1352 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(22),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_2_FFY_RST,
      O => PerLBusInterface0_RegBank_14_22
    );
  PerLBusInterface0_RegBank_14_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_2_FFY_RST
    );
  PerLBusInterface0_RegBank_14_19_1353 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(19),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_19_FFX_RST,
      O => PerLBusInterface0_RegBank_14_19
    );
  PerLBusInterface0_RegBank_14_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_19_FFX_RST
    );
  PerLBusInterface0_RegBank_14_2_1354 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(2),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_2_FFX_RST,
      O => PerLBusInterface0_RegBank_14_2
    );
  PerLBusInterface0_RegBank_14_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_2_FFX_RST
    );
  PerLBusInterface0_RegBank_14_21_1355 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(21),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_21_FFX_RST,
      O => PerLBusInterface0_RegBank_14_21
    );
  PerLBusInterface0_RegBank_14_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_21_FFX_RST
    );
  PerLBusInterface0_RegBank_14_24_1356 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(24),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_25_FFY_RST,
      O => PerLBusInterface0_RegBank_14_24
    );
  PerLBusInterface0_RegBank_14_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_25_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_14 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(14),
      CE => PerLBusInterface0_ReadRegMask_14_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_14_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(14)
    );
  PerLBusInterface0_ReadRegMask_14_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_14_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(15),
      CE => PerLBusInterface0_ReadRegMask_15_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_15_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(15)
    );
  PerLBusInterface0_ReadRegMask_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_15_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_16 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(16),
      CE => PerLBusInterface0_ReadRegMask_17_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_17_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(16)
    );
  PerLBusInterface0_ReadRegMask_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_17_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(17),
      CE => PerLBusInterface0_ReadRegMask_17_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_17_FFX_RST,
      O => PerLBusInterface0_ReadRegMask(17)
    );
  PerLBusInterface0_ReadRegMask_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_17_FFX_RST
    );
  PerLBusInterface0_ReadRegMask_31 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(31),
      CE => PerLBusInterface0_ReadRegMask_18_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_18_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(31)
    );
  PerLBusInterface0_ReadRegMask_18_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_18_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(18),
      CE => PerLBusInterface0_ReadRegMask_18_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_18_FFX_RST,
      O => PerLBusInterface0_ReadRegMask(18)
    );
  PerLBusInterface0_ReadRegMask_18_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_18_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_18_FFX_RST
    );
  PerLBusInterface0_ReadRegMask_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(19),
      CE => PerLBusInterface0_ReadRegMask_19_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_19_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(19)
    );
  PerLBusInterface0_ReadRegMask_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_19_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(1),
      CE => PerLBusInterface0_ReadRegMask_1_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_1_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(1)
    );
  PerLBusInterface0_ReadRegMask_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_1_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_20 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(20),
      CE => PerLBusInterface0_ReadRegMask_21_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_21_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(20)
    );
  PerLBusInterface0_ReadRegMask_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_21_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_21 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(21),
      CE => PerLBusInterface0_ReadRegMask_21_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_21_FFX_RST,
      O => PerLBusInterface0_ReadRegMask(21)
    );
  PerLBusInterface0_ReadRegMask_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_21_FFX_RST
    );
  PerLBusInterface0_ReadRegMask_22 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(22),
      CE => PerLBusInterface0_ReadRegMask_22_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_22_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(22)
    );
  PerLBusInterface0_ReadRegMask_22_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_22_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_22_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_23 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(23),
      CE => PerLBusInterface0_ReadRegMask_23_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_23_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(23)
    );
  PerLBusInterface0_ReadRegMask_23_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_23_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(5),
      CE => PerLBusInterface0_ReadRegMask_5_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_5_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(5)
    );
  PerLBusInterface0_ReadRegMask_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_5_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(6),
      CE => PerLBusInterface0_ReadRegMask_6_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_6_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(6)
    );
  PerLBusInterface0_ReadRegMask_6_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_6_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(7),
      CE => PerLBusInterface0_ReadRegMask_7_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_7_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(7)
    );
  PerLBusInterface0_ReadRegMask_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_7_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(8),
      CE => PerLBusInterface0_ReadRegMask_8_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_8_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(8)
    );
  PerLBusInterface0_ReadRegMask_8_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_8_FFY_RST
    );
  PerLBusInterface0_ReadRegMask_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0180(9),
      CE => PerLBusInterface0_ReadRegMask_9_CEMUXNOT,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_ReadRegMask_9_FFY_RST,
      O => PerLBusInterface0_ReadRegMask(9)
    );
  PerLBusInterface0_ReadRegMask_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_ReadRegMask_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_ReadRegMask_9_FFY_RST
    );
  PerLBusInterface0_RegBank_19_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_10_FFY_RST,
      O => PerLBusInterface0_RegBank_19_9_Q
    );
  PerLBusInterface0_RegBank_19_10_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_10_FFY_RST
    );
  PerLBusInterface0_RegBank_19_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_10_FFX_RST,
      O => PerLBusInterface0_RegBank_19_10_Q
    );
  PerLBusInterface0_RegBank_19_10_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_10_FFX_RST
    );
  PerLBusInterface0_RegBank_19_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_2_FFX_RST,
      O => PerLBusInterface0_RegBank_19_2_Q
    );
  PerLBusInterface0_RegBank_19_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_2_FFX_RST
    );
  PerLBusInterface0_RegBank_19_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_4_FFY_RST,
      O => PerLBusInterface0_RegBank_19_3_Q
    );
  PerLBusInterface0_RegBank_19_4_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_4_FFY_RST
    );
  PerLBusInterface0_RegBank_19_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_19_4_FFX_RST,
      O => PerLBusInterface0_RegBank_19_4_Q
    );
  PerLBusInterface0_RegBank_19_4_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_19_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_19_4_FFX_RST
    );
  PerLBusInterface0_RegBank_0_15_1357 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_15_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_15
    );
  PerLBusInterface0_RegBank_0_15_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_15_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_15_FFX_SET
    );
  PerLBusInterface0_RegBank_0_19_1358 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49936,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_19_FFX_RST,
      O => PerLBusInterface0_RegBank_0_19
    );
  PerLBusInterface0_RegBank_0_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_19_FFX_RST
    );
  PerLBusInterface0_RegBank_0_21_1359 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49926,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_21_FFX_RST,
      O => PerLBusInterface0_RegBank_0_21
    );
  PerLBusInterface0_RegBank_0_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_21_FFX_RST
    );
  PerLBusInterface0_RegBank_0_2_1360 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_3_FFY_RST,
      O => PerLBusInterface0_RegBank_0_2
    );
  PerLBusInterface0_RegBank_0_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_3_FFY_RST
    );
  PerLBusInterface0_RegBank_0_23_1361 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49934,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_23_FFX_RST,
      O => PerLBusInterface0_RegBank_0_23
    );
  PerLBusInterface0_RegBank_0_23_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_23_FFX_RST
    );
  PerLBusInterface0_RegBank_0_3_1362 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_3_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_3
    );
  PerLBusInterface0_RegBank_0_3_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_3_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_3_FFX_SET
    );
  PerLBusInterface0_RegBank_0_4_1363 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_5_FFY_RST,
      O => PerLBusInterface0_RegBank_0_4
    );
  PerLBusInterface0_RegBank_0_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_5_FFY_RST
    );
  PerLBusInterface0_RegBank_0_5_1364 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_5_FFX_RST,
      O => PerLBusInterface0_RegBank_0_5
    );
  PerLBusInterface0_RegBank_0_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_5_FFX_RST
    );
  PerLBusInterface0_RegBank_0_6_1365 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_0_7_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_6
    );
  PerLBusInterface0_RegBank_0_7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_0_7_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_0_7_FFY_SET
    );
  PerLBusInterface0_RegBank_0_7_1366 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_7_FFX_RST,
      O => PerLBusInterface0_RegBank_0_7
    );
  PerLBusInterface0_RegBank_0_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_7_FFX_RST
    );
  PerLBusInterface0_RegBank_0_8_1367 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_9_FFY_RST,
      O => PerLBusInterface0_RegBank_0_8
    );
  PerLBusInterface0_RegBank_0_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_9_FFY_RST
    );
  PerLBusInterface0_RegBank_0_9_1368 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_0_9_FFX_RST,
      O => PerLBusInterface0_RegBank_0_9
    );
  PerLBusInterface0_RegBank_0_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_0_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_0_9_FFX_RST
    );
  PerLBusInterface0_RegBank_14_0_1369 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(0),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_1_FFY_RST,
      O => PerLBusInterface0_RegBank_14_0
    );
  PerLBusInterface0_RegBank_14_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_1_FFY_RST
    );
  PerLBusInterface0_RegBank_14_12_1370 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(12),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_13_FFY_RST,
      O => PerLBusInterface0_RegBank_14_12
    );
  PerLBusInterface0_RegBank_14_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_13_FFY_RST
    );
  PerLBusInterface0_RegBank_14_1_1371 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(1),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_1_FFX_RST,
      O => PerLBusInterface0_RegBank_14_1
    );
  PerLBusInterface0_RegBank_14_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_1_FFX_RST
    );
  PerLBusInterface0_RegBank_14_11_1372 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(11),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_11_FFX_RST,
      O => PerLBusInterface0_RegBank_14_11
    );
  PerLBusInterface0_RegBank_14_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_11_FFX_RST
    );
  PerLBusInterface0_RegBank_14_14_1373 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(14),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_15_FFY_RST,
      O => PerLBusInterface0_RegBank_14_14
    );
  PerLBusInterface0_RegBank_14_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_15_FFY_RST
    );
  PerLBusInterface0_RegBank_14_13_1374 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(13),
      CE => PerLBusInterface0_n0482,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_13_FFX_RST,
      O => PerLBusInterface0_RegBank_14_13
    );
  PerLBusInterface0_RegBank_14_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_13_FFX_RST
    );
  PerLBusInterface0_RegBank_15_3_1375 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(3),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_3_FFX_RST,
      O => PerLBusInterface0_RegBank_15_3
    );
  PerLBusInterface0_RegBank_15_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_3_FFX_RST
    );
  PerLBusInterface0_RegBank_15_31_1376 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(31),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_31_FFX_RST,
      O => PerLBusInterface0_RegBank_15_31
    );
  PerLBusInterface0_RegBank_15_31_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_31_FFX_RST
    );
  PerLBusInterface0_RegBank_15_4_1377 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(4),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_5_FFY_RST,
      O => PerLBusInterface0_RegBank_15_4
    );
  PerLBusInterface0_RegBank_15_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_5_FFY_RST
    );
  PerLBusInterface0_RegBank_15_6_1378 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(6),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_7_FFY_RST,
      O => PerLBusInterface0_RegBank_15_6
    );
  PerLBusInterface0_RegBank_15_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_7_FFY_RST
    );
  PerLBusInterface0_RegBank_15_5_1379 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(5),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_5_FFX_RST,
      O => PerLBusInterface0_RegBank_15_5
    );
  PerLBusInterface0_RegBank_15_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_5_FFX_RST
    );
  PerLBusInterface0_RegBank_15_8_1380 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(8),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_9_FFY_RST,
      O => PerLBusInterface0_RegBank_15_8
    );
  PerLBusInterface0_RegBank_15_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_9_FFY_RST
    );
  PerLBusInterface0_RegBank_15_7_1381 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(7),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_7_FFX_RST,
      O => PerLBusInterface0_RegBank_15_7
    );
  PerLBusInterface0_RegBank_15_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_7_FFX_RST
    );
  PerLBusInterface0_RegBank_16_0_1382 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0486,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_16_1_FFY_RST,
      O => PerLBusInterface0_RegBank_16_0
    );
  PerLBusInterface0_RegBank_16_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_16_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_16_1_FFY_RST
    );
  PerLBusInterface0_RegBank_14_28_1383 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(28),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_29_FFY_RST,
      O => PerLBusInterface0_RegBank_14_28
    );
  PerLBusInterface0_RegBank_14_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_29_FFY_RST
    );
  PerLBusInterface0_RegBank_14_25_1384 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(25),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_25_FFX_RST,
      O => PerLBusInterface0_RegBank_14_25
    );
  PerLBusInterface0_RegBank_14_25_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_25_FFX_RST
    );
  PerLBusInterface0_RegBank_14_27_1385 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(27),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_27_FFX_RST,
      O => PerLBusInterface0_RegBank_14_27
    );
  PerLBusInterface0_RegBank_14_27_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_27_FFX_RST
    );
  PerLBusInterface0_RegBank_14_23_1386 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(23),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_3_FFY_RST,
      O => PerLBusInterface0_RegBank_14_23
    );
  PerLBusInterface0_RegBank_14_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_3_FFY_RST
    );
  PerLBusInterface0_RegBank_14_29_1387 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(29),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_29_FFX_RST,
      O => PerLBusInterface0_RegBank_14_29
    );
  PerLBusInterface0_RegBank_14_29_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_29_FFX_RST
    );
  PerLBusInterface0_RegBank_14_30_1388 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(30),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_31_FFY_RST,
      O => PerLBusInterface0_RegBank_14_30
    );
  PerLBusInterface0_RegBank_14_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_31_FFY_RST
    );
  PerLBusInterface0_RegBank_14_3_1389 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(3),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_3_FFX_RST,
      O => PerLBusInterface0_RegBank_14_3
    );
  PerLBusInterface0_RegBank_14_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_3_FFX_RST
    );
  PerLBusInterface0_RegBank_14_4_1390 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(4),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_5_FFY_RST,
      O => PerLBusInterface0_RegBank_14_4
    );
  PerLBusInterface0_RegBank_14_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_5_FFY_RST
    );
  PerLBusInterface0_RegBank_14_31_1391 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(31),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_31_FFX_RST,
      O => PerLBusInterface0_RegBank_14_31
    );
  PerLBusInterface0_RegBank_14_31_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_31_FFX_RST
    );
  PerLBusInterface0_RegBank_15_2_1392 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(2),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_2_FFX_RST,
      O => PerLBusInterface0_RegBank_15_2
    );
  PerLBusInterface0_RegBank_15_2_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_2_FFX_RST
    );
  PerLBusInterface0_RegBank_15_21_1393 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(21),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_21_FFX_RST,
      O => PerLBusInterface0_RegBank_15_21
    );
  PerLBusInterface0_RegBank_15_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_21_FFX_RST
    );
  PerLBusInterface0_RegBank_15_24_1394 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(24),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_25_FFY_RST,
      O => PerLBusInterface0_RegBank_15_24
    );
  PerLBusInterface0_RegBank_15_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_25_FFY_RST
    );
  PerLBusInterface0_RegBank_15_28_1395 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(28),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_29_FFY_RST,
      O => PerLBusInterface0_RegBank_15_28
    );
  PerLBusInterface0_RegBank_15_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_29_FFY_RST
    );
  PerLBusInterface0_RegBank_15_25_1396 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(25),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_25_FFX_RST,
      O => PerLBusInterface0_RegBank_15_25
    );
  PerLBusInterface0_RegBank_15_25_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_25_FFX_RST
    );
  PerLBusInterface0_RegBank_15_27_1397 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(27),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_27_FFX_RST,
      O => PerLBusInterface0_RegBank_15_27
    );
  PerLBusInterface0_RegBank_15_27_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_27_FFX_RST
    );
  PerLBusInterface0_RegBank_15_23_1398 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(23),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_3_FFY_RST,
      O => PerLBusInterface0_RegBank_15_23
    );
  PerLBusInterface0_RegBank_15_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_3_FFY_RST
    );
  PerLBusInterface0_RegBank_15_29_1399 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(29),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_29_FFX_RST,
      O => PerLBusInterface0_RegBank_15_29
    );
  PerLBusInterface0_RegBank_15_29_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_29_FFX_RST
    );
  PerLBusInterface0_RegBank_15_14_1400 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(14),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_15_FFY_RST,
      O => PerLBusInterface0_RegBank_15_14
    );
  PerLBusInterface0_RegBank_15_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_15_FFY_RST
    );
  PerLBusInterface0_RegBank_15_11_1401 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(11),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_11_FFX_RST,
      O => PerLBusInterface0_RegBank_15_11
    );
  PerLBusInterface0_RegBank_15_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_11_FFX_RST
    );
  PerLBusInterface0_RegBank_15_13_1402 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(13),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_13_FFX_RST,
      O => PerLBusInterface0_RegBank_15_13
    );
  PerLBusInterface0_RegBank_15_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_13_FFX_RST
    );
  PerLBusInterface0_RegBank_15_16_1403 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(16),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_17_FFY_RST,
      O => PerLBusInterface0_RegBank_15_16
    );
  PerLBusInterface0_RegBank_15_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_17_FFY_RST
    );
  PerLBusInterface0_RegBank_15_15_1404 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(15),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_15_FFX_RST,
      O => PerLBusInterface0_RegBank_15_15
    );
  PerLBusInterface0_RegBank_15_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_15_FFX_RST
    );
  PerLBusInterface0_RegBank_15_18_1405 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(18),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_19_FFY_RST,
      O => PerLBusInterface0_RegBank_15_18
    );
  PerLBusInterface0_RegBank_15_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_19_FFY_RST
    );
  PerLBusInterface0_RegBank_15_17_1406 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(17),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_17_FFX_RST,
      O => PerLBusInterface0_RegBank_15_17
    );
  PerLBusInterface0_RegBank_15_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_17_FFX_RST
    );
  PerLBusInterface0_RegBank_15_22_1407 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(22),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_2_FFY_RST,
      O => PerLBusInterface0_RegBank_15_22
    );
  PerLBusInterface0_RegBank_15_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_2_FFY_RST
    );
  PerLBusInterface0_RegBank_15_19_1408 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(19),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_19_FFX_RST,
      O => PerLBusInterface0_RegBank_15_19
    );
  PerLBusInterface0_RegBank_15_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_19_FFX_RST
    );
  PerLBusInterface0_RegBank_14_5_1409 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(5),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_5_FFX_RST,
      O => PerLBusInterface0_RegBank_14_5
    );
  PerLBusInterface0_RegBank_14_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_5_FFX_RST
    );
  PerLBusInterface0_RegBank_14_8_1410 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(8),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_9_FFY_RST,
      O => PerLBusInterface0_RegBank_14_8
    );
  PerLBusInterface0_RegBank_14_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_9_FFY_RST
    );
  PerLBusInterface0_RegBank_14_7_1411 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(7),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_7_FFX_RST,
      O => PerLBusInterface0_RegBank_14_7
    );
  PerLBusInterface0_RegBank_14_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_7_FFX_RST
    );
  PerLBusInterface0_RegBank_14_9_1412 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0250(9),
      CE => PerLBusInterface0_n04821_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_14_9_FFX_RST,
      O => PerLBusInterface0_RegBank_14_9
    );
  PerLBusInterface0_RegBank_14_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_14_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_14_9_FFX_RST
    );
  PerLBusInterface0_RegBank_15_0_1413 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(0),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_1_FFY_RST,
      O => PerLBusInterface0_RegBank_15_0
    );
  PerLBusInterface0_RegBank_15_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_1_FFY_RST
    );
  PerLBusInterface0_RegBank_15_10_1414 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(10),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_11_FFY_RST,
      O => PerLBusInterface0_RegBank_15_10
    );
  PerLBusInterface0_RegBank_15_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_11_FFY_RST
    );
  PerLBusInterface0_RegBank_15_1_1415 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(1),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_1_FFX_RST,
      O => PerLBusInterface0_RegBank_15_1
    );
  PerLBusInterface0_RegBank_15_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_1_FFX_RST
    );
  PerLBusInterface0_RegBank_15_12_1416 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(12),
      CE => PerLBusInterface0_n0484,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_13_FFY_RST,
      O => PerLBusInterface0_RegBank_15_12
    );
  PerLBusInterface0_RegBank_15_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_13_FFY_RST
    );
  PerLBusInterface0_RegBank_7_1_1417 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_1_FFX_RST,
      O => PerLBusInterface0_RegBank_7_1
    );
  PerLBusInterface0_RegBank_7_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_1_FFX_RST
    );
  PerLBusInterface0_RegBank_7_11_1418 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_11_FFX_RST,
      O => PerLBusInterface0_RegBank_7_11
    );
  PerLBusInterface0_RegBank_7_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_11_FFX_RST
    );
  PerLBusInterface0_RegBank_7_12_1419 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_13_FFY_RST,
      O => PerLBusInterface0_RegBank_7_12
    );
  PerLBusInterface0_RegBank_7_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_13_FFY_RST
    );
  PerLBusInterface0_RegBank_7_13_1420 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_13_FFX_RST,
      O => PerLBusInterface0_RegBank_7_13
    );
  PerLBusInterface0_RegBank_7_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_13_FFX_RST
    );
  PerLBusInterface0_RegBank_7_14_1421 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_15_FFY_RST,
      O => PerLBusInterface0_RegBank_7_14
    );
  PerLBusInterface0_RegBank_7_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_15_FFY_RST
    );
  PerLBusInterface0_RegBank_7_15_1422 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_15_FFX_RST,
      O => PerLBusInterface0_RegBank_7_15
    );
  PerLBusInterface0_RegBank_7_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_15_FFX_RST
    );
  PerLBusInterface0_RegBank_7_16_1423 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49924,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_7_17_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_7_16
    );
  PerLBusInterface0_RegBank_7_17_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_7_17_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_7_17_FFY_SET
    );
  PerLBusInterface0_RegBank_7_17_1424 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49928,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_7_17_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_7_17
    );
  PerLBusInterface0_RegBank_7_17_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_7_17_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_7_17_FFX_SET
    );
  PerLBusInterface0_RegBank_7_18_1425 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49932,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_7_18_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_7_18
    );
  PerLBusInterface0_RegBank_7_18_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_7_18_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_7_18_FFY_SET
    );
  PerLBusInterface0_RegBank_7_4_1426 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_7_5_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_7_4
    );
  PerLBusInterface0_RegBank_7_5_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_7_5_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_7_5_FFY_SET
    );
  PerLBusInterface0_RegBank_7_2_1427 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_3_FFY_RST,
      O => PerLBusInterface0_RegBank_7_2
    );
  PerLBusInterface0_RegBank_7_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_3_FFY_RST
    );
  PerLBusInterface0_RegBank_4_11_1428 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_11_FFX_RST,
      O => PerLBusInterface0_RegBank_4_11
    );
  PerLBusInterface0_RegBank_4_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_11_FFX_RST
    );
  PerLBusInterface0_RegBank_4_12_1429 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_13_FFY_RST,
      O => PerLBusInterface0_RegBank_4_12
    );
  PerLBusInterface0_RegBank_4_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_13_FFY_RST
    );
  PerLBusInterface0_RegBank_4_13_1430 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_13_FFX_RST,
      O => PerLBusInterface0_RegBank_4_13
    );
  PerLBusInterface0_RegBank_4_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_13_FFX_RST
    );
  PerLBusInterface0_RegBank_4_14_1431 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_15_FFY_RST,
      O => PerLBusInterface0_RegBank_4_14
    );
  PerLBusInterface0_RegBank_4_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_15_FFY_RST
    );
  PerLBusInterface0_RegBank_4_15_1432 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_15_FFX_RST,
      O => PerLBusInterface0_RegBank_4_15
    );
  PerLBusInterface0_RegBank_4_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_15_FFX_RST
    );
  PerLBusInterface0_RegBank_4_16_1433 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49924,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_20_FFY_RST,
      O => PerLBusInterface0_RegBank_4_16
    );
  PerLBusInterface0_RegBank_4_20_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_20_FFY_RST
    );
  PerLBusInterface0_RegBank_4_4_1434 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_5_FFY_RST,
      O => PerLBusInterface0_RegBank_4_4
    );
  PerLBusInterface0_RegBank_4_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_5_FFY_RST
    );
  PerLBusInterface0_RegBank_4_21_1435 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49926,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_21_FFY_RST,
      O => PerLBusInterface0_RegBank_4_21
    );
  PerLBusInterface0_RegBank_4_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_21_FFY_RST
    );
  PerLBusInterface0_RegBank_4_20_1436 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49922,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_20_FFX_RST,
      O => PerLBusInterface0_RegBank_4_20
    );
  PerLBusInterface0_RegBank_4_20_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_20_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_20_FFX_RST
    );
  PerLBusInterface0_RegBank_4_2_1437 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_3_FFY_RST,
      O => PerLBusInterface0_RegBank_4_2
    );
  PerLBusInterface0_RegBank_4_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_3_FFY_RST
    );
  PerLBusInterface0_RegBank_20_10_1438 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_11_FFY_RST,
      O => PerLBusInterface0_RegBank_20_10
    );
  PerLBusInterface0_RegBank_20_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_11_FFY_RST
    );
  PerLBusInterface0_RegBank_1_9_1439 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_9_FFX_RST,
      O => PerLBusInterface0_RegBank_1_9
    );
  PerLBusInterface0_RegBank_1_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_9_FFX_RST
    );
  PerLBusInterface0_RegBank_20_0_1440 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_1_FFY_RST,
      O => PerLBusInterface0_RegBank_20_0
    );
  PerLBusInterface0_RegBank_20_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_1_FFY_RST
    );
  PerLBusInterface0_RegBank_20_1_1441 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_1_FFX_RST,
      O => PerLBusInterface0_RegBank_20_1
    );
  PerLBusInterface0_RegBank_20_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_1_FFX_RST
    );
  PerLBusInterface0_RegBank_20_11_1442 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_11_FFX_RST,
      O => PerLBusInterface0_RegBank_20_11
    );
  PerLBusInterface0_RegBank_20_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_11_FFX_RST
    );
  PerLBusInterface0_RegBank_20_12_1443 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_13_FFY_RST,
      O => PerLBusInterface0_RegBank_20_12
    );
  PerLBusInterface0_RegBank_20_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_13_FFY_RST
    );
  PerLBusInterface0_RegBank_20_13_1444 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_13_FFX_RST,
      O => PerLBusInterface0_RegBank_20_13
    );
  PerLBusInterface0_RegBank_20_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_13_FFX_RST
    );
  PerLBusInterface0_RegBank_20_14_1445 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_15_FFY_RST,
      O => PerLBusInterface0_RegBank_20_14
    );
  PerLBusInterface0_RegBank_20_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_15_FFY_RST
    );
  PerLBusInterface0_RegBank_20_15_1446 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_15_FFX_RST,
      O => PerLBusInterface0_RegBank_20_15
    );
  PerLBusInterface0_RegBank_20_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_15_FFX_RST
    );
  PerLBusInterface0_RegBank_20_16_1447 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49924,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_17_FFY_RST,
      O => PerLBusInterface0_RegBank_20_16
    );
  PerLBusInterface0_RegBank_20_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_17_FFY_RST
    );
  PerLBusInterface0_RegBank_20_17_1448 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49928,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_17_FFX_RST,
      O => PerLBusInterface0_RegBank_20_17
    );
  PerLBusInterface0_RegBank_20_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_17_FFX_RST
    );
  PerLBusInterface0_RegBank_20_18_1449 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49932,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_19_FFY_RST,
      O => PerLBusInterface0_RegBank_20_18
    );
  PerLBusInterface0_RegBank_20_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_19_FFY_RST
    );
  PerLBusInterface0_RegBank_20_20_1450 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49922,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_21_FFY_RST,
      O => PerLBusInterface0_RegBank_20_20
    );
  PerLBusInterface0_RegBank_20_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_21_FFY_RST
    );
  PerLBusInterface0_RegBank_20_19_1451 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49936,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_19_FFX_RST,
      O => PerLBusInterface0_RegBank_20_19
    );
  PerLBusInterface0_RegBank_20_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_19_FFX_RST
    );
  PerLBusInterface0_RegBank_16_2_1452 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0486,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_16_2_FFY_RST,
      O => PerLBusInterface0_RegBank_16_2
    );
  PerLBusInterface0_RegBank_16_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_16_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_16_2_FFY_RST
    );
  PerLBusInterface0_RegBank_15_9_1453 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0251(9),
      CE => PerLBusInterface0_n04841_1,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_15_9_FFX_RST,
      O => PerLBusInterface0_RegBank_15_9
    );
  PerLBusInterface0_RegBank_15_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_15_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_15_9_FFX_RST
    );
  PerLBusInterface0_RegBank_16_1_1454 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0486,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_16_1_FFX_RST,
      O => PerLBusInterface0_RegBank_16_1
    );
  PerLBusInterface0_RegBank_16_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_16_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_16_1_FFX_RST
    );
  PerLBusInterface0_RegBank_18_12_1455 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_13_FFY_RST,
      O => PerLBusInterface0_RegBank_18_12
    );
  PerLBusInterface0_RegBank_18_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_13_FFY_RST
    );
  PerLBusInterface0_RegBank_18_10_1456 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_11_FFY_RST,
      O => PerLBusInterface0_RegBank_18_10
    );
  PerLBusInterface0_RegBank_18_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_11_FFY_RST
    );
  PerLBusInterface0_RegBank_18_11_1457 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_11_FFX_RST,
      O => PerLBusInterface0_RegBank_18_11
    );
  PerLBusInterface0_RegBank_18_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_11_FFX_RST
    );
  PerLBusInterface0_RegBank_18_13_1458 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_13_FFX_RST,
      O => PerLBusInterface0_RegBank_18_13
    );
  PerLBusInterface0_RegBank_18_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_13_FFX_RST
    );
  PerLBusInterface0_RegBank_18_14_1459 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_15_FFY_RST,
      O => PerLBusInterface0_RegBank_18_14
    );
  PerLBusInterface0_RegBank_18_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_15_FFY_RST
    );
  PerLBusInterface0_RegBank_18_15_1460 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49920,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_15_FFX_RST,
      O => PerLBusInterface0_RegBank_18_15
    );
  PerLBusInterface0_RegBank_18_15_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_15_FFX_RST
    );
  PerLBusInterface0_RegBank_18_16_1461 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49924,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_17_FFY_RST,
      O => PerLBusInterface0_RegBank_18_16
    );
  PerLBusInterface0_RegBank_18_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_17_FFY_RST
    );
  PerLBusInterface0_RegBank_18_29_1462 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49952,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_29_FFX_RST,
      O => PerLBusInterface0_RegBank_18_29
    );
  PerLBusInterface0_RegBank_18_29_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_29_FFX_RST
    );
  PerLBusInterface0_RegBank_18_2_1463 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_3_FFY_RST,
      O => PerLBusInterface0_RegBank_18_2
    );
  PerLBusInterface0_RegBank_18_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_3_FFY_RST
    );
  PerLBusInterface0_RegBank_18_3_1464 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_3_FFX_RST,
      O => PerLBusInterface0_RegBank_18_3
    );
  PerLBusInterface0_RegBank_18_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_3_FFX_RST
    );
  PerLBusInterface0_RegBank_18_30_1465 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49942,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_31_FFY_RST,
      O => PerLBusInterface0_RegBank_18_30
    );
  PerLBusInterface0_RegBank_18_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_31_FFY_RST
    );
  PerLBusInterface0_RegBank_18_31_1466 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49946,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_31_FFX_RST,
      O => PerLBusInterface0_RegBank_18_31
    );
  PerLBusInterface0_RegBank_18_31_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_31_FFX_RST
    );
  PerLBusInterface0_RegBank_18_4_1467 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_5_FFY_RST,
      O => PerLBusInterface0_RegBank_18_4
    );
  PerLBusInterface0_RegBank_18_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_5_FFY_RST
    );
  PerLBusInterface0_RegBank_18_5_1468 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_5_FFX_RST,
      O => PerLBusInterface0_RegBank_18_5
    );
  PerLBusInterface0_RegBank_18_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_5_FFX_RST
    );
  PerLBusInterface0_RegBank_18_6_1469 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_7_FFY_RST,
      O => PerLBusInterface0_RegBank_18_6
    );
  PerLBusInterface0_RegBank_18_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_7_FFY_RST
    );
  PerLBusInterface0_RegBank_18_7_1470 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_7_FFX_RST,
      O => PerLBusInterface0_RegBank_18_7
    );
  PerLBusInterface0_RegBank_18_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_7_FFX_RST
    );
  PerLBusInterface0_RegBank_18_8_1471 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_9_FFY_RST,
      O => PerLBusInterface0_RegBank_18_8
    );
  PerLBusInterface0_RegBank_18_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_9_FFY_RST
    );
  PerLBusInterface0_RegBank_1_10_1472 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_11_FFY_RST,
      O => PerLBusInterface0_RegBank_1_10
    );
  PerLBusInterface0_RegBank_1_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_11_FFY_RST
    );
  PerLBusInterface0_RegBank_18_9_1473 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_9_FFX_RST,
      O => PerLBusInterface0_RegBank_18_9
    );
  PerLBusInterface0_RegBank_18_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_9_FFX_RST
    );
  PerLBusInterface0_RegBank_1_0_1474 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_1_1_FFY_RST,
      O => PerLBusInterface0_RegBank_1_0
    );
  PerLBusInterface0_RegBank_1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_1_1_FFY_RST
    );
  PerLBusInterface0_RegBank_5_3_1475 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_3_FFX_RST,
      O => PerLBusInterface0_RegBank_5_3
    );
  PerLBusInterface0_RegBank_5_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_3_FFX_RST
    );
  PerLBusInterface0_RegBank_5_5_1476 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_5_FFX_RST,
      O => PerLBusInterface0_RegBank_5_5
    );
  PerLBusInterface0_RegBank_5_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_5_FFX_RST
    );
  PerLBusInterface0_RegBank_5_6_1477 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_8_FFY_RST,
      O => PerLBusInterface0_RegBank_5_6
    );
  PerLBusInterface0_RegBank_5_8_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_8_FFY_RST
    );
  PerLBusInterface0_RegBank_5_8_1478 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_8_FFX_RST,
      O => PerLBusInterface0_RegBank_5_8
    );
  PerLBusInterface0_RegBank_5_8_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_8_FFX_RST
    );
  PerLBusInterface0_RegBank_63_12_1479 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_RegBank_63_12_LOGIC_ZERO,
      CE => PerLBusInterface0_n0496,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_63_12_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_63_12
    );
  PerLBusInterface0_RegBank_63_12_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_63_12_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_63_12_FFY_SET
    );
  PerLBusInterface0_RegBank_6_0_1480 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_1_FFY_RST,
      O => PerLBusInterface0_RegBank_6_0
    );
  PerLBusInterface0_RegBank_6_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_1_FFY_RST
    );
  PerLBusInterface0_RegBank_6_10_1481 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_11_FFY_RST,
      O => PerLBusInterface0_RegBank_6_10
    );
  PerLBusInterface0_RegBank_6_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_11_FFY_RST
    );
  PerLBusInterface0_RegBank_6_1_1482 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_1_FFX_RST,
      O => PerLBusInterface0_RegBank_6_1
    );
  PerLBusInterface0_RegBank_6_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_1_FFX_RST
    );
  PerLBusInterface0_RegBank_18_17_1483 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49928,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_17_FFX_RST,
      O => PerLBusInterface0_RegBank_18_17
    );
  PerLBusInterface0_RegBank_18_17_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_17_FFX_RST
    );
  PerLBusInterface0_RegBank_18_18_1484 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49932,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_19_FFY_RST,
      O => PerLBusInterface0_RegBank_18_18
    );
  PerLBusInterface0_RegBank_18_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_19_FFY_RST
    );
  PerLBusInterface0_RegBank_18_19_1485 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49936,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_19_FFX_RST,
      O => PerLBusInterface0_RegBank_18_19
    );
  PerLBusInterface0_RegBank_18_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_19_FFX_RST
    );
  PerLBusInterface0_RegBank_18_20_1486 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49922,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_21_FFY_RST,
      O => PerLBusInterface0_RegBank_18_20
    );
  PerLBusInterface0_RegBank_18_21_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_21_FFY_RST
    );
  PerLBusInterface0_RegBank_18_21_1487 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49926,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_21_FFX_RST,
      O => PerLBusInterface0_RegBank_18_21
    );
  PerLBusInterface0_RegBank_18_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_21_FFX_RST
    );
  PerLBusInterface0_RegBank_18_22_1488 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49930,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_23_FFY_RST,
      O => PerLBusInterface0_RegBank_18_22
    );
  PerLBusInterface0_RegBank_18_23_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_23_FFY_RST
    );
  PerLBusInterface0_RegBank_18_23_1489 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49934,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_23_FFX_RST,
      O => PerLBusInterface0_RegBank_18_23
    );
  PerLBusInterface0_RegBank_18_23_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_23_FFX_RST
    );
  PerLBusInterface0_RegBank_18_24_1490 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49938,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_25_FFY_RST,
      O => PerLBusInterface0_RegBank_18_24
    );
  PerLBusInterface0_RegBank_18_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_25_FFY_RST
    );
  PerLBusInterface0_RegBank_18_25_1491 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49940,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_25_FFX_RST,
      O => PerLBusInterface0_RegBank_18_25
    );
  PerLBusInterface0_RegBank_18_25_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_25_FFX_RST
    );
  PerLBusInterface0_RegBank_18_26_1492 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49944,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_27_FFY_RST,
      O => PerLBusInterface0_RegBank_18_26
    );
  PerLBusInterface0_RegBank_18_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_27_FFY_RST
    );
  PerLBusInterface0_RegBank_18_28_1493 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49950,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_29_FFY_RST,
      O => PerLBusInterface0_RegBank_18_28
    );
  PerLBusInterface0_RegBank_18_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_29_FFY_RST
    );
  PerLBusInterface0_RegBank_18_27_1494 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49948,
      CE => PerLBusInterface0_n0492,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_18_27_FFX_RST,
      O => PerLBusInterface0_RegBank_18_27
    );
  PerLBusInterface0_RegBank_18_27_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_18_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_18_27_FFX_RST
    );
  PerLBusInterface0_RegBank_20_5_1495 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_5_FFX_RST,
      O => PerLBusInterface0_RegBank_20_5
    );
  PerLBusInterface0_RegBank_20_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_5_FFX_RST
    );
  PerLBusInterface0_RegBank_20_6_1496 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_7_FFY_RST,
      O => PerLBusInterface0_RegBank_20_6
    );
  PerLBusInterface0_RegBank_20_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_7_FFY_RST
    );
  PerLBusInterface0_RegBank_20_7_1497 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_7_FFX_RST,
      O => PerLBusInterface0_RegBank_20_7
    );
  PerLBusInterface0_RegBank_20_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_7_FFX_RST
    );
  PerLBusInterface0_RegBank_20_8_1498 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_9_FFY_RST,
      O => PerLBusInterface0_RegBank_20_8
    );
  PerLBusInterface0_RegBank_20_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_9_FFY_RST
    );
  PerLBusInterface0_RegBank_3_10_1499 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_11_FFY_RST,
      O => PerLBusInterface0_RegBank_3_10
    );
  PerLBusInterface0_RegBank_3_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_11_FFY_RST
    );
  PerLBusInterface0_RegBank_20_9_1500 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_9_FFX_RST,
      O => PerLBusInterface0_RegBank_20_9
    );
  PerLBusInterface0_RegBank_20_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_9_FFX_RST
    );
  PerLBusInterface0_RegBank_3_0_1501 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_1_FFY_RST,
      O => PerLBusInterface0_RegBank_3_0
    );
  PerLBusInterface0_RegBank_3_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_1_FFY_RST
    );
  PerLBusInterface0_RegBank_3_1_1502 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_1_FFX_RST,
      O => PerLBusInterface0_RegBank_3_1
    );
  PerLBusInterface0_RegBank_3_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_1_FFX_RST
    );
  PerLBusInterface0_RegBank_3_12_1503 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_13_FFY_RST,
      O => PerLBusInterface0_RegBank_3_12
    );
  PerLBusInterface0_RegBank_3_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_13_FFY_RST
    );
  PerLBusInterface0_RegBank_4_3_1504 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_3_FFX_RST,
      O => PerLBusInterface0_RegBank_4_3
    );
  PerLBusInterface0_RegBank_4_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_3_FFX_RST
    );
  PerLBusInterface0_RegBank_4_5_1505 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_5_FFX_RST,
      O => PerLBusInterface0_RegBank_4_5
    );
  PerLBusInterface0_RegBank_4_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_5_FFX_RST
    );
  PerLBusInterface0_RegBank_4_6_1506 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_4_7_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_4_6
    );
  PerLBusInterface0_RegBank_4_7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_4_7_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_4_7_FFY_SET
    );
  PerLBusInterface0_RegBank_4_7_1507 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_7_FFX_RST,
      O => PerLBusInterface0_RegBank_4_7
    );
  PerLBusInterface0_RegBank_4_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_7_FFX_RST
    );
  PerLBusInterface0_RegBank_4_8_1508 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_4_9_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_4_8
    );
  PerLBusInterface0_RegBank_4_9_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_4_9_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_4_9_FFY_SET
    );
  PerLBusInterface0_RegBank_5_9_1509 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_10_FFY_RST,
      O => PerLBusInterface0_RegBank_5_9
    );
  PerLBusInterface0_RegBank_5_10_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_10_FFY_RST
    );
  PerLBusInterface0_RegBank_4_9_1510 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_4_9_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_4_9
    );
  PerLBusInterface0_RegBank_4_9_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_4_9_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_4_9_FFX_SET
    );
  PerLBusInterface0_RegBank_5_0_1511 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_1_FFY_RST,
      O => PerLBusInterface0_RegBank_5_0
    );
  PerLBusInterface0_RegBank_5_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_1_FFY_RST
    );
  PerLBusInterface0_RegBank_5_1_1512 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_1_FFX_RST,
      O => PerLBusInterface0_RegBank_5_1
    );
  PerLBusInterface0_RegBank_5_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_1_FFX_RST
    );
  PerLBusInterface0_RegBank_5_10_1513 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_10_FFX_RST,
      O => PerLBusInterface0_RegBank_5_10
    );
  PerLBusInterface0_RegBank_5_10_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_10_FFX_RST
    );
  PerLBusInterface0_RegBank_5_11_1514 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_11_FFY_RST,
      O => PerLBusInterface0_RegBank_5_11
    );
  PerLBusInterface0_RegBank_5_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_11_FFY_RST
    );
  PerLBusInterface0_RegBank_5_4_1515 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_5_FFY_RST,
      O => PerLBusInterface0_RegBank_5_4
    );
  PerLBusInterface0_RegBank_5_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_5_FFY_RST
    );
  PerLBusInterface0_RegBank_5_2_1516 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0473,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_5_3_FFY_RST,
      O => PerLBusInterface0_RegBank_5_2
    );
  PerLBusInterface0_RegBank_5_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_5_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_5_3_FFY_RST
    );
  PerLBusInterface0_RegBank_20_21_1517 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49926,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_21_FFX_RST,
      O => PerLBusInterface0_RegBank_20_21
    );
  PerLBusInterface0_RegBank_20_21_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_21_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_21_FFX_RST
    );
  PerLBusInterface0_RegBank_20_22_1518 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49930,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_23_FFY_RST,
      O => PerLBusInterface0_RegBank_20_22
    );
  PerLBusInterface0_RegBank_20_23_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_23_FFY_RST
    );
  PerLBusInterface0_RegBank_20_23_1519 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49934,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_23_FFX_RST,
      O => PerLBusInterface0_RegBank_20_23
    );
  PerLBusInterface0_RegBank_20_23_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_23_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_23_FFX_RST
    );
  PerLBusInterface0_RegBank_20_24_1520 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49938,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_25_FFY_RST,
      O => PerLBusInterface0_RegBank_20_24
    );
  PerLBusInterface0_RegBank_20_25_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_25_FFY_RST
    );
  PerLBusInterface0_RegBank_20_25_1521 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49940,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_25_FFX_RST,
      O => PerLBusInterface0_RegBank_20_25
    );
  PerLBusInterface0_RegBank_20_25_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_25_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_25_FFX_RST
    );
  PerLBusInterface0_RegBank_20_26_1522 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49944,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_27_FFY_RST,
      O => PerLBusInterface0_RegBank_20_26
    );
  PerLBusInterface0_RegBank_20_27_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_27_FFY_RST
    );
  PerLBusInterface0_RegBank_20_27_1523 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49948,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_27_FFX_RST,
      O => PerLBusInterface0_RegBank_20_27
    );
  PerLBusInterface0_RegBank_20_27_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_27_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_27_FFX_RST
    );
  PerLBusInterface0_RegBank_20_28_1524 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49950,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_29_FFY_RST,
      O => PerLBusInterface0_RegBank_20_28
    );
  PerLBusInterface0_RegBank_20_29_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_29_FFY_RST
    );
  PerLBusInterface0_RegBank_20_29_1525 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49952,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_29_FFX_RST,
      O => PerLBusInterface0_RegBank_20_29
    );
  PerLBusInterface0_RegBank_20_29_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_29_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_29_FFX_RST
    );
  PerLBusInterface0_RegBank_20_2_1526 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_3_FFY_RST,
      O => PerLBusInterface0_RegBank_20_2
    );
  PerLBusInterface0_RegBank_20_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_3_FFY_RST
    );
  PerLBusInterface0_RegBank_20_3_1527 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_3_FFX_RST,
      O => PerLBusInterface0_RegBank_20_3
    );
  PerLBusInterface0_RegBank_20_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_3_FFX_RST
    );
  PerLBusInterface0_RegBank_20_30_1528 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49942,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_31_FFY_RST,
      O => PerLBusInterface0_RegBank_20_30
    );
  PerLBusInterface0_RegBank_20_31_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_31_FFY_RST
    );
  PerLBusInterface0_RegBank_20_4_1529 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_5_FFY_RST,
      O => PerLBusInterface0_RegBank_20_4
    );
  PerLBusInterface0_RegBank_20_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_5_FFY_RST
    );
  PerLBusInterface0_RegBank_20_31_1530 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49946,
      CE => PerLBusInterface0_n0237,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_20_31_FFX_RST,
      O => PerLBusInterface0_RegBank_20_31
    );
  PerLBusInterface0_RegBank_20_31_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_20_31_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_20_31_FFX_RST
    );
  PerLBusInterface0_RegBank_3_11_1531 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_11_FFX_RST,
      O => PerLBusInterface0_RegBank_3_11
    );
  PerLBusInterface0_RegBank_3_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_11_FFX_RST
    );
  PerLBusInterface0_RegBank_3_13_1532 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_13_FFX_RST,
      O => PerLBusInterface0_RegBank_3_13
    );
  PerLBusInterface0_RegBank_3_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_13_FFX_RST
    );
  PerLBusInterface0_RegBank_3_2_1533 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_3_FFY_RST,
      O => PerLBusInterface0_RegBank_3_2
    );
  PerLBusInterface0_RegBank_3_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_3_FFY_RST
    );
  PerLBusInterface0_RegBank_3_3_1534 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_3_FFX_RST,
      O => PerLBusInterface0_RegBank_3_3
    );
  PerLBusInterface0_RegBank_3_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_3_FFX_RST
    );
  PerLBusInterface0_RegBank_3_4_1535 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_5_FFY_RST,
      O => PerLBusInterface0_RegBank_3_4
    );
  PerLBusInterface0_RegBank_3_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_5_FFY_RST
    );
  PerLBusInterface0_RegBank_3_5_1536 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_5_FFX_RST,
      O => PerLBusInterface0_RegBank_3_5
    );
  PerLBusInterface0_RegBank_3_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_5_FFX_RST
    );
  PerLBusInterface0_RegBank_3_6_1537 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_7_FFY_RST,
      O => PerLBusInterface0_RegBank_3_6
    );
  PerLBusInterface0_RegBank_3_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_7_FFY_RST
    );
  PerLBusInterface0_RegBank_3_7_1538 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_7_FFX_RST,
      O => PerLBusInterface0_RegBank_3_7
    );
  PerLBusInterface0_RegBank_3_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_7_FFX_RST
    );
  PerLBusInterface0_RegBank_3_8_1539 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_9_FFY_RST,
      O => PerLBusInterface0_RegBank_3_8
    );
  PerLBusInterface0_RegBank_3_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_9_FFY_RST
    );
  PerLBusInterface0_RegBank_4_10_1540 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49910,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_11_FFY_RST,
      O => PerLBusInterface0_RegBank_4_10
    );
  PerLBusInterface0_RegBank_4_11_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_11_FFY_RST
    );
  PerLBusInterface0_RegBank_3_9_1541 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0467,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_3_9_FFX_RST,
      O => PerLBusInterface0_RegBank_3_9
    );
  PerLBusInterface0_RegBank_3_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_3_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_3_9_FFX_RST
    );
  PerLBusInterface0_RegBank_4_0_1542 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_1_FFY_RST,
      O => PerLBusInterface0_RegBank_4_0
    );
  PerLBusInterface0_RegBank_4_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_1_FFY_RST
    );
  PerLBusInterface0_RegBank_4_1_1543 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49970,
      CE => PerLBusInterface0_n0470,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_4_1_FFX_RST,
      O => PerLBusInterface0_RegBank_4_1
    );
  PerLBusInterface0_RegBank_4_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_4_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_4_1_FFX_RST
    );
  PerLBusInterface0_RegBank_6_11_1544 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49912,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_11_FFX_RST,
      O => PerLBusInterface0_RegBank_6_11
    );
  PerLBusInterface0_RegBank_6_11_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_11_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_11_FFX_RST
    );
  PerLBusInterface0_RegBank_6_12_1545 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49914,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_13_FFY_RST,
      O => PerLBusInterface0_RegBank_6_12
    );
  PerLBusInterface0_RegBank_6_13_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_13_FFY_RST
    );
  PerLBusInterface0_RegBank_6_13_1546 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49916,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_13_FFX_RST,
      O => PerLBusInterface0_RegBank_6_13
    );
  PerLBusInterface0_RegBank_6_13_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_13_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_13_FFX_RST
    );
  PerLBusInterface0_RegBank_6_14_1547 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49918,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_14_FFY_RST,
      O => PerLBusInterface0_RegBank_6_14
    );
  PerLBusInterface0_RegBank_6_14_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_14_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_14_FFY_RST
    );
  PerLBusInterface0_RegBank_6_2_1548 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49976,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_3_FFY_RST,
      O => PerLBusInterface0_RegBank_6_2
    );
  PerLBusInterface0_RegBank_6_3_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_3_FFY_RST
    );
  PerLBusInterface0_RegBank_6_3_1549 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_3_FFX_RST,
      O => PerLBusInterface0_RegBank_6_3
    );
  PerLBusInterface0_RegBank_6_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_3_FFX_RST
    );
  PerLBusInterface0_RegBank_6_4_1550 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49988,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_5_FFY_RST,
      O => PerLBusInterface0_RegBank_6_4
    );
  PerLBusInterface0_RegBank_6_5_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_5_FFY_RST
    );
  PerLBusInterface0_RegBank_6_5_1551 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_5_FFX_RST,
      O => PerLBusInterface0_RegBank_6_5
    );
  PerLBusInterface0_RegBank_6_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_5_FFX_RST
    );
  PerLBusInterface0_RegBank_6_6_1552 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_7_FFY_RST,
      O => PerLBusInterface0_RegBank_6_6
    );
  PerLBusInterface0_RegBank_6_7_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_7_FFY_RST
    );
  PerLBusInterface0_RegBank_6_7_1553 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_7_FFX_RST,
      O => PerLBusInterface0_RegBank_6_7
    );
  PerLBusInterface0_RegBank_6_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_7_FFX_RST
    );
  PerLBusInterface0_RegBank_6_8_1554 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_9_FFY_RST,
      O => PerLBusInterface0_RegBank_6_8
    );
  PerLBusInterface0_RegBank_6_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_9_FFY_RST
    );
  PerLBusInterface0_RegBank_6_9_1555 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0476,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_6_9_FFX_RST,
      O => PerLBusInterface0_RegBank_6_9
    );
  PerLBusInterface0_RegBank_6_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_6_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_6_9_FFX_RST
    );
  PerLBusInterface0_RegBank_7_0_1556 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49964,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_1_FFY_RST,
      O => PerLBusInterface0_RegBank_7_0
    );
  PerLBusInterface0_RegBank_7_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_1_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_17 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0320,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_17_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_17_Q
    );
  PerLBusInterface0_RegWriteEn_17_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_17_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_17_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_18 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0319,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_19_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_18_Q
    );
  PerLBusInterface0_RegWriteEn_19_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_19_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_19 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0318,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_19_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_19_Q
    );
  PerLBusInterface0_RegWriteEn_19_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_19_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_19_FFX_RST
    );
  PerLBusInterface0_RegWriteEn_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0333,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_1_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_0_Q
    );
  PerLBusInterface0_RegWriteEn_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_1_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0332,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_1_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_1_Q
    );
  PerLBusInterface0_RegWriteEn_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_1_FFX_RST
    );
  PerLBusInterface0_RegWriteEn_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0331,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_4_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_3_Q
    );
  PerLBusInterface0_RegWriteEn_4_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_4_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_5 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0329,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_6_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_5_Q
    );
  PerLBusInterface0_RegWriteEn_6_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_6_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_4 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0330,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_4_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_4_Q
    );
  PerLBusInterface0_RegWriteEn_4_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_4_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_4_FFX_RST
    );
  TriggerDelay0_DelayCount_0_64_1557 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_135,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_64_FFX_RST,
      O => TriggerDelay0_DelayCount_0_64
    );
  TriggerDelay0_DelayCount_0_64_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_64_FFX_RST
    );
  TriggerDelay0_DelayCount_0_67_1558 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_138,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_66_FFY_RST,
      O => TriggerDelay0_DelayCount_0_67
    );
  TriggerDelay0_DelayCount_0_66_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_66_FFY_RST
    );
  TriggerDelay0_DelayCount_0_66_1559 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_137,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_66_FFX_RST,
      O => TriggerDelay0_DelayCount_0_66
    );
  TriggerDelay0_DelayCount_0_66_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_66_FFX_RST
    );
  TriggerDelay0_DelayCount_0_69_1560 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_140,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_68_FFY_RST,
      O => TriggerDelay0_DelayCount_0_69
    );
  TriggerDelay0_DelayCount_0_68_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_68_FFY_RST
    );
  TriggerDelay0_DelayCount_0_68_1561 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_139,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_68_FFX_RST,
      O => TriggerDelay0_DelayCount_0_68
    );
  TriggerDelay0_DelayCount_0_68_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_68_FFX_RST
    );
  TriggerDelay0_DelayCount_0_71_1562 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_142,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_70_FFY_RST,
      O => TriggerDelay0_DelayCount_0_71
    );
  TriggerDelay0_DelayCount_0_70_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_70_FFY_RST
    );
  PerLBusInterface0_RegBank_7_3_1563 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49982,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_3_FFX_RST,
      O => PerLBusInterface0_RegBank_7_3
    );
  PerLBusInterface0_RegBank_7_3_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_3_FFX_RST
    );
  PerLBusInterface0_RegBank_7_5_1564 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49994,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_5_FFX_RST,
      O => PerLBusInterface0_RegBank_7_5
    );
  PerLBusInterface0_RegBank_7_5_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_5_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_5_FFX_RST
    );
  PerLBusInterface0_RegBank_7_6_1565 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => N50002,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => PerLBusInterface0_RegBank_7_7_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_7_6
    );
  PerLBusInterface0_RegBank_7_7_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_RegBank_7_7_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_RegBank_7_7_FFY_SET
    );
  PerLBusInterface0_RegBank_7_8_1566 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49892,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_9_FFY_RST,
      O => PerLBusInterface0_RegBank_7_8
    );
  PerLBusInterface0_RegBank_7_9_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_9_FFY_RST
    );
  PerLBusInterface0_RegBank_7_7_1567 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49886,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_7_FFX_RST,
      O => PerLBusInterface0_RegBank_7_7
    );
  PerLBusInterface0_RegBank_7_7_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_7_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_7_FFX_RST
    );
  PerLBusInterface0_RegBank_7_9_1568 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => N49898,
      CE => PerLBusInterface0_n0479,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegBank_7_9_FFX_RST,
      O => PerLBusInterface0_RegBank_7_9
    );
  PerLBusInterface0_RegBank_7_9_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegBank_7_9_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegBank_7_9_FFX_RST
    );
  PerLBusInterface0_RegWriteEn_9 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0325,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_10_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_9_Q
    );
  PerLBusInterface0_RegWriteEn_10_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_10_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_15 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0322,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_15_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_15_Q
    );
  PerLBusInterface0_RegWriteEn_15_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_15_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_15_FFY_RST
    );
  PerLBusInterface0_RegWriteEn_10 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0324,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_10_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_10_Q
    );
  PerLBusInterface0_RegWriteEn_10_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_10_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_10_FFX_RST
    );
  PerLBusInterface0_RegWriteEn_6 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0328,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_6_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_6_Q
    );
  PerLBusInterface0_RegWriteEn_6_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_6_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_6_FFX_RST
    );
  PerLBusInterface0_RegWriteEn_7 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0327,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_8_FFY_RST,
      O => PerLBusInterface0_RegWriteEn_7_Q
    );
  PerLBusInterface0_RegWriteEn_8_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_8_FFY_RST
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_0 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_StrobeExtender0_FeedbackBit,
      CE => PerLBusInterface0_StrobeExtender0_n0007,
      CLK => LCLK,
      SET => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR(0)
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFY_SET
    );
  PerLBusInterface0_RegWriteEn_8 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0326,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_RegWriteEn_8_FFX_RST,
      O => PerLBusInterface0_RegWriteEn_8_Q
    );
  PerLBusInterface0_RegWriteEn_8_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_RegWriteEn_8_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_RegWriteEn_8_FFX_RST
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_1 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_StrobeExtender0_CountLFSR(0),
      CE => PerLBusInterface0_StrobeExtender0_n0007,
      CLK => LCLK,
      SET => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFX_SET,
      RST => GND,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR(1)
    );
  PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFX_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_StrobeExtender0_CountLFSR_1_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_StrobeExtender0_CountLFSR_1_FFX_SET
    );
  PerLBusInterface0_StrobeExtender0_pStrobeOut_1569 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_ForceBScan,
      CE => PerLBusInterface0_StrobeExtender0_n0013,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_StrobeExtender0_pStrobeOut_FFY_RST,
      O => PerLBusInterface0_StrobeExtender0_pStrobeOut
    );
  PerLBusInterface0_StrobeExtender0_pStrobeOut_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_StrobeExtender0_pStrobeOut_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_StrobeExtender0_pStrobeOut_FFY_RST
    );
  PerLBusInterface0_pCalDac_nCS_1570 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_n0279,
      CE => PerLBusInterface0_CalClkEn1,
      CLK => LCLK,
      SET => PerLBusInterface0_pCalDac_nCS_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_pCalDac_nCS
    );
  PerLBusInterface0_pCalDac_nCS_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_pCalDac_nCS_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_pCalDac_nCS_FFY_SET
    );
  PerLBusInterface0_pCalDac_nLD_1571 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_n0278,
      CE => PerLBusInterface0_CalClkEn1,
      CLK => LCLK,
      SET => PerLBusInterface0_pCalDac_nLD_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_pCalDac_nLD
    );
  PerLBusInterface0_pCalDac_nLD_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_pCalDac_nLD_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_pCalDac_nLD_FFY_SET
    );
  PerLBusInterface0_pEncoderReset_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0343,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pEncoderReset_1_FFY_RST,
      O => PerLBusInterface0_pEncoderReset(0)
    );
  PerLBusInterface0_pEncoderReset_1_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_pEncoderReset_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_pEncoderReset_1_FFY_RST
    );
  PerLBusInterface0_pEncoderReset_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0342,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pEncoderReset_1_FFX_RST,
      O => PerLBusInterface0_pEncoderReset(1)
    );
  PerLBusInterface0_pEncoderReset_1_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_pEncoderReset_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_pEncoderReset_1_FFX_RST
    );
  PerLBusInterface0_pEncoderReset_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_n0341,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pEncoderReset_2_FFY_RST,
      O => PerLBusInterface0_pEncoderReset(2)
    );
  PerLBusInterface0_pEncoderReset_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_pEncoderReset_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_pEncoderReset_2_FFY_RST
    );
  PerLBusInterface0_pGateDataEn_1572 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_GateDataOut_1,
      CE => pnLReset_IBUF,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pGateDataEn_FFY_RST,
      O => PerLBusInterface0_pGateDataEn
    );
  PerLBusInterface0_pGateDataEn_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_pGateDataEn_FFY_RST
    );
  PerLBusInterface0_pGateDataOut_1573 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_RegBank_14_31,
      CE => pnLReset_IBUF,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pGateDataOut_FFY_RST,
      O => PerLBusInterface0_pGateDataOut
    );
  PerLBusInterface0_pGateDataOut_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_pGateDataOut_FFY_RST
    );
  TriggerDelay0_DelayCount_1_64_1574 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_135,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_64_FFX_RST,
      O => TriggerDelay0_DelayCount_1_64
    );
  TriggerDelay0_DelayCount_1_64_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_64_FFX_RST
    );
  TriggerDelay0_DelayCount_1_66_1575 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_137,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_66_FFX_RST,
      O => TriggerDelay0_DelayCount_1_66
    );
  TriggerDelay0_DelayCount_1_66_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_66_FFX_RST
    );
  TriggerDelay0_DelayCount_1_69_1576 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_140,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_68_FFY_RST,
      O => TriggerDelay0_DelayCount_1_69
    );
  TriggerDelay0_DelayCount_1_68_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_68_FFY_RST
    );
  TriggerDelay0_DelayCount_1_68_1577 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_139,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_68_FFX_RST,
      O => TriggerDelay0_DelayCount_1_68
    );
  TriggerDelay0_DelayCount_1_68_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_68_FFX_RST
    );
  TriggerDelay0_DelayCount_1_71_1578 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_142,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_70_FFY_RST,
      O => TriggerDelay0_DelayCount_1_71
    );
  TriggerDelay0_DelayCount_1_70_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_70_FFY_RST
    );
  TriggerDelay0_DelayCount_1_61_1579 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_132,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_60_FFY_RST,
      O => TriggerDelay0_DelayCount_1_61
    );
  TriggerDelay0_DelayCount_1_60_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_60_FFY_RST
    );
  TriggerDelay0_DelayCount_0_72_1580 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_143,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_72_FFX_RST,
      O => TriggerDelay0_DelayCount_0_72
    );
  TriggerDelay0_DelayCount_0_72_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_72_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_72_FFX_RST
    );
  TriggerDelay0_DelayCount_0_70_1581 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_141,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_70_FFX_RST,
      O => TriggerDelay0_DelayCount_0_70
    );
  TriggerDelay0_DelayCount_0_70_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_70_FFX_RST
    );
  TriggerDelay0_DelayCount_1_57_1582 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_128,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_57_FFY_RST,
      O => TriggerDelay0_DelayCount_1_57
    );
  TriggerDelay0_DelayCount_1_57_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_57_FFY_RST
    );
  TriggerDelay0_DelayCount_1_59_1583 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_130,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_58_FFY_RST,
      O => TriggerDelay0_DelayCount_1_59
    );
  TriggerDelay0_DelayCount_1_58_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_58_FFY_RST
    );
  PerLBusInterface0_pGateDataSel_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_RegBank_16_0,
      CE => pnLReset_IBUF,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pGateDataSel_1_FFY_RST,
      O => PerLBusInterface0_pGateDataSel(0)
    );
  PerLBusInterface0_pGateDataSel_1_FFY_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_pGateDataSel_1_FFY_RST
    );
  PerLBusInterface0_pGateDataSel_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_RegBank_16_1,
      CE => pnLReset_IBUF,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_pGateDataSel_1_FFX_RST,
      O => PerLBusInterface0_pGateDataSel(1)
    );
  PerLBusInterface0_pGateDataSel_1_FFX_RSTOR : X_BUF
    port map (
      I => GSR,
      O => PerLBusInterface0_pGateDataSel_1_FFX_RST
    );
  PerLBusInterface0_vCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_vCount_n0000(1),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_vCount_0_FFY_RST,
      O => PerLBusInterface0_vCount(1)
    );
  PerLBusInterface0_vCount_0_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_vCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_vCount_0_FFY_RST
    );
  PerLBusInterface0_vCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_vCount_0_BXMUXNOT,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_vCount_0_FFX_RST,
      O => PerLBusInterface0_vCount(0)
    );
  PerLBusInterface0_vCount_0_FFX_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_vCount_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_vCount_0_FFX_RST
    );
  PerLBusInterface0_vCount_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_vCount_n0000(2),
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_vCount_2_FFY_RST,
      O => PerLBusInterface0_vCount(2)
    );
  PerLBusInterface0_vCount_2_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_vCount_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_vCount_2_FFY_RST
    );
  PerLBusInterface0_vIncAddr_1584 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => PerLBusInterface0_vIncAddr_GROM,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => PerLBusInterface0_vIncAddr_FFY_RST,
      O => PerLBusInterface0_vIncAddr
    );
  PerLBusInterface0_vIncAddr_FFY_RSTOR : X_OR2
    port map (
      I0 => PerLBusInterface0_vIncAddr_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => PerLBusInterface0_vIncAddr_FFY_RST
    );
  TriggerDelay0_ActiveCount_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_ActiveCount_1_BYMUXNOT,
      CE => TriggerDelay0_n0021,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_ActiveCount_1_FFY_RST,
      O => TriggerDelay0_ActiveCount(0)
    );
  TriggerDelay0_ActiveCount_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_ActiveCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_ActiveCount_1_FFY_RST
    );
  TriggerDelay0_DelayActive_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayActive_0_GROM,
      CE => TriggerDelay0_n0084,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayActive_0_FFY_RST,
      O => TriggerDelay0_DelayActive(0)
    );
  TriggerDelay0_DelayActive_0_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayActive_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayActive_0_FFY_RST
    );
  TriggerDelay0_ActiveCount_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_ActiveCount_n0000(1),
      CE => TriggerDelay0_n0021,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_ActiveCount_1_FFX_RST,
      O => TriggerDelay0_ActiveCount(1)
    );
  TriggerDelay0_ActiveCount_1_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_ActiveCount_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_ActiveCount_1_FFX_RST
    );
  TriggerDelay0_DelayActive_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayActive_2_GROM,
      CE => TriggerDelay0_n0080,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayActive_2_FFY_RST,
      O => TriggerDelay0_DelayActive(2)
    );
  TriggerDelay0_DelayActive_2_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayActive_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayActive_2_FFY_RST
    );
  TriggerDelay0_DelayActive_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayActive_3_GROM,
      CE => TriggerDelay0_n0078,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayActive_3_FFY_RST,
      O => TriggerDelay0_DelayActive(3)
    );
  TriggerDelay0_DelayActive_3_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayActive_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayActive_3_FFY_RST
    );
  TriggerDelay0_DelayCount_0_57_1585 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_128,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_57_FFY_RST,
      O => TriggerDelay0_DelayCount_0_57
    );
  TriggerDelay0_DelayCount_0_57_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_57_FFY_RST
    );
  TriggerDelay0_DelayCount_0_59_1586 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_130,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_58_FFY_RST,
      O => TriggerDelay0_DelayCount_0_59
    );
  TriggerDelay0_DelayCount_0_58_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_58_FFY_RST
    );
  PerLBusInterface0_pCalDac_CLK_1587 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => PerLBusInterface0_n0277,
      CE => PerLBusInterface0_n0537,
      CLK => LCLK,
      SET => PerLBusInterface0_pCalDac_CLK_FFY_SET,
      RST => GND,
      O => PerLBusInterface0_pCalDac_CLK
    );
  PerLBusInterface0_pCalDac_CLK_FFY_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => PerLBusInterface0_pCalDac_CLK_SRMUX_OUTPUTNOT,
      O => PerLBusInterface0_pCalDac_CLK_FFY_SET
    );
  PerLBusInterface0_RegBank_0_13_1_1588 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pLD_13_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => pLD_13_IFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_13_1
    );
  pLD_13_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pLD_13_SRMUXNOT,
      O => pLD_13_IFF_SET
    );
  PerLBusInterface0_RegBank_0_14_1_1589 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_14_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_14_IFF_RST,
      O => PerLBusInterface0_RegBank_0_14_1
    );
  pLD_14_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_14_SRMUXNOT,
      I1 => GSR,
      O => pLD_14_IFF_RST
    );
  PerLBusInterface0_RegBank_17_15_1590 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_15_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_15_IFF_RST,
      O => PerLBusInterface0_RegBank_17_15
    );
  pLD_15_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_15_SRMUXNOT,
      I1 => GSR,
      O => pLD_15_IFF_RST
    );
  PerLBusInterface0_RegBank_17_16_1591 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_16_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_16_IFF_RST,
      O => PerLBusInterface0_RegBank_17_16
    );
  pLD_16_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_16_SRMUXNOT,
      I1 => GSR,
      O => pLD_16_IFF_RST
    );
  PerLBusInterface0_RegBank_0_24_1_1592 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_24_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_24_IFF_RST,
      O => PerLBusInterface0_RegBank_0_24_1
    );
  pLD_24_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_24_SRMUXNOT,
      I1 => GSR,
      O => pLD_24_IFF_RST
    );
  PerLBusInterface0_RegBank_17_25_1593 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_25_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_25_IFF_RST,
      O => PerLBusInterface0_RegBank_17_25
    );
  pLD_25_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_25_SRMUXNOT,
      I1 => GSR,
      O => pLD_25_IFF_RST
    );
  PerLBusInterface0_RegBank_17_26_1594 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_26_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_26_IFF_RST,
      O => PerLBusInterface0_RegBank_17_26
    );
  pLD_26_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_26_SRMUXNOT,
      I1 => GSR,
      O => pLD_26_IFF_RST
    );
  PerLBusInterface0_RegBank_17_27_1595 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_27_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_27_IFF_RST,
      O => PerLBusInterface0_RegBank_17_27
    );
  pLD_27_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_27_SRMUXNOT,
      I1 => GSR,
      O => pLD_27_IFF_RST
    );
  TriggerDelay0_DelayCount_0_58_1596 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_129,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_58_FFX_RST,
      O => TriggerDelay0_DelayCount_0_58
    );
  TriggerDelay0_DelayCount_0_58_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_58_FFX_RST
    );
  TriggerDelay0_DelayCount_0_61_1597 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_132,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_60_FFY_RST,
      O => TriggerDelay0_DelayCount_0_61
    );
  TriggerDelay0_DelayCount_0_60_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_60_FFY_RST
    );
  TriggerDelay0_DelayCount_0_60_1598 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_131,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_60_FFX_RST,
      O => TriggerDelay0_DelayCount_0_60
    );
  TriggerDelay0_DelayCount_0_60_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_60_FFX_RST
    );
  TriggerDelay0_DelayCount_0_63_1599 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_134,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_62_FFY_RST,
      O => TriggerDelay0_DelayCount_0_63
    );
  TriggerDelay0_DelayCount_0_62_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_62_FFY_RST
    );
  TriggerDelay0_DelayCount_0_62_1600 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_133,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_62_FFX_RST,
      O => TriggerDelay0_DelayCount_0_62
    );
  TriggerDelay0_DelayCount_0_62_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_62_FFX_RST
    );
  TriggerDelay0_DelayCount_0_65_1601 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_0_inst_sum_136,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_0_64_FFY_RST,
      O => TriggerDelay0_DelayCount_0_65
    );
  TriggerDelay0_DelayCount_0_64_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_0_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_0_64_FFY_RST
    );
  TriggerDelay0_DelayCount_1_72_1602 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_143,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_72_FFX_RST,
      O => TriggerDelay0_DelayCount_1_72
    );
  TriggerDelay0_DelayCount_1_72_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_72_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_72_FFX_RST
    );
  TriggerDelay0_DelayCount_1_70_1603 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_141,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_70_FFX_RST,
      O => TriggerDelay0_DelayCount_1_70
    );
  TriggerDelay0_DelayCount_1_70_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_70_FFX_RST
    );
  TriggerDelay0_DelayCount_2_57_1604 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_128,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_57_FFY_RST,
      O => TriggerDelay0_DelayCount_2_57
    );
  TriggerDelay0_DelayCount_2_57_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_57_FFY_RST
    );
  TriggerDelay0_DelayCount_2_59_1605 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_130,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_58_FFY_RST,
      O => TriggerDelay0_DelayCount_2_59
    );
  TriggerDelay0_DelayCount_2_58_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_58_FFY_RST
    );
  TriggerDelay0_DelayCount_2_61_1606 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_132,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_60_FFY_RST,
      O => TriggerDelay0_DelayCount_2_61
    );
  TriggerDelay0_DelayCount_2_60_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_60_FFY_RST
    );
  TriggerDelay0_DelayCount_2_64_1607 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_135,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_64_FFX_RST,
      O => TriggerDelay0_DelayCount_2_64
    );
  TriggerDelay0_DelayCount_2_64_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_64_FFX_RST
    );
  TriggerDelay0_DelayCount_2_66_1608 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_137,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_66_FFX_RST,
      O => TriggerDelay0_DelayCount_2_66
    );
  TriggerDelay0_DelayCount_2_66_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_66_FFX_RST
    );
  TriggerDelay0_DelayCount_2_69_1609 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_140,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_68_FFY_RST,
      O => TriggerDelay0_DelayCount_2_69
    );
  TriggerDelay0_DelayCount_2_68_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_68_FFY_RST
    );
  TriggerDelay0_DelayCount_2_68_1610 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_139,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_68_FFX_RST,
      O => TriggerDelay0_DelayCount_2_68
    );
  TriggerDelay0_DelayCount_2_68_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_68_FFX_RST
    );
  TriggerDelay0_DelayCount_2_71_1611 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_142,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_70_FFY_RST,
      O => TriggerDelay0_DelayCount_2_71
    );
  TriggerDelay0_DelayCount_2_70_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_70_FFY_RST
    );
  PerLBusInterface0_RegBank_17_17_1612 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_17_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_17_IFF_RST,
      O => PerLBusInterface0_RegBank_17_17
    );
  pLD_17_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_17_SRMUXNOT,
      I1 => GSR,
      O => pLD_17_IFF_RST
    );
  PerLBusInterface0_RegBank_17_18_1613 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_18_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_18_IFF_RST,
      O => PerLBusInterface0_RegBank_17_18
    );
  pLD_18_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_18_SRMUXNOT,
      I1 => GSR,
      O => pLD_18_IFF_RST
    );
  PerLBusInterface0_RegBank_17_19_1614 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_19_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_19_IFF_RST,
      O => PerLBusInterface0_RegBank_17_19
    );
  pLD_19_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_19_SRMUXNOT,
      I1 => GSR,
      O => pLD_19_IFF_RST
    );
  PerLBusInterface0_RegBank_0_1_1_1615 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pLD_1_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => pLD_1_IFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_1_1
    );
  pLD_1_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pLD_1_SRMUXNOT,
      O => pLD_1_IFF_SET
    );
  TriggerDelay0_DelayCount_3_60_1616 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_131,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_60_FFX_RST,
      O => TriggerDelay0_DelayCount_3_60
    );
  TriggerDelay0_DelayCount_3_60_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_60_FFX_RST
    );
  TriggerDelay0_DelayCount_3_63_1617 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_134,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_62_FFY_RST,
      O => TriggerDelay0_DelayCount_3_63
    );
  TriggerDelay0_DelayCount_3_62_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_62_FFY_RST
    );
  TriggerDelay0_DelayCount_3_62_1618 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_133,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_62_FFX_RST,
      O => TriggerDelay0_DelayCount_3_62
    );
  TriggerDelay0_DelayCount_3_62_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_62_FFX_RST
    );
  TriggerDelay0_DelayCount_3_65_1619 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_136,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_64_FFY_RST,
      O => TriggerDelay0_DelayCount_3_65
    );
  TriggerDelay0_DelayCount_3_64_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_64_FFY_RST
    );
  TriggerDelay0_DelayCount_3_67_1620 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_138,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_66_FFY_RST,
      O => TriggerDelay0_DelayCount_3_67
    );
  TriggerDelay0_DelayCount_3_66_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_66_FFY_RST
    );
  TriggerDelay0_DelayCount_3_64_1621 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_135,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_64_FFX_RST,
      O => TriggerDelay0_DelayCount_3_64
    );
  TriggerDelay0_DelayCount_3_64_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_64_FFX_RST
    );
  TriggerDelay0_DelayCount_1_58_1622 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_129,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_58_FFX_RST,
      O => TriggerDelay0_DelayCount_1_58
    );
  TriggerDelay0_DelayCount_1_58_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_58_FFX_RST
    );
  TriggerDelay0_DelayCount_1_60_1623 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_131,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_60_FFX_RST,
      O => TriggerDelay0_DelayCount_1_60
    );
  TriggerDelay0_DelayCount_1_60_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_60_FFX_RST
    );
  TriggerDelay0_DelayCount_1_63_1624 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_134,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_62_FFY_RST,
      O => TriggerDelay0_DelayCount_1_63
    );
  TriggerDelay0_DelayCount_1_62_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_62_FFY_RST
    );
  TriggerDelay0_DelayCount_1_62_1625 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_133,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_62_FFX_RST,
      O => TriggerDelay0_DelayCount_1_62
    );
  TriggerDelay0_DelayCount_1_62_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_62_FFX_RST
    );
  TriggerDelay0_DelayCount_1_65_1626 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_136,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_64_FFY_RST,
      O => TriggerDelay0_DelayCount_1_65
    );
  TriggerDelay0_DelayCount_1_64_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_64_FFY_RST
    );
  TriggerDelay0_DelayCount_1_67_1627 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_1_inst_sum_138,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_1_66_FFY_RST,
      O => TriggerDelay0_DelayCount_1_67
    );
  TriggerDelay0_DelayCount_1_66_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_1_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_1_66_FFY_RST
    );
  TriggerDelay0_DelayCount_2_58_1628 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_129,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_58_FFX_RST,
      O => TriggerDelay0_DelayCount_2_58
    );
  TriggerDelay0_DelayCount_2_58_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_58_FFX_RST
    );
  TriggerDelay0_DelayCount_2_60_1629 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_131,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_60_FFX_RST,
      O => TriggerDelay0_DelayCount_2_60
    );
  TriggerDelay0_DelayCount_2_60_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_60_FFX_RST
    );
  TriggerDelay0_DelayCount_2_63_1630 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_134,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_62_FFY_RST,
      O => TriggerDelay0_DelayCount_2_63
    );
  TriggerDelay0_DelayCount_2_62_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_62_FFY_RST
    );
  TriggerDelay0_DelayCount_2_62_1631 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_133,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_62_FFX_RST,
      O => TriggerDelay0_DelayCount_2_62
    );
  TriggerDelay0_DelayCount_2_62_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_62_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_62_FFX_RST
    );
  TriggerDelay0_DelayCount_2_65_1632 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_136,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_64_FFY_RST,
      O => TriggerDelay0_DelayCount_2_65
    );
  TriggerDelay0_DelayCount_2_64_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_64_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_64_FFY_RST
    );
  TriggerDelay0_DelayCount_2_67_1633 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_138,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_66_FFY_RST,
      O => TriggerDelay0_DelayCount_2_67
    );
  TriggerDelay0_DelayCount_2_66_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_66_FFY_RST
    );
  TriggerDelay0_DelayCount_2_70_1634 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_141,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_70_FFX_RST,
      O => TriggerDelay0_DelayCount_2_70
    );
  TriggerDelay0_DelayCount_2_70_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_70_FFX_RST
    );
  TriggerDelay0_DelayCount_2_72_1635 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_2_inst_sum_143,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_2_72_FFX_RST,
      O => TriggerDelay0_DelayCount_2_72
    );
  TriggerDelay0_DelayCount_2_72_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_2_72_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_2_72_FFX_RST
    );
  TriggerDelay0_DelayCount_3_57_1636 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_128,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_57_FFY_RST,
      O => TriggerDelay0_DelayCount_3_57
    );
  TriggerDelay0_DelayCount_3_57_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_57_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_57_FFY_RST
    );
  TriggerDelay0_DelayCount_3_59_1637 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_130,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_58_FFY_RST,
      O => TriggerDelay0_DelayCount_3_59
    );
  TriggerDelay0_DelayCount_3_58_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_58_FFY_RST
    );
  TriggerDelay0_DelayCount_3_61_1638 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_132,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_60_FFY_RST,
      O => TriggerDelay0_DelayCount_3_61
    );
  TriggerDelay0_DelayCount_3_60_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_60_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_60_FFY_RST
    );
  TriggerDelay0_DelayCount_3_58_1639 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_129,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_58_FFX_RST,
      O => TriggerDelay0_DelayCount_3_58
    );
  TriggerDelay0_DelayCount_3_58_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_58_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_58_FFX_RST
    );
  PerLBusInterface0_RegBank_19_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_0_IDELAY,
      CE => PerLBusInterface0_n0510,
      CLK => LCLK,
      SET => GND,
      RST => pLD_0_IFF_RST,
      O => PerLBusInterface0_RegBank_19_0_Q
    );
  pLD_0_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_0_SRMUXNOT,
      I1 => GSR,
      O => pLD_0_IFF_RST
    );
  PerLBusInterface0_RegBank_0_10_1_1640 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_10_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_10_IFF_RST,
      O => PerLBusInterface0_RegBank_0_10_1
    );
  pLD_10_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_10_SRMUXNOT,
      I1 => GSR,
      O => pLD_10_IFF_RST
    );
  PerLBusInterface0_RegBank_0_11_1_1641 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_11_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_11_IFF_RST,
      O => PerLBusInterface0_RegBank_0_11_1
    );
  pLD_11_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_11_SRMUXNOT,
      I1 => GSR,
      O => pLD_11_IFF_RST
    );
  PerLBusInterface0_RegBank_0_12_1_1642 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_12_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_12_IFF_RST,
      O => PerLBusInterface0_RegBank_0_12_1
    );
  pLD_12_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_12_SRMUXNOT,
      I1 => GSR,
      O => pLD_12_IFF_RST
    );
  TriggerDelay0_DelayCount_3_66_1643 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_137,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_66_FFX_RST,
      O => TriggerDelay0_DelayCount_3_66
    );
  TriggerDelay0_DelayCount_3_66_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_66_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_66_FFX_RST
    );
  TriggerDelay0_DelayCount_3_69_1644 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_140,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_68_FFY_RST,
      O => TriggerDelay0_DelayCount_3_69
    );
  TriggerDelay0_DelayCount_3_68_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_68_FFY_RST
    );
  TriggerDelay0_DelayCount_3_68_1645 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_139,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_68_FFX_RST,
      O => TriggerDelay0_DelayCount_3_68
    );
  TriggerDelay0_DelayCount_3_68_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_68_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_68_FFX_RST
    );
  TriggerDelay0_DelayCount_3_71_1646 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_142,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_70_FFY_RST,
      O => TriggerDelay0_DelayCount_3_71
    );
  TriggerDelay0_DelayCount_3_70_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_70_FFY_RST
    );
  TriggerDelay0_TriggerOut_3 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0026,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerOut_3_FFY_RST,
      O => TriggerDelay0_TriggerOut(3)
    );
  TriggerDelay0_TriggerOut_3_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerOut_3_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerOut_3_FFY_RST
    );
  TriggerDelay0_TriggerRegs_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => RawTrigger,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerRegs_1_FFY_RST,
      O => TriggerDelay0_TriggerRegs(0)
    );
  TriggerDelay0_TriggerRegs_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerRegs_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerRegs_1_FFY_RST
    );
  TriggerDelay0_TriggerRegs_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_TriggerRegs_1_1,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerRegs_2_FFY_RST,
      O => TriggerDelay0_TriggerRegs(2)
    );
  TriggerDelay0_TriggerRegs_2_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerRegs_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerRegs_2_FFY_RST
    );
  TriggerDelay0_TriggerRegs_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_TriggerRegs(0),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerRegs_1_FFX_RST,
      O => TriggerDelay0_TriggerRegs(1)
    );
  TriggerDelay0_TriggerRegs_1_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerRegs_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerRegs_1_FFX_RST
    );
  TriggerDelay0_TriggerRegs_1_1_1647 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_TriggerRegs(0),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerRegs_1_1_FFY_RST,
      O => TriggerDelay0_TriggerRegs_1_1
    );
  TriggerDelay0_TriggerRegs_1_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerRegs_1_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerRegs_1_1_FFY_RST
    );
  PerLBusInterface0_RegBank_0_2_1_1648 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pAIN_0_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pAIN_0_OFF_RST,
      O => PerLBusInterface0_RegBank_0_2_1
    );
  pAIN_0_OFF_RSTOR : X_OR2
    port map (
      I0 => pAIN_0_SRMUXNOT,
      I1 => GSR,
      O => pAIN_0_OFF_RST
    );
  PerLBusInterface0_RegBank_0_3_1_1649 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pAIN_1_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => pAIN_1_OFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_3_1
    );
  pAIN_1_OFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pAIN_1_SRMUXNOT,
      O => pAIN_1_OFF_SET
    );
  PerLBusInterface0_RegBank_0_4_1_1650 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pAIN_2_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pAIN_2_OFF_RST,
      O => PerLBusInterface0_RegBank_0_4_1
    );
  pAIN_2_OFF_RSTOR : X_OR2
    port map (
      I0 => pAIN_2_SRMUXNOT,
      I1 => GSR,
      O => pAIN_2_OFF_RST
    );
  PerLBusInterface0_RegBank_0_5_1_1651 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pAIN_3_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pAIN_3_OFF_RST,
      O => PerLBusInterface0_RegBank_0_5_1
    );
  pAIN_3_OFF_RSTOR : X_OR2
    port map (
      I0 => pAIN_3_SRMUXNOT,
      I1 => GSR,
      O => pAIN_3_OFF_RST
    );
  TriggerDelay0_DelayCount_3_70_1652 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_141,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_70_FFX_RST,
      O => TriggerDelay0_DelayCount_3_70
    );
  TriggerDelay0_DelayCount_3_70_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_70_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_70_FFX_RST
    );
  TriggerDelay0_DelayCount_3_72_1653 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_DelayCount_3_inst_sum_143,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_DelayCount_3_72_FFX_RST,
      O => TriggerDelay0_DelayCount_3_72
    );
  TriggerDelay0_DelayCount_3_72_FFX_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_DelayCount_3_72_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_DelayCount_3_72_FFX_RST
    );
  TriggerDelay0_OutShifter_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0038(0),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_OutShifter_0_FFY_RST,
      O => TriggerDelay0_OutShifter(0)
    );
  TriggerDelay0_OutShifter_0_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_OutShifter_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_OutShifter_0_FFY_RST
    );
  TriggerDelay0_OutShifter_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0038(1),
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_OutShifter_1_FFY_RST,
      O => TriggerDelay0_OutShifter(1)
    );
  TriggerDelay0_OutShifter_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_OutShifter_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_OutShifter_1_FFY_RST
    );
  TriggerDelay0_TriggerOut_0 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0029,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerOut_0_FFY_RST,
      O => TriggerDelay0_TriggerOut(0)
    );
  TriggerDelay0_TriggerOut_0_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerOut_0_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerOut_0_FFY_RST
    );
  TriggerDelay0_TriggerOut_1 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0028,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerOut_1_FFY_RST,
      O => TriggerDelay0_TriggerOut(1)
    );
  TriggerDelay0_TriggerOut_1_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerOut_1_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerOut_1_FFY_RST
    );
  TriggerDelay0_TriggerOut_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => TriggerDelay0_n0027,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => TriggerDelay0_TriggerOut_2_FFY_RST,
      O => TriggerDelay0_TriggerOut(2)
    );
  TriggerDelay0_TriggerOut_2_FFY_RSTOR : X_OR2
    port map (
      I0 => TriggerDelay0_TriggerOut_2_SRMUX_OUTPUTNOT,
      I1 => GSR,
      O => TriggerDelay0_TriggerOut_2_FFY_RST
    );
  PerLBusInterface0_RegBank_0_20_1_1654 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pCAL_0_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => pCAL_0_OFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_20_1
    );
  pCAL_0_OFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pCAL_0_SRMUXNOT,
      O => pCAL_0_OFF_SET
    );
  PerLBusInterface0_RegBank_0_21_1_1655 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCAL_1_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pCAL_1_OFF_RST,
      O => PerLBusInterface0_RegBank_0_21_1
    );
  pCAL_1_OFF_RSTOR : X_OR2
    port map (
      I0 => pCAL_1_SRMUXNOT,
      I1 => GSR,
      O => pCAL_1_OFF_RST
    );
  PerLBusInterface0_RegBank_0_22_1_1656 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCAL_2_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pCAL_2_OFF_RST,
      O => PerLBusInterface0_RegBank_0_22_1
    );
  pCAL_2_OFF_RSTOR : X_OR2
    port map (
      I0 => pCAL_2_SRMUXNOT,
      I1 => GSR,
      O => pCAL_2_OFF_RST
    );
  OFD1_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCalDac_CLK_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pCalDac_CLK_OFF_RST,
      O => OFD1_QBUF
    );
  pCalDac_CLK_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pCalDac_CLK_OFF_RST
    );
  OFD0_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCalDac_SDI_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pCalDac_SDI_OFF_RST,
      O => OFD0_QBUF
    );
  pCalDac_SDI_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pCalDac_SDI_OFF_RST
    );
  IFD0_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder0In_0_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder0In_0_IFF_RST,
      O => IFD0
    );
  pEncoder0In_0_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder0In_0_IFF_RST
    );
  IFD1_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder0In_1_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder0In_1_IFF_RST,
      O => IFD1
    );
  pEncoder0In_1_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder0In_1_IFF_RST
    );
  IFD2_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder1In_0_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder1In_0_IFF_RST,
      O => IFD2
    );
  pEncoder1In_0_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder1In_0_IFF_RST
    );
  IFD3_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder1In_1_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder1In_1_IFF_RST,
      O => IFD3
    );
  pEncoder1In_1_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder1In_1_IFF_RST
    );
  IFD4_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder2In_0_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder2In_0_IFF_RST,
      O => IFD4
    );
  pEncoder2In_0_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder2In_0_IFF_RST
    );
  IFD5_INFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pEncoder2In_1_IDELAY,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pEncoder2In_1_IFF_RST,
      O => IFD5
    );
  pEncoder2In_1_IFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pEncoder2In_1_IFF_RST
    );
  OFD3_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCalDac_nCS_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pCalDac_nCS_OFF_RST,
      O => OFD3_QBUF
    );
  pCalDac_nCS_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pCalDac_nCS_OFF_RST
    );
  OFD2_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pCalDac_nLD_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pCalDac_nLD_OFF_RST,
      O => OFD2_QBUF
    );
  pCalDac_nLD_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pCalDac_nLD_OFF_RST
    );
  PerLBusInterface0_RegBank_0_19_1_1657 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pDdsFsk_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pDdsFsk_OFF_RST,
      O => PerLBusInterface0_RegBank_0_19_1
    );
  pDdsFsk_OFF_RSTOR : X_OR2
    port map (
      I0 => pDdsFsk_SRMUXNOT,
      I1 => GSR,
      O => pDdsFsk_OFF_RST
    );
  PerLBusInterface0_RegBank_0_18_1_1658 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pDdsKey_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pDdsKey_OFF_RST,
      O => PerLBusInterface0_RegBank_0_18_1
    );
  pDdsKey_OFF_RSTOR : X_OR2
    port map (
      I0 => pDdsKey_SRMUXNOT,
      I1 => GSR,
      O => pDdsKey_OFF_RST
    );
  PerLBusInterface0_RegBank_17_31_1659 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_31_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_31_IFF_RST,
      O => PerLBusInterface0_RegBank_17_31
    );
  pLD_31_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_31_SRMUXNOT,
      I1 => GSR,
      O => pLD_31_IFF_RST
    );
  PerLBusInterface0_RegBank_17_3_1660 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_3_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_3_IFF_RST,
      O => PerLBusInterface0_RegBank_17_3
    );
  pLD_3_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_3_SRMUXNOT,
      I1 => GSR,
      O => pLD_3_IFF_RST
    );
  PerLBusInterface0_RegBank_17_4_1661 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_4_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_4_IFF_RST,
      O => PerLBusInterface0_RegBank_17_4
    );
  pLD_4_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_4_SRMUXNOT,
      I1 => GSR,
      O => pLD_4_IFF_RST
    );
  PerLBusInterface0_RegBank_17_5_1662 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_5_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_5_IFF_RST,
      O => PerLBusInterface0_RegBank_17_5
    );
  pLD_5_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_5_SRMUXNOT,
      I1 => GSR,
      O => pLD_5_IFF_RST
    );
  OFD9_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ6_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ6_OFF_RST,
      O => OFD9_QBUF
    );
  pZ6_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ6_OFF_RST
    );
  OFD10_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ7_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ7_OFF_RST,
      O => OFD10_QBUF
    );
  pZ7_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ7_OFF_RST
    );
  PerLBusInterface0_RegBank_1_16_1_1663 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pZ11_OD,
      CE => PerLBusInterface0_n0464,
      CLK => LCLK,
      SET => pZ11_OFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_1_16_1
    );
  pZ11_OFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pZ11_SRMUXNOT,
      O => pZ11_OFF_SET
    );
  OFD5_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ2_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ2_OFF_RST,
      O => OFD5_QBUF
    );
  pZ2_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ2_OFF_RST
    );
  OFD6_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ3_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ3_OFF_RST,
      O => OFD6_QBUF
    );
  pZ3_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ3_OFF_RST
    );
  OFD7_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ4_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ4_OFF_RST,
      O => OFD7_QBUF
    );
  pZ4_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ4_OFF_RST
    );
  OFD8_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ5_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ5_OFF_RST,
      O => OFD8_QBUF
    );
  pZ5_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ5_OFF_RST
    );
  PerLBusInterface0_RegBank_17_20_1664 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_20_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_20_IFF_RST,
      O => PerLBusInterface0_RegBank_17_20
    );
  pLD_20_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_20_SRMUXNOT,
      I1 => GSR,
      O => pLD_20_IFF_RST
    );
  PerLBusInterface0_RegBank_17_21_1665 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_21_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_21_IFF_RST,
      O => PerLBusInterface0_RegBank_17_21
    );
  pLD_21_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_21_SRMUXNOT,
      I1 => GSR,
      O => pLD_21_IFF_RST
    );
  PerLBusInterface0_RegBank_17_22_1666 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_22_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_22_IFF_RST,
      O => PerLBusInterface0_RegBank_17_22
    );
  pLD_22_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_22_SRMUXNOT,
      I1 => GSR,
      O => pLD_22_IFF_RST
    );
  PerLBusInterface0_RegBank_0_23_1_1667 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_23_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_23_IFF_RST,
      O => PerLBusInterface0_RegBank_0_23_1
    );
  pLD_23_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_23_SRMUXNOT,
      I1 => GSR,
      O => pLD_23_IFF_RST
    );
  PerLBusInterface0_RegBank_17_12_1668 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_12_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_12_OFF_RST,
      O => PerLBusInterface0_RegBank_17_12
    );
  pPIO_12_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_12_SRMUXNOT,
      I1 => GSR,
      O => pPIO_12_OFF_RST
    );
  PerLBusInterface0_RegBank_17_13_1669 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_13_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_13_OFF_RST,
      O => PerLBusInterface0_RegBank_17_13
    );
  pPIO_13_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_13_SRMUXNOT,
      I1 => GSR,
      O => pPIO_13_OFF_RST
    );
  PerLBusInterface0_RegBank_17_14_1670 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_14_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_14_OFF_RST,
      O => PerLBusInterface0_RegBank_17_14
    );
  pPIO_14_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_14_SRMUXNOT,
      I1 => GSR,
      O => pPIO_14_OFF_RST
    );
  PerLBusInterface0_RegBank_0_6_1_1671 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pLD_6_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => pLD_6_IFF_SET,
      RST => GND,
      O => PerLBusInterface0_RegBank_0_6_1
    );
  pLD_6_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pLD_6_SRMUXNOT,
      O => pLD_6_IFF_SET
    );
  PerLBusInterface0_RegBank_0_7_1_1672 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_7_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_7_IFF_RST,
      O => PerLBusInterface0_RegBank_0_7_1
    );
  pLD_7_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_7_SRMUXNOT,
      I1 => GSR,
      O => pLD_7_IFF_RST
    );
  PerLBusInterface0_RegBank_0_8_1_1673 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_8_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_8_IFF_RST,
      O => PerLBusInterface0_RegBank_0_8_1
    );
  pLD_8_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_8_SRMUXNOT,
      I1 => GSR,
      O => pLD_8_IFF_RST
    );
  PerLBusInterface0_RegBank_0_9_1_1674 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_9_IDELAY,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pLD_9_IFF_RST,
      O => PerLBusInterface0_RegBank_0_9_1
    );
  pLD_9_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_9_SRMUXNOT,
      I1 => GSR,
      O => pLD_9_IFF_RST
    );
  PerLBusInterface0_RegBank_17_28_1675 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_28_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_28_IFF_RST,
      O => PerLBusInterface0_RegBank_17_28
    );
  pLD_28_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_28_SRMUXNOT,
      I1 => GSR,
      O => pLD_28_IFF_RST
    );
  PerLBusInterface0_RegBank_17_29_1676 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_29_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_29_IFF_RST,
      O => PerLBusInterface0_RegBank_17_29
    );
  pLD_29_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_29_SRMUXNOT,
      I1 => GSR,
      O => pLD_29_IFF_RST
    );
  PerLBusInterface0_RegBank_17_2_1677 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_2_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_2_IFF_RST,
      O => PerLBusInterface0_RegBank_17_2
    );
  pLD_2_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_2_SRMUXNOT,
      I1 => GSR,
      O => pLD_2_IFF_RST
    );
  PerLBusInterface0_RegBank_17_30_1678 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pLD_30_IDELAY,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pLD_30_IFF_RST,
      O => PerLBusInterface0_RegBank_17_30
    );
  pLD_30_IFF_RSTOR : X_OR2
    port map (
      I0 => pLD_30_SRMUXNOT,
      I1 => GSR,
      O => pLD_30_IFF_RST
    );
  PerLBusInterface0_LWnR_1679 : X_FF
    generic map(
      INIT => '1'
    )
    port map (
      I => pLWnR_IDELAY,
      CE => pnFpgaCs_IBUF,
      CLK => LCLK,
      SET => pLWnR_IFF_SET,
      RST => GND,
      O => PerLBusInterface0_LWnR
    );
  pLWnR_IFF_SETOR : X_OR2
    port map (
      I0 => GSR,
      I1 => pLWnR_SRMUXNOT,
      O => pLWnR_IFF_SET
    );
  PerLBusInterface0_RegBank_17_10_1680 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_10_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_10_OFF_RST,
      O => PerLBusInterface0_RegBank_17_10
    );
  pPIO_10_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_10_SRMUXNOT,
      I1 => GSR,
      O => pPIO_10_OFF_RST
    );
  PerLBusInterface0_RegBank_17_11_1681 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_11_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_11_OFF_RST,
      O => PerLBusInterface0_RegBank_17_11
    );
  pPIO_11_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_11_SRMUXNOT,
      I1 => GSR,
      O => pPIO_11_OFF_RST
    );
  PerLBusInterface0_RegBank_17_7_1682 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_7_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_7_OFF_RST,
      O => PerLBusInterface0_RegBank_17_7
    );
  pPIO_7_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_7_SRMUXNOT,
      I1 => GSR,
      O => pPIO_7_OFF_RST
    );
  PerLBusInterface0_RegBank_17_8_1683 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_8_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_8_OFF_RST,
      O => PerLBusInterface0_RegBank_17_8
    );
  pPIO_8_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_8_SRMUXNOT,
      I1 => GSR,
      O => pPIO_8_OFF_RST
    );
  PerLBusInterface0_RegBank_17_9_1684 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_9_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_9_OFF_RST,
      O => PerLBusInterface0_RegBank_17_9
    );
  pPIO_9_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_9_SRMUXNOT,
      I1 => GSR,
      O => pPIO_9_OFF_RST
    );
  PerLBusInterface0_RegBank_17_6_1685 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_6_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_6_OFF_RST,
      O => PerLBusInterface0_RegBank_17_6
    );
  pPIO_6_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_6_SRMUXNOT,
      I1 => GSR,
      O => pPIO_6_OFF_RST
    );
  PerLBusInterface0_RegBank_17_23_1686 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_23_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_23_OFF_RST,
      O => PerLBusInterface0_RegBank_17_23
    );
  pPIO_23_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_23_SRMUXNOT,
      I1 => GSR,
      O => pPIO_23_OFF_RST
    );
  PerLBusInterface0_RegBank_17_24_1687 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pPIO_24_OD,
      CE => PerLBusInterface0_n0489,
      CLK => LCLK,
      SET => GND,
      RST => pPIO_24_OFF_RST,
      O => PerLBusInterface0_RegBank_17_24
    );
  pPIO_24_OFF_RSTOR : X_OR2
    port map (
      I0 => pPIO_24_SRMUXNOT,
      I1 => GSR,
      O => pPIO_24_OFF_RST
    );
  PerLBusInterface0_RegBank_0_0_1_1688 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pSEL_AC_DC_OD,
      CE => PerLBusInterface0_n0461,
      CLK => LCLK,
      SET => GND,
      RST => pSEL_AC_DC_OFF_RST,
      O => PerLBusInterface0_RegBank_0_0_1
    );
  pSEL_AC_DC_OFF_RSTOR : X_OR2
    port map (
      I0 => pSEL_AC_DC_SRMUXNOT,
      I1 => GSR,
      O => pSEL_AC_DC_OFF_RST
    );
  OFD4_OUTFF : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ1_OD,
      CE => VCC,
      CLK => LCLK,
      SET => GND,
      RST => pZ1_OFF_RST,
      O => OFD4_QBUF
    );
  pZ1_OFF_RSTOR : X_BUF
    port map (
      I => GSR,
      O => pZ1_OFF_RST
    );
  TriggerDelay0_OutShifter_2 : X_FF
    generic map(
      INIT => '0'
    )
    port map (
      I => pZ10_OD,
      CE => VCC,
      CLK => SampleClk,
      SET => GND,
      RST => pZ10_OFF_RST,
      O => TriggerDelay0_OutShifter(2)
    );
  pZ10_OFF_RSTOR : X_OR2
    port map (
      I0 => pZ10_SRMUXNOT,
      I1 => GSR,
      O => pZ10_OFF_RST
    );
  pLED_D9_OBUF_VCC : X_ONE
    port map (
      O => pLED_D9_OBUF
    );
  EncoderMonitor0_EncoderReset_3_GND : X_ZERO
    port map (
      O => EncoderMonitor0_EncoderReset(3)
    );
  BUFG0_BUF : X_CKBUF
    port map (
      I => Sample2xClk_NoBuff,
      O => Sample2xClk
    );
  BUFG1_BUF : X_CKBUF
    port map (
      I => SampleClk_NoBuff,
      O => SampleClk
    );
  pLCLK_BUF : X_CKBUF
    port map (
      I => pLCLK,
      O => LCLK
    );
  pSampleClk_BUF : X_CKBUF
    port map (
      I => pSampleClk,
      O => SampleClkIn
    );
  NlwBlock_peripheralfpgatop_VCC : X_ONE
    port map (
      O => VCC
    );
  NlwBlock_peripheralfpgatop_GND : X_ZERO
    port map (
      O => GND
    );
  NlwBlockROC : X_ROC
    generic map (ROC_WIDTH => 100 ns)
    port map (O => GSR);
  NlwBlockTOC : X_TOC
    port map (O => GTS);

end Structure;

