JDF G
// Created by Project Navigator ver 1.0
PROJECT original-tidied
DESIGN dspfpgav0
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 0
DEVSPEED -6
DEVSPEEDTIME 1129923378
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 1086179439
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\src\DspFpgaTop.vhd
SOURCE ..\src\DataInterleave.vhd
SOURCE ..\src\LBusInterface.vhd
SOURCE ..\src\SramSwitching.vhd
SOURCE ..\src\DataRectifier.vhd
SOURCE ..\src\SramWriteCtrl.vhd
SOURCE ..\src\DspFpgaPkg.vhd
SOURCE ..\src\TriggerGenerator.vhd
SOURCE ..\src\InterfaceGate.vhd
SOURCE ..\src\Gate.vhd
SOURCE ..\src\GateResultSelect.vhd
SOURCE ..\src\TcgCtrl.vhd
SOURCE ..\..\SharedComps\src\DualPortRam.vhd
SOURCE ..\src\CurvedGate.vhd
SOURCE ..\..\SharedComps\src\RippleCounter.vhd
SOURCE ..\..\SharedComps\src\StrobeExtender.vhd
SOURCE ..\src\DspFpgaPkgV0.vhd
SOURCE ..\src\PCK_CRC32_D16.vhd
SOURCE ..\..\SharedComps\src\DPBRAM32x256.vhd
DEPASSOC dspfpgatop ..\constraints\DspFpga.ucf
[Normal]
p_xstEquivRegRemoval=xstvhd, spartan2, VHDL.t_synthesize, 1082634598, True
p_xstGenerateRTLNetlist=xstvhd, spartan2, VHDL.t_synthesize, 1078854740, No
p_xstOptimizeInsPrimtives=xstvhd, spartan2, VHDL.t_synthesize, 1082386425, True
p_xstUseSynthConstFile=xstvhd, spartan2, VHDL.t_synthesize, 1078854804, False
p_xstWriteTimingConstraints=xstvhd, spartan2, VHDL.t_synthesize, 1078916444, True
xilxBitgCfg_GenOpt_BinaryFile=xstvhd, spartan2, VHDL.t_bitFile, 1078919187, True
xilxMapCoverMode=xstvhd, spartan2, Implementation.t_map, 1087467973, Area
xilxMapPackRegInto=xstvhd, spartan2, Implementation.t_map, 1084379684, For Inputs and Outputs
xilxMapReportDetail=xstvhd, spartan2, Implementation.t_map, 1078916497, True
xilxPAReffortLevel=xstvhd, spartan2, Implementation.t_par, 1078854768, High
xilxPARguideMode=xstvhd, spartan2, Implementation.t_par, 1129842931, None
xilxPARplacerCostTable=xstvhd, spartan2, Implementation.t_par, 1083151986, 1
xilxPostTrceRpt=xstvhd, spartan2, Implementation.t_postRouteTrce, 1078916497, Verbose Report
xilxPostTrceRptLimit=xstvhd, spartan2, Implementation.t_postRouteTrce, 1078916497, 5
xilxPostTrceRptTiming=xstvhd, spartan2, Implementation.t_postRouteTrce, 1078916497, 5
xilxPreTrceRpt=xstvhd, spartan2, Implementation.t_preRouteTrce, 1078916497, Verbose Report
xilxPreTrceRptLimit=xstvhd, spartan2, Implementation.t_preRouteTrce, 1078916497, 5
xilxPreTrceRptTiming=xstvhd, spartan2, Implementation.t_preRouteTrce, 1078916497, 5
xilxSynthRegBalancing=xstvhd, spartan2, VHDL.t_synthesize, 1129618247, No
_SynthConstraintsFile=xstvhd, spartan2, VHDL.t_synthesize, 1078854804,
_SynthFsmEncode=xstvhd, spartan2, VHDL.t_synthesize, 1129834775, Auto
_SynthOpt=xstvhd, spartan2, VHDL.t_synthesize, 1141384488, Area
_SynthOptEffort=xstvhd, spartan2, VHDL.t_synthesize, 1141383556, Normal
_SynthResSharing=xstvhd, spartan2, VHDL.t_synthesize, 1129924951, True
[STATUS-ALL]
dspfpgatop.ngcFile=WARNINGS,1141384535
[STRATEGY-LIST]
Normal=True
