---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: DelayValueRam.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card Peripheral FPGA
--
-- Design Description:
-- Module to implement a Dual Port RAM to hold delay values for the
-- focusing unit.  The dual port RAM has one write-only side which one
-- 32-bit wide data bus for software to fill the RAM with data.
-- The second port is read only and has an 8-bit data bus, allowing 'free'
-- bus width conversion.
--
-- This module instantiates a CoreGen module as the synthesis tools could
-- not be made to infer Dual Port RAM with different bus widths.
-- A simulation version of the CoreGen module is also provided for
-- simulation purposes only.
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity DelayValueRam is
  port(-- Port 1
       pClk       : in  std_ulogic;
       pWriteEn   : in  std_ulogic;
       pAddr      : in  std_logic_vector(8 downto 0);
       pDataIn    : in  std_logic_vector(31 downto 0);
       -- Port 2
       pDpClk     : in  std_ulogic;
       pDpAddr    : in  std_logic_vector(10 downto 0);
       pDpDataOut : out std_logic_vector(7 downto 0));
end entity DelayValueRam;


architecture syn of DelayValueRam is

  component delay_value_ram
    port (addra : in  std_logic_vector(10 downto 0);
          addrb : in  std_logic_vector(8 downto 0);
          clka  : in  std_logic;
          clkb  : in  std_logic;
          dinb  : in  std_logic_vector(31 downto 0);
          douta : out std_logic_vector(7 downto 0);
          web   : in  std_logic);
  end component delay_value_ram;


begin

  delay_value_ram0: delay_value_ram
    port map(addra => pDpAddr,
             addrb => pAddr,
             clka  => pDpClk,
             clkb  => pClk,
             dinb  => pDataIn,
             douta => pDpDataOut,
             web   => pWriteEn);

end syn;
