---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2006
--
-- Filename: BeaSwitch.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Module to switch between inputs when Bea Gate triggers
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity BeaSwitch is
  port(pnReset         : in  std_ulogic;
       pADC_2xClk      : in  std_ulogic;
       pTriggersIn     : in  std_logic_vector(7 downto 0);
       pTriggerNum     : in  std_logic_vector(2 downto 0);
       pBeaEnable      : in  std_ulogic;
       pBeaSwitch      : out std_ulogic);
end entity BeaSwitch;


architecture Rtl of BeaSwitch is

  signal BeaSwitch : std_ulogic;
begin

  GenSwitch: process(pnReset, pADC_2xClk)
  begin
    if pnReset = '0' then
      BeaSwitch <= '0';
      pBeaSwitch <= '0';
    elsif rising_edge(pADC_2xClk) then
      if pBeaEnable = '1' and pTriggersIn(conv_integer(unsigned(pTriggerNum))) = '1' then
        BeaSwitch <= '1';
      else
        BeaSwitch <= '0';
      end if;
      pBeaSwitch <= BeaSwitch;
    end if;
  end process GenSwitch;

end architecture Rtl;