---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: PeripheralFpgaPkg.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card Peripheral FPGA
--
-- Design Description:
-- VHDL package for Peripheral FPGA
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

-- Bring in the constant cFpgaVersion to define the FPGA version
library work;
use work.PeripheralVerPkg.all;


package PeripheralFpgaPkg is

  --
  -- Modify cFpgaRevision to set the revision of the FPGA
  --
  constant cFpgaRevision: std_logic_vector(11 downto 0) := X"115";
  --
  --
  --


  constant cNoOfRegs :  integer := 64; -- (Unused regs will be optimised out)
  constant cDecodeBits: integer := 8;
  constant cRegBase  : std_logic_vector(31 downto 0) := X"00500400";

  -- Register Names and offset (/4) from cRegBase
  constant cHardwareCtrl       : integer := 16#00# / 4;
  constant cTriggerCtrl        : integer := 16#04# / 4;
  constant cPulseGenerator     : integer := 16#08# / 4;
  constant cCalibrationData    : integer := 16#0C# / 4;
  constant cAScanCtrl          : integer := 16#10# / 4;
  constant cSensorSetup        : integer := 16#14# / 4;
  constant cPingPongData       : integer := 16#18# / 4;
  constant cBScanTriggerCtrl   : integer := 16#1C# / 4;
  constant cEncoder0Output     : integer := 16#20# / 4;
  constant cEncoder1Output     : integer := 16#24# / 4;
  constant cEncoder2Output     : integer := 16#28# / 4;
  constant cEncoder3Output     : integer := 16#2C# / 4;
  constant cEncoder4Output     : integer := 16#30# / 4;
  constant cEncoder5Output     : integer := 16#34# / 4;
  constant cGateStartStop      : integer := 16#38# / 4;
  constant cGateAttributes     : integer := 16#3C# / 4;
  constant cGateSetup          : integer := 16#40# / 4;
  constant cPerIoBank0         : integer := 16#44# / 4;
  constant cPerIoDdr0          : integer := 16#48# / 4;
  constant cFocusUnitCtrl      : integer := 16#4C# / 4;
  constant cDelayValueData     : integer := 16#50# / 4;
  constant cPerIoBank1         : integer := 16#64# / 4;
  constant cPerIoDdr1          : integer := 16#68# / 4;
  --
  constant cPerFpgaVer         : integer := 16#FC# / 4;


  -- Type to hold array of registers
  type tRegSet is array(0 to cNoOfRegs-1) of std_logic_vector(31 downto 0);
  type tRegSetArray is array(0 to 1) of tRegSet;

  -- Constant holding initial register values
  -- (Only writable bits have initial values)
  constant cRegSetInitVals: tRegSetArray :=
                                      ((-- Register Init Values for Version 0 of the FPGA
                                        cHardwareCtrl       => X"0010A04A",
                                        cTriggerCtrl        => X"00010000",
                                        cPulseGenerator     => X"00000008",
                                        cCalibrationData    => X"00000000",
                                        cAScanCtrl          => X"00000000",
                                        cSensorSetup        => X"00000000",
                                        cPingPongData       => X"00000000",
                                        cBScanTriggerCtrl   => X"00070050",
                                        cEncoder0Output     => X"00000000",
                                        cEncoder1Output     => X"00000000",
                                        cEncoder2Output     => X"00000000",
                                        cEncoder3Output     => X"00000000",
                                        cEncoder4Output     => X"00000000",
                                        cEncoder5Output     => X"00000000",
                                        cGateStartStop      => X"00000000",
                                        cGateAttributes     => X"00000000",
                                        cGateSetup          => X"00000000",
                                        cPerIoBank0         => X"00000000",
                                        cPerIoDdr0          => X"00000000",
                                        cPerIoBank1         => X"00000000",
                                        cPerIoDdr1          => X"00000000",
                                        --
                                        cPerFpgaVer         => (X"00000" & cFpgaRevision),
                                        others              => X"00000000"),

                                       (-- Register Init Values for Version 1 of the FPGA
                                        cHardwareCtrl       => X"0010A04A",
                                        cTriggerCtrl        => X"00010000",
--                                        cPulseGenerator     => X"00000005",
                                        cCalibrationData    => X"00000000",
                                        cAScanCtrl          => X"00000340",
                                        cSensorSetup        => X"00000000",
                                        cPingPongData       => X"00000000",
                                        cBScanTriggerCtrl   => X"00070050",
                                        cEncoder0Output     => X"00000000",
                                        cEncoder1Output     => X"00000000",
                                        cEncoder2Output     => X"00000000",
                                        cEncoder3Output     => X"00000000",
                                        cEncoder4Output     => X"00000000",
                                        cEncoder5Output     => X"00000000",
                                        cGateStartStop      => X"00000000",
                                        cGateAttributes     => X"00000000",
                                        cGateSetup          => X"00000000",
                                        cPerIoBank0         => X"00000000",
                                        cPerIoDdr0          => X"00000000",
                                        cFocusUnitCtrl      => X"00000000",
                                        cDelayValueData     => X"00000000",
                                        cPerIoBank1         => X"00000000",
                                        cPerIoDdr1          => X"00000000",
                                        --
                                        cPerFpgaVer         => (X"00001" & cFpgaRevision),
                                        others              => X"00000000"));

  -- Constant holding writable bit positions
  -- A '1' specifies that a bit is writable at a given address
  constant cRegSetWriteMask: tRegSetArray:=
                                      ((-- Register Write Mask Values for Version 0 of the FPGA
                                        cHardwareCtrl       => X"01FCFFFF",
                                        cTriggerCtrl        => X"01F1FFFF",
                                        cPulseGenerator     => X"00000FFF",
                                        cCalibrationData    => X"00003FFF",
                                        cAScanCtrl          => X"0031FFFF",
                                        cSensorSetup        => X"0000137F",
                                        cPingPongData       => X"00007FFF",
                                        cBScanTriggerCtrl   => X"7FFFFFFF",
                                        cEncoder0Output     => X"00000000",
                                        cEncoder1Output     => X"00000000",
                                        cEncoder2Output     => X"00000000",
                                        cEncoder3Output     => X"00000000",
                                        cEncoder4Output     => X"00000000",
                                        cEncoder5Output     => X"00000000",
                                        cGateStartStop      => X"FFFFFFFF",
                                        cGateAttributes     => X"FFFDF7FF",
                                        cGateSetup          => X"00000007",
                                        cPerIoBank0         => X"FFFFFFFC",
                                        cPerIoDdr0          => X"FFFFFFFC",
                                        cPerIoBank1         => X"7FFFFFFF",
                                        cPerIoDdr1          => X"7FFFFFFF",
                                        --
                                        cPerFpgaVer         => X"00000000",
                                        others              => X"00000000"),

                                       (-- Register Write Mask Values for Version 1 of the FPGA
                                        cHardwareCtrl       => X"01FCFFFF",
                                        cTriggerCtrl        => X"01F1FFFF",
                                        cCalibrationData    => X"00003FFF",
                                        cAScanCtrl          => X"0031FFFF",
                                        cSensorSetup        => X"00001F7F",
                                        cPingPongData       => X"00007FFF",
                                        cBScanTriggerCtrl   => X"7FFFFFFF",
                                        cEncoder0Output     => X"00000000",
                                        cEncoder1Output     => X"00000000",
                                        cEncoder2Output     => X"00000000",
                                        cEncoder3Output     => X"00000000",
                                        cEncoder4Output     => X"00000000",
                                        cEncoder5Output     => X"00000000",
                                        cGateStartStop      => X"FFFFFFFF",
                                        cGateAttributes     => X"FFFDF7FF",
                                        cGateSetup          => X"00000007",
                                        cPerIoBank0         => X"FFFFFFFC",
                                        cPerIoDdr0          => X"FFFFFFFC",
                                        cFocusUnitCtrl      => X"000007FF",
                                        cDelayValueData     => X"FFFFFFFF",
                                        cPerIoBank1         => X"7FFFFFFF",
                                        cPerIoDdr1          => X"7FFFFFFF",
                                        --
                                        cPerFpgaVer         => X"00000000",
                                        others              => X"00000000"));

  -- Constant holding readable bit positions
  -- A '1' specifies that a bit is readable at a given address
  constant cRegSetReadMask: tRegSetArray:=
                                      ((-- Register Read Mask Values for Version 0 of the FPGA
                                        cHardwareCtrl       => X"01FCFFFF",
                                        cTriggerCtrl        => X"01F1FFFF",
                                        cPulseGenerator     => X"00000FFF",
                                        cCalibrationData    => X"80000000",
                                        cAScanCtrl          => X"0031FFFF",
                                        cSensorSetup        => X"8000137F",
                                        cPingPongData       => X"00000000",
                                        cBScanTriggerCtrl   => X"7FFFFFFF",
                                        cEncoder0Output     => X"FFFFFFFF",
                                        cEncoder1Output     => X"FFFFFFFF",
                                        cEncoder2Output     => X"FFFFFFFF",
                                        cEncoder3Output     => X"FFFFFFFF",
                                        cEncoder4Output     => X"FFFFFFFF",
                                        cEncoder5Output     => X"FFFFFFFF",
                                        cGateStartStop      => X"FFFFFFFF",
                                        cGateAttributes     => X"FFFDF7FF",
                                        cGateSetup          => X"8000000F",
                                        cPerIoBank0         => X"FFFFFFFC",
                                        cPerIoDdr0          => X"FFFFFFFC",
                                        cPerIoBank1         => X"7FFFFFFF",
                                        cPerIoDdr1          => X"7FFFFFFF",
                                        --
                                        cPerFpgaVer         => X"0000FFFF",
                                        others              => X"00000000"),

                                       (-- Register Read Mask Values for Version 1 of the FPGA
                                        cHardwareCtrl       => X"01FCFFFF",
                                        cTriggerCtrl        => X"01F1FFFF",
                                        cCalibrationData    => X"80000000",
                                        cAScanCtrl          => X"0031FFFF",
                                        cSensorSetup        => X"80000F7F",
                                        cPingPongData       => X"00000000",
                                        cBScanTriggerCtrl   => X"7FFFFFFF",
                                        cEncoder0Output     => X"FFFFFFFF",
                                        cEncoder1Output     => X"FFFFFFFF",
                                        cEncoder2Output     => X"FFFFFFFF",
                                        cEncoder3Output     => X"00000000",
                                        cEncoder4Output     => X"00000000",
                                        cEncoder5Output     => X"00000000",
                                        cGateStartStop      => X"00000000",
                                        cGateAttributes     => X"00000000",
                                        cGateSetup          => X"8000000F",
                                        cPerIoBank0         => X"FFFFFFFC",
                                        cPerIoDdr0          => X"FFFFFFFC",
                                        cFocusUnitCtrl      => X"80000000",
                                        cDelayValueData     => X"00000000",
                                        cPerIoBank1         => X"7FFFFFFF",
                                        cPerIoDdr1          => X"7FFFFFFF",
                                        --
                                        cPerFpgaVer         => X"0000FFFF",
                                        others              => X"00000000"));

end package PeripheralFpgaPkg;
