---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: SimCtrl003.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card FPGAs
--
-- Design Description:
--Simulation Control file (003) for Digitiser card testbench
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


entity SimCtrl is
  port(ToBusModel   : out tToBusModel;
       FromBusModel : in tFromBusModel;
       ToAdcModel   : out tToAdcModel;
       FromAdcModel : in tFromAdcModel);
end entity SimCtrl;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00500000#;
  constant cSysCommandReg: integer := 16#00500014#;
  constant cSysStatusReg:  integer := 16#00500014#;

  constant cPerCheckReg:   integer := 16#00500400#;

  constant cGateStartStop:  integer := 16#00500438#;
  constant cGateAttributes: integer := 16#0050043C#;
  constant cGateSetup:      integer := 16#00500440#;

  -- Define the base of the system SRAM
  constant cSysSramBase:   integer := 16#00400000#;

  -- Define the base of the sample SRAM
  constant cSampleSramBase:   integer := 16#00000000#;


begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Doing shortened FPGA configuration to reduce simulation time"));
    writeline (OUTPUT, vLine);

    -- Program the FPGAs - actually skip full configuration simulation
    LBusWrite(cSysSramBase, 16#DEADBEEF#, ToBusModel, FromBusModel);
    LBusWrite(cSysCommandReg, 16#00000011#, ToBusModel, FromBusModel);

    -- Try to access the check register, should be delayed untill FPGAs have been configured
    LBusWrite(cSysCheckReg, 16#01234567#, ToBusModel, FromBusModel);
    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FEDCBA98# then
      write (vLine, string'("Testbench: Error - Expected 0xFEDCBA98 from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    else
      write (vLine, string'("Testbench: Shortened FPGA configuration complete"));
      writeline (OUTPUT, vLine);
    end if;

    -- Setup values for the number of samples
    LBusWrite(16#00500258#, 16#0000019F#, ToBusModel, FromBusModel);

    -- Setup value for the holdoff
--    LBusWrite(16#00500208#, 16#0000000A#, ToBusModel, FromBusModel);

    -- Select external trigger
    LBusWrite(16#00500404#, 16#00000000#, ToBusModel, FromBusModel);

    write (vLine, string'("Testbench: Test 1A (Gates 1 to 6) - +Ve Threshold - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1A (Gates 1 to 6) - Detecting Amplitude of 1st, 2nd, 3rd, 4th, last and largest peaks"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1A (Gate 7) - Bipolar - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1A (Gate 7) - Detecting Amplitude of 1st peak"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000001#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#01B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#02B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 3 (Does not exist!)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#03B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of last peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0EB4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0FB4F12E#, ToBusModel, FromBusModel);
--    LBusWrite(cGateAttributes, 16#FFC4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;


    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40091 from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC0091# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC0091 from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1900091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1900091 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#90000091# then
      write (vLine, string'("Testbench: Error - Expected 0x90000091 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1900091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1900091 from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC0091# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC0091 from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40091 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    --
    -- Setup new gate values for new test
    --
    write (vLine, string'("Testbench: Test 1A (Gate 4) - Bipolar - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1A (Gate 4) - Detecting Amplitude of 2nd peak"));
    writeline (OUTPUT, vLine);

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to be exactly the same as Gate 2 but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#01B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Disable other gates
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;


    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE0C0091# then
      write (vLine, string'("Testbench: Error - Expected 0xBE0C0091 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new gate values for new tests
    --
    write (vLine, string'("Testbench: Test 1B (Gates 1 to 7) - Bipolar - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1B (Gates 1 to 7) - Detecting Amplitude of 3rd, 4th, 5th, 6th, last and largest peaks"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#02B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#03B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 4
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#04B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 5
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#05B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 6 (Does not exist)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#06B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = Last
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0EB0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = Largest
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0FB0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Clear data available register bit
    LBusWrite(16#00500264#, 16#00000001#, ToBusModel, FromBusModel);

    -- Check bit has been cleared
    LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Data Available bit in Data Sampling Status register did not clear"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC0091# then
      write (vLine, string'("Testbench: Error - Expected 0xBE0C0091 from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BD300091# then
      write (vLine, string'("Testbench: Error - Expected 0xBD300091 from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1900091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1900091 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE700091# then
      write (vLine, string'("Testbench: Error - Expected 0xBE700091 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#90000091# then
      write (vLine, string'("Testbench: Error - Expected 0x90000091 from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE700091# then
      write (vLine, string'("Testbench: Error - Expected 0xBE700091 from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BD300091# then
      write (vLine, string'("Testbench: Error - Expected 0xBD300091 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new values for gates for new test
    --
    write (vLine, string'("Testbench: Test 2A (Gates 1 to 6) - +Ve Threshold - Trailing Flank - Test pattern 1"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2A (Gates 1 to 6) - Detecting Amplitude of 1st, 2nd, 3rd, 4th, last and largest peaks"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2A (Gates 7 to 8) - Bipolar - Trailing Flank - Test pattern 1"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2A (Gates 7 to 8) - Detecting Amplitude of 1st and 2nd peaks"));
    writeline (OUTPUT, vLine);
    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#01B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#02B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 3 (Does not exist!)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#03B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of last peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0EB4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#01B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Clear data available register bit
    LBusWrite(16#00500264#, 16#00000001#, ToBusModel, FromBusModel);

    -- Check bit has been cleared
    LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Data Available bit in Data Sampling Status register did not clear"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(1, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400A5# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400A5 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400CD from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC00CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC00CD from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B19000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB19000CD from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#900000CD# then
      write (vLine, string'("Testbench: Error - Expected 0x900000CD from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B19000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB19000CD from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC00CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC00CD from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400CD from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new gate values for new test
    --
    write (vLine, string'("Testbench: Test 2A (Gate 2) - Bipolar - Trailing Flank - Test pattern 1"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2A (Gate 2) - Detecting Amplitude of 2nd peak"));
    writeline (OUTPUT, vLine);

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to be exactly the same as Gate 2 but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#01B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Disable other gates
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(1, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE0C00CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBE0C00CD from Sample SRAM (Gate 8 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new gate values for new tests
    --
    write (vLine, string'("Testbench: Test 2B (Gates 1 to 7) - Bipolar - Trailing Flank - Test pattern 1"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2B (Gates 1 to 7) - Detecting Amplitude of 3rd, 4th, 5th, 6th, last and largest peaks"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Gate 3 but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#02B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#03B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 4
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#04B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 5
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#05B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = 6 (Does not exist)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#06B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = Last
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0EB0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate, but Bipolar, Amp peak select = Largest
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#0FB0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Clear data available register bit
    LBusWrite(16#00500264#, 16#00000001#, ToBusModel, FromBusModel);

    -- Check bit has been cleared
    LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Data Available bit in Data Sampling Status register did not clear"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(1, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400A5# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400A5 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC00CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBE0C00CD from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BD3000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBD3000CD from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B19000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xB19000CD from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE7000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBE7000CD from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#900000CD# then
      write (vLine, string'("Testbench: Error - Expected 0x900000CD from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BE7000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBE7000CD from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#BD3000CD# then
      write (vLine, string'("Testbench: Error - Expected 0xBD3000CD from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new values for gates for new test
    --
    write (vLine, string'("Testbench: Test 3 (Gates 1 to 6) - +Ve Threshold - Trailing Flank - Test pattern 0 - Distance metric on non-existant peak"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 3 (Gates 1 to 6) - Detecting Amplitude of 1st, 2nd, 3rd, 4th, last and largest peaks"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 3 (Gate 7) - Bipolar - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 3 (Gate 7) - Detecting Amplitude of 1st peak"));
    writeline (OUTPUT, vLine);
    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D0B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D1B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D2B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 3 (Does not exist!)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D3B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of last peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#DEB4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D1B4F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D0B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Clear data available register bit
    LBusWrite(16#00500264#, 16#00000001#, ToBusModel, FromBusModel);

    -- Check bit has been cleared
    LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Data Available bit in Data Sampling Status register did not clear"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1F40000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1F40000 from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A2BC0000# then
      write (vLine, string'("Testbench: Error - Expected 0xA2BC0000 from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1900000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1900000 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#80000000# then
      write (vLine, string'("Testbench: Error - Expected 0x80000000 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1900000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1900000 from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A2BC0000# then
      write (vLine, string'("Testbench: Error - Expected 0xA2BC0000 from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1F40000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1F40000 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    --
    -- Setup new gate values for new test
    --
    write (vLine, string'("Testbench: Test 3 (Gate 7) - Bipolar - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 3 (Gate 7) - Detecting Amplitude of 2nd peak"));
    writeline (OUTPUT, vLine);

    -- Disable other gates
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;


    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to be exactly the same as Gate 2 but Bipolar polarity
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D1B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AE0C0000# then
      write (vLine, string'("Testbench: Error - Expected 0xAE0C0000 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;



    --
    -- Setup new values for gates for new test
    --
    write (vLine, string'("Testbench: Test 4 (Gates 1 to 7) - -Ve Threshold - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 4 (Gates 1 to 7) - Detecting Amplitude of 1st, 2nd, 3rd, 4th, last and largest peaks"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D0B8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D1B8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D2B8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of peak 3 (Does not exist!)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D3B8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of last peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#DEB8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but amplitute of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#D1B8F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Disable unused gates
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;


    -- Clear data available register bit
    LBusWrite(16#00500264#, 16#00000001#, ToBusModel, FromBusModel);

    -- Check bit has been cleared
    LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000000# then
      write (vLine, string'("Testbench: Error - Data Available bit in Data Sampling Status register did not clear"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AE0C0000# then
      write (vLine, string'("Testbench: Error - Expected 0xAE0C0000 from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AD300000# then
      write (vLine, string'("Testbench: Error - Expected 0xAD300000 from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AE700000# then
      write (vLine, string'("Testbench: Error - Expected 0xAE700000 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#80000000# then
      write (vLine, string'("Testbench: Error - Expected 0x80000000 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AE700000# then
      write (vLine, string'("Testbench: Error - Expected 0xAE700000 from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AD300000# then
      write (vLine, string'("Testbench: Error - Expected 0xAD300000 from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;