---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: OutPort32.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card
--
-- Design Description:
-- picoBlaze 32bit output port
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity OutPort32 is
  generic(
    gRstVal  : in  std_logic_vector(31 downto 0) := (others => '0'));
  port(
    pClock   : in  std_ulogic;
    pnReset  : in  std_ulogic;
    pWE      : in  std_ulogic;
    pDataIn  : in  std_logic_vector(7 downto 0);
    pPAD     : in  std_logic_vector(7 downto 0);
    pDataOut : out std_logic_vector(31 downto 0);
    pSyncSet : in  std_logic_vector(31 downto 0));
end OutPort32;

architecture RTL of OutPort32 is

  constant cBE0     : std_logic_vector(7 downto 0) := x"10";
  constant cBE1     : std_logic_vector(7 downto 0) := x"11";
  constant cBE2     : std_logic_vector(7 downto 0) := x"12";
  constant cBE3     : std_logic_vector(7 downto 0) := x"13";
  constant cBE0Mask : std_logic_vector(7 downto 0) := x"14";

  signal DataBuffer : std_logic_vector (31 downto 0);

begin

  pDataOut <= DataBuffer;

  process (pClock, pnReset)
  begin
    if pnReset = '0' then
      DataBuffer <= gRstVal;
    elsif rising_edge(pClock) then
      if pWE = '1' then
        case pPAD is
          when cBE0     => DataBuffer(7 downto 0)   <= pDataIn;
          when cBE1     => DataBuffer(15 downto 8)  <= pDataIn;
          when cBE2     => DataBuffer(23 downto 16) <= pDataIn;
          when cBE3     => DataBuffer(31 downto 24) <= pDataIn;
          when cBE0Mask => DataBuffer(7 downto 3)   <= pDataIn(7 downto 3);
                           DataBuffer(0)            <= pDataIn(0);
          when others =>
            null;
        end case;
      end if;
      for count in 0 to 31 loop
        if pSyncSet(Count) = '1' then
          DataBuffer(Count) <= '1';
        end if;
      end loop;
    end if;
  end process;

end architecture RTL;
