---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: InPort32.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- 32bit input port
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity InPort32 is
  generic(
	gBase    : std_logic_vector(7 downto 0) := x"20");
  port(
    pClock   : in  std_ulogic;
    pnReset  : in  std_ulogic;
    pnWE     : in  std_ulogic;
    pPAD     : in  std_logic_vector(7 downto 0);
    pDataIn  : in  std_logic_vector(31 downto 0);
    pDataOut : out std_logic_vector(31 downto 0);
    pDOut8   : out std_logic_vector(7 downto 0);
    pSyncClr : in  std_logic_vector(31 downto 0));
end InPort32;

architecture RTL of InPort32 is

  constant cBE0 : std_logic_vector(1 downto 0) := "00";
  constant cBE1 : std_logic_vector(1 downto 0) := "01";
  constant cBE2 : std_logic_vector(1 downto 0) := "10";
  constant cBE3 : std_logic_vector(1 downto 0) := "11";

  signal DataBuffer : std_logic_vector(31 downto 0);

begin

  DBuf: process (pClock, pnReset)
  begin
    if pnReset = '0' then
      DataBuffer <= (others => '0');
    elsif rising_edge(pClock) then
      if pnWE = '0' then
        DataBuffer <= pDataIn;
      end if;
      for count in 0 to 31 loop
        if pSyncClr(Count) = '1' then
          DataBuffer(Count) <= '0';
        end if;
      end loop;
    end if;
  end process DBuf;

  DMux: process (pPAD, DataBuffer)
  begin
    if (pPAD(7 downto 2) = gBase(7 downto 2) ) then
        case pPAD(1 downto 0) is
          when cBE0   => pDOut8 <= DataBuffer(7 downto 0);
          when cBE1   => pDOut8 <= DataBuffer(15 downto 8);
          when cBE2   => pDOut8 <= DataBuffer(23 downto 16);
          when cBE3   => pDOut8 <= DataBuffer(31 downto 24);
          when others => pDOut8 <= (others => '0');
        end case;
    else
  	  pDOut8 <= (others => '0');
    end if;
  end process DMux;

  pDataOut <= DataBuffer;

end architecture RTL;

