---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: TapDelay.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- This module generates a 32 bit tap delay register used by the
-- CalControl module to find out the phase transitions.
---------------------------------------------------------------------------

library ieee;
library UNISIM;
use ieee.std_logic_1164.all;
use UNISIM.VCOMPONENTS.all;


entity TapDelay is
  port (Clk   : in  std_logic;
        Reset : in  std_logic;
        TapIn : in  std_logic;
        Flop2 : out std_logic_vector(31 downto 0));
end TapDelay;

architecture Str of TapDelay is

  signal Tap        : std_logic_vector(31 downto 0);
  signal Flop1      : std_logic_vector(31 downto 0);
  signal Flop2XNor  : std_logic_vector(30 downto 0);

  attribute syn_preserve : boolean;

  attribute syn_preserve of Tap   : signal is true;
  attribute syn_preserve of Flop1 : signal is true;    


begin

  l0 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => TapIn,
              I2 => '0',
              I3 => '1',
              O  => Tap(0));

  l1 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(0),
              I2 => '0',
              I3 => '1',
              O  => Tap(1));

  l2 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(1),
              I2 => '0',
              I3 => '1',
              O  => Tap(2));

  l3 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(2),
              I2 => '0',
              I3 => '1',
              O  => Tap(3));

  l4 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(3),
              I2 => '0',
              I3 => '1',
              O  => Tap(4));

  l5 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(4),
              I2 => '0',
              I3 => '1',
              O  => Tap(5));

  l6 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(5),
              I2 => '0',
              I3 => '1',
              O  => Tap(6));

  l7 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(6),
              I2 => '0',
              I3 => '1',
              O  => Tap(7));

  l8 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(7),
              I2 => '0',
              I3 => '1',
              O  => Tap(8));

  l9 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(8),
              I2 => '0',
              I3 => '1',
              O  => Tap(9));

  l10 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(9),
              I2 => '0',
              I3 => '1',
              O  => Tap(10));

  l11 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(10),
              I2 => '0',
              I3 => '1',
              O  => Tap(11));

  l12 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(11),
              I2 => '0',
              I3 => '1',
              O  => Tap(12));

  l13 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(12),
              I2 => '0',
              I3 => '1',
              O  => Tap(13));

  l14 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(13),
              I2 => '0',
              I3 => '1',
              O  => Tap(14));

  l15 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(14),
              I2 => '0',
              I3 => '1',
              O  => Tap(15));

  l16 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(15),
              I2 => '0',
              I3 => '1',
              O  => Tap(16));

  l17 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(16),
              I2 => '0',
              I3 => '1',
              O  => Tap(17));

  l18 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(17),
              I2 => '0',
              I3 => '1',
              O  => Tap(18));

  l19 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(18),
              I2 => '0',
              I3 => '1',
              O  => Tap(19));

  l20 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(19),
              I2 => '0',
              I3 => '1',
              O  => Tap(20));

  l21 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(20),
              I2 => '0',
              I3 => '1',
              O  => Tap(21));

  l22 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(21),
              I2 => '0',
              I3 => '1',
              O  => Tap(22));

  l23 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(22),
              I2 => '0',
              I3 => '1',
              O  => Tap(23));

  l24 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(23),
              I2 => '0',
              I3 => '1',
              O  => Tap(24));

  l25 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(24),
              I2 => '0',
              I3 => '1',
              O  => Tap(25));

  l26 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(25),
              I2 => '0',
              I3 => '1',
              O  => Tap(26));

  l27 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(26),
              I2 => '0',
              I3 => '1',
              O  => Tap(27));

  l28 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(27),
              I2 => '0',
              I3 => '1',
              O  => Tap(28));

  l29 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(28),
              I2 => '0',
              I3 => '1',
              O  => Tap(29));

  l30 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(29),
              I2 => '0',
              I3 => '1',
              O  => Tap(30));

  l31 : LUT4 generic map (INIT => x"e2e2")
    port map (I0 => '1',
              I1 => Tap(30),
              I2 => '0',
              I3 => '1',
              O  => Tap(31));

  GenTap1: for i in 0 to 31 generate
    r: FDR
      port map (Q => Flop1(i),
                C => Clk,
                D => Tap(i),
                R => Reset);
  end generate;
  
  GenAsgn: for i in 0 to 30 generate
    Flop2XNor(i)  <= Flop1(i) xnor Flop1(i+1);
  end generate;

  GenTap2: for i in 0 to 30 generate
    u: FDR
      port map (Q => Flop2(i),
                C => Clk,
                D => Flop2XNor(i),
                R => Reset);
  end generate;
  
  u31: FDR
    port map (Q => Flop2(31),
              C => Clk,
              D => Flop1(31),
              R => Reset);

end Str;
