---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DPBRAM32x256.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card
--
-- Design Description:
-- 32 bit x 256 word Dual Port Block Ram ( Spartan-II / IIE )
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity DPBRAM32x256 is
  port(
    pnReset  : in  std_ulogic;
    pClock   : in  std_ulogic;
    AddressA : in  std_logic_vector(7 downto 0);
    AddressB : in  std_logic_vector(7 downto 0);
    DataInA  : in  std_logic_vector(31 downto 0);
    DataInB  : in  std_logic_vector(31 downto 0);
    WriteEnA : in  std_ulogic;
    WriteEnB : in  std_ulogic;
    DataOutA : out std_logic_vector(31 downto 0);
    DataOutB : out std_logic_vector(31 downto 0)); 
end DPBRAM32x256;

architecture RTL of DPBRAM32x256 is

  signal Reset : std_ulogic;

begin

  Reset <= not pnReset;

  RAMB4_S16_S16_High : RAMB4_S16_S16
    port map (
      DOA   => DataOutA(31 downto 16),  -- Port A 16-bit data output
      DOB   => DataOutB(31 downto 16),  -- Port B 16-bit data output
      ADDRA => AddressA,                -- Port A 8-bit address input
      ADDRB => AddressB,                -- Port B 8-bit address input
      CLKA  => pClock,                  -- Port A clock input
      CLKB  => pClock,                  -- Port B clock input
      DIA   => DataInA(31 downto 16),   -- Port A 16-bit data input
      DIB   => DataInB(31 downto 16),   -- Port B 16-bit data input
      ENA   => '1',                     -- Port A RAM enable input
      ENB   => '1',                     -- Port B RAM enable input
      RSTA  => Reset,                   -- Port A Synchronous reset input
      RSTB  => Reset,                   -- Port B Synchronous reset input
      WEA   => WriteEnA,                -- Port A RAM write enable input
      WEB   => WriteEnB                 -- Port B RAM write enable input
      );

  RAMB4_S16_S16_Low : RAMB4_S16_S16
    port map (
      DOA   => DataOutA(15 downto 0),   -- Port A 16-bit data output
      DOB   => DataOutB(15 downto 0),   -- Port B 16-bit data output
      ADDRA => AddressA,                -- Port A 8-bit address input
      ADDRB => AddressB,                -- Port B 8-bit address input
      CLKA  => pClock,                  -- Port A clock input
      CLKB  => pClock,                  -- Port B clock input
      DIA   => DataInA(15 downto 0),    -- Port A 16-bit data input
      DIB   => DataInB(15 downto 0),    -- Port B 16-bit data input
      ENA   => '1',                     -- Port A RAM enable input
      ENB   => '1',                     -- Port B RAM enable input
      RSTA  => Reset,                   -- Port A Synchronous reset input
      RSTB  => Reset,                   -- Port B Synchronous reset input
      WEA   => WriteEnA,                -- Port A RAM write enable input
      WEB   => WriteEnB                 -- Port B RAM write enable input
      );

end architecture RTL;

