---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DAC7612Model.vhd
-- Language: VHDL '93
-- Project:  PRx Card Control FPGA
--
-- Design Description:
-- DAC Model
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

entity AD5399Model is
  port(pDacClk     : in std_ulogic;
       pDacnCs     : in std_ulogic;
       pDacSdi     : in std_ulogic;
       pDacDataA   : out std_logic_vector(11 downto 0);
       pDacDataB   : out std_logic_vector(11 downto 0));
end entity AD5399Model;



architecture beh of AD5399Model is
begin

  State : process
    variable A: std_logic_vector(3 downto 0);
    variable D: std_logic_vector(11 downto 0);
    variable  Count: integer;
  begin
    wait on pDacClk, pDacnCs;

    if rising_edge(pDacClk) then
      if (pDacnCs = '0') then
        A := A(2 downto 0) & D(11);
        D := D(10 downto 0) & pDacSdi;
        Count := Count + 1;
        if (Count = 16) then
          if (A(3) = '0') then
            pDacDataA <= D;
          end if;
          if (A(3) = '1') then
            pDacDataB <= D;
          end if;
        end if;
      end if;
    end if;

    if falling_edge(pDacnCs) then
      Count := 0;
    end if;

  end process State;    

end architecture beh;