---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SimCtr.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card FPGAs
--
-- Design Description:
-- Simulation Control entity common to multiple architectures
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;

entity SimCtrl is
  port(ToBusModel    : out tToBusModel;
       FromBusModel  : in  tFromBusModel;
       pHVCtrl       : in  std_logic_vector(11 downto 0);
       pTCGVal       : in  std_logic_vector(11 downto 0);
       pTrigger      : out std_ulogic;
       pTriggerIn    : in  std_ulogic;
       pAck          : in  std_ulogic;
       pHighVoltageOK: out std_ulogic;
       pFineDelay    : in  std_logic_vector(7 downto 0));
end entity SimCtrl;
