---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SimCtrl003.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card FPGAs
--
-- Design Description:
-- Simulation Control file (003) for pulse receive card testbench
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCommandReg:       integer := 16#00500014#;
  constant cSysStatusReg:        integer := 16#00500014#;

  -- Define the base of the system SRAM
  constant cSysSramBase:         integer := 16#00400000#;

  constant cSysGlobalConfigReg:  integer := 16#005000f0#;
  constant cSysSeqTableBase:     integer := 16#00700000#;

begin

  -- Main Simulation Control process
  Main: process
    variable vAddr: integer;
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    pHighVoltageOK <= '0';
    pTrigger <= '0';

    -- Initialise the Bus Model (bus clock = 33 MHz)
    BusInit(30 ns, ToBusModel, FromBusModel);

    write (vLine, string'("Testbench: Testing Overload function"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;
    -- set up some realistic values sequence table
    LBusWrite(cSysSeqTableBase,     16#80000001#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+1*4, 16#00000555#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+2*4, 16#02031020#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+3*4, 16#00000308#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+4*4, 16#00000033#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+5*4, 16#00001000#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+7*4, 10000, ToBusModel, FromBusModel);
    -- 2nd entry
    LBusWrite(cSysSeqTableBase+8*4, 16#80010002#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+9*4, 16#00000444#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+10*4, 16#02031020#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+11*4, 16#00000204#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+12*4, 16#00000022#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+13*4, 16#00002000#, ToBusModel, FromBusModel);
    LBusWrite(cSysSeqTableBase+15*4, 10000, ToBusModel, FromBusModel);

    -- 3rd entry disabled
    LBusWrite(cSysSeqTableBase+16*4, 16#00000000#, ToBusModel, FromBusModel);

    wait for 100 ns;

    -- set Global configuration register - internal trigger
    LBusWrite(cSysGlobalConfigReg, 16#55008E00#, ToBusModel, FromBusModel);


    -- send global configuration and sequence table over serial link to control FPGA
    LBusWrite(cSysCommandReg, 16#00000008#, ToBusModel, FromBusModel);

    wait until rising_edge(pTriggerIn);

    LBusRead(cSysStatusReg, vRData, ToBusModel, FromBusModel);
    if (conv_std_logic_vector(vRData, 32) and X"00000010") /= X"00000000" then
      write (vLine, string'("Testbench: Error - Expected 0 from Overload Status Read"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    wait until falling_edge(pTriggerIn);
    wait for 20 us;

    LBusRead(cSysStatusReg, vRData, ToBusModel, FromBusModel);
    if (conv_std_logic_vector(vRData, 32) and X"00000010") /= X"00000010" then
      write (vLine, string'("Testbench: Error - Expected 1 from Overload Status Read"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- clear overload flag
    LBusWrite(cSysCommandReg, 16#00000010#, ToBusModel, FromBusModel);

    wait for 20 us;

    LBusRead(cSysStatusReg, vRData, ToBusModel, FromBusModel);
    if (conv_std_logic_vector(vRData, 32) and X"00000010") /= X"00000000" then
      write (vLine, string'("Testbench: Error - Expected 0 from Overload Status Read"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;


    wait for 100 ns;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation 006 completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation 006 completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;