---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DataMux.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Data Multiplexer for Pulser Receiver Card (PRx) System FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity DataMux is
  port(
    pDataIn0 : in  std_logic_vector(31 downto 0);
    pDataIn1 : in  std_logic_vector(31 downto 0);
    pDataIn2 : in  std_logic_vector(31 downto 0);
    pDataIn3 : in  std_logic_vector(31 downto 0);
    pDataIn4 : in  std_logic_vector(31 downto 0);
    pDataIn5 : in  std_logic_vector(31 downto 0);
    pDataIn6 : in  std_logic_vector(31 downto 0);
    pDataIn7 : in  std_logic_vector(31 downto 0);
    pDataIn8 : in  std_logic_vector(31 downto 0);
    pDataIn9 : in  std_logic_vector(31 downto 0);
    pDSEL0   : in  std_logic;
    pDSEL1   : in  std_logic;
    pDSEL2   : in  std_logic;
    pDSEL3   : in  std_logic;
    pDSEL4   : in  std_logic;
    pDSEL5   : in  std_logic;
    pDSEL6   : in  std_logic;
    pDSEL7   : in  std_logic;
    pDSEL8   : in  std_logic;
    pDSEL9   : in  std_logic;
    pDataOut : out std_logic_vector(31 downto 0));
end DataMux;

architecture RTL of DataMux is

begin

  pDataOut <= pDataIn0 when pDSEL0 = '0' else
  			      pDataIn1 when pDSEL1 = '0' else
  			      pDataIn2 when pDSEL2 = '0' else
  			      pDataIn3 when pDSEL3 = '0' else
  			      pDataIn4 when pDSEL4 = '0' else
  			      pDataIn5 when pDSEL5 = '0' else
  			      pDataIn6 when pDSEL6 = '0' else
  			      pDataIn7 when pDSEL7 = '0' else
  			      pDataIn8 when pDSEL8 = '0' else
  			      pDataIn9;

end architecture RTL;

