Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,943 out of  4,704   62%
  Number of 4 input LUTs:         3,228 out of  4,704   68%
  Number of Slice Flip Flops:     2,711 out of  4,704   57%
  Number of 4 input LUTs:         2,959 out of  4,704   62%
  Number of Slice Flip Flops:     2,779 out of  4,704   59%
  Number of 4 input LUTs:         2,949 out of  4,704   62%
  Number of Slice Flip Flops:     2,718 out of  4,704   57%
  Number of 4 input LUTs:         2,959 out of  4,704   62%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,241 out of  2,350   95%
    Number of Slices containing unrelated logic:       109 out of  2,350    4%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,090 out of  4,704   65%
      Number used as logic:                     2,959
      Number used as a route-thru:                118
      Number used as Shift registers:              13
   Number of bonded IOBs:           267 out of    284   94%
      IOB Flip Flops:                              92
   Number of Tbufs:                 396 out of  2,464   16%
   Number of Block RAMs:             11 out of     14   78%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   Number of DLLs:                    1 out of      4   25%

##
## 27-May-2004
## Fixed small sample dropping bug in gates
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,922 out of  4,704   62%
  Number of 4 input LUTs:         3,109 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,111 out of  2,350   89%
    Number of Slices containing unrelated logic:       239 out of  2,350   10%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,221 out of  4,704   68%
      Number used as logic:                     3,109
      Number used as a route-thru:                112
   Number of bonded IOBs:           267 out of    284   94%
      IOB Flip Flops:                              92
   Number of Tbufs:                 396 out of  2,464   16%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%


##
## 27-May-2004
## Using low skew lines, not primary clock lines for high fanout signals
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,948 out of  4,704   62%
  Number of 4 input LUTs:         3,179 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,051 out of  2,350   87%
    Number of Slices containing unrelated logic:       299 out of  2,350   12%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,284 out of  4,704   69%
      Number used as logic:                     3,179
      Number used as a route-thru:                105
   Number of bonded IOBs:           267 out of    284   94%
      IOB Flip Flops:                              92
   Number of Tbufs:                 396 out of  2,464   16%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%


##
## 26-May-2004
## TriggerDelay moved to Peripheral FPGA
## Updated (fixed?!) DDS Access
## 
##
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,998 out of  4,704   63%
  Number of 4 input LUTs:         3,192 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,987 out of  2,350   84%
    Number of Slices containing unrelated logic:       363 out of  2,350   15%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,297 out of  4,704   70%
      Number used as logic:                     3,192
      Number used as a route-thru:                105
   Number of bonded IOBs:           267 out of    284   94%
      IOB Flip Flops:                              92
   Number of Tbufs:                 396 out of  2,464   16%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.232ns   | 4    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------
#
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,998 out of  4,704   63%
  Number of 4 input LUTs:         3,192 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,988 out of  2,350   84%
    Number of Slices containing unrelated logic:       362 out of  2,350   15%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,297 out of  4,704   70%
      Number used as logic:                     3,192
      Number used as a route-thru:                105
   Number of bonded IOBs:           267 out of    284   94%
      IOB Flip Flops:                              92
   Number of Tbufs:                 396 out of  2,464   16%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.613ns   | 7    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------



##
## 20-May-2004
## Slight fixes to SramWriteCtrl state machine
##
##
All constraints were met.
##
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,966 out of  4,704   63%
  Number of 4 input LUTs:         3,115 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,056 out of  2,350   87%
    Number of Slices containing unrelated logic:       294 out of  2,350   12%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,215 out of  4,704   68%
      Number used as logic:                     3,115
      Number used as a route-thru:                100
   Number of bonded IOBs:           266 out of    284   93%
      IOB Flip Flops:                             105
   Number of Tbufs:                 377 out of  2,464   15%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%


##
## 19-May-2004
## Modified encoder data writing + some SramWriteCtrl fixes
##
All constraints were met.
##
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,966 out of  4,704   63%
  Number of 4 input LUTs:         3,120 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,054 out of  2,350   87%
    Number of Slices containing unrelated logic:       296 out of  2,350   12%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,220 out of  4,704   68%
      Number used as logic:                     3,120
      Number used as a route-thru:                100
   Number of bonded IOBs:           266 out of    284   93%
      IOB Flip Flops:                             105
   Number of Tbufs:                 377 out of  2,464   15%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

##
## Timings for -5 part
##   
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.864ns   | 4    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------


##
## 18-May-2004
## Build with 8 gates, sample dropping and 8-bit A-Scan data mode
## Gate registers in DSP FPGA
##
All constraints were met.
##
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     3,108 out of  4,704   66%
  Number of 4 input LUTs:         3,307 out of  4,704   70%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,970 out of  2,350   83%
    Number of Slices containing unrelated logic:       380 out of  2,350   16%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,420 out of  4,704   72%
      Number used as logic:                     3,307
      Number used as a route-thru:                113
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                             107
   Number of Tbufs:                 442 out of  2,464   17%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

##
## Timings for -5 part
##
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.371ns   | 6    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------

##
## Moving Gate registers to Peripheral FPGA and bringing the data across in a
## serial datastream.
##
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,964 out of  4,704   63%
  Number of 4 input LUTs:         3,123 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,129 out of  2,350   90%
    Number of Slices containing unrelated logic:       221 out of  2,350    9%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,241 out of  4,704   68%
      Number used as logic:                     3,123
      Number used as a route-thru:                118
   Number of bonded IOBs:           264 out of    284   92%
      IOB Flip Flops:                             105
   Number of Tbufs:                 375 out of  2,464   15%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%












##
## 24-Mar-2004
## First build with test mode included + DDS access fixed
##
   Design Summary:
	 Number of errors:      0
	 Number of warnings:    0
	 Logic Utilization:
	   Number of Slice Flip Flops:       451 out of  4,704    9%
	   Number of 4 input LUTs:         1,416 out of  4,704   30%
	 Logic Distribution:
	     Number of occupied Slices:                         904 out of  2,352   38%
	     Number of Slices containing only related logic:    904 out of    904  100%
	     Number of Slices containing unrelated logic:         0 out of    904    0%
	         *See NOTES below for an explanation of the effects of unrelated logic
	 Total Number 4 input LUTs:        1,466 out of  4,704   31%
	       Number used as logic:                     1,416
	       Number used as a route-thru:                 50
	    Number of bonded IOBs:           236 out of    284   83%
	       IOB Flip Flops:                             104
	    Number of GCLKs:                   2 out of      4   50%
	    Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       451 out of  4,704    9%
  Number of 4 input LUTs:         1,416 out of  4,704   30%
Logic Distribution:
    Number of occupied Slices:                         904 out of  2,352   38%
    Number of Slices containing only related logic:    904 out of    904  100%
    Number of Slices containing unrelated logic:         0 out of    904    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,466 out of  4,704   31%
      Number used as logic:                     1,416
      Number used as a route-thru:                 50
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                             104
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
   
##
## 25-Mar-2004
## First build with 4 stage pipeline for Sampling RAM access
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       474 out of  4,704   10%
  Number of 4 input LUTs:         1,413 out of  4,704   30%
Logic Distribution:
    Number of occupied Slices:                         910 out of  2,352   38%
    Number of Slices containing only related logic:    910 out of    910  100%
    Number of Slices containing unrelated logic:         0 out of    910    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,463 out of  4,704   31%
      Number used as logic:                     1,413
      Number used as a route-thru:                 50
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                             168
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   

##
## 25-Mar-2004
## Using TBUFs for SramSwitching MUXing
## Idea dropped as it messed up timings
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       485 out of  4,704   10%
  Number of 4 input LUTs:         1,280 out of  4,704   27%
Logic Distribution:
    Number of occupied Slices:                         861 out of  2,352   36%
    Number of Slices containing only related logic:    861 out of    861  100%
    Number of Slices containing unrelated logic:         0 out of    861    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,358 out of  4,704   28%
      Number used as logic:                     1,280
      Number used as a route-thru:                 78
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                             168
   Number of Tbufs:                 292 out of  2,464   11%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   

##
## 25-Mar-2004
## Sample RAM reads have wait state (nREADY=1) reads cycles.
## Start delay and No of samples registers and functions implemented.
## Data available register implemented.
##      
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       524 out of  4,704   11%
  Number of 4 input LUTs:         1,488 out of  4,704   31%
Logic Distribution:
    Number of occupied Slices:                         983 out of  2,352   41%
    Number of Slices containing only related logic:    983 out of    983  100%
    Number of Slices containing unrelated logic:         0 out of    983    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,584 out of  4,704   33%
      Number used as logic:                     1,488
      Number used as a route-thru:                 96
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                             105
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

##
## 29-Mar-2004
## Tristate buffers used to read register MUXing (saves nearly 1000 LUTs)
## Support for multiple scan data in each sample SRAM bank.
## Critical timing areas re-coded, now not a problem.
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       635 out of  4,704   13%
  Number of 4 input LUTs:           533 out of  4,704   11%
Logic Distribution:
    Number of occupied Slices:                         529 out of  2,352   22%
    Number of Slices containing only related logic:    529 out of    529  100%
    Number of Slices containing unrelated logic:         0 out of    529    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          606 out of  4,704   12%
      Number used as logic:                       533
      Number used as a route-thru:                 73
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              73
   Number of Tbufs:                 304 out of  2,464   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
##
## 30-Mar-2004
## Moved over to new SRAM bank switching scheme.
## Added bits 1 and 2 to DataSamplingStatus register
## Added index word write to the start of every A-scan data block in sample SRAM
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       688 out of  4,704   14%
  Number of 4 input LUTs:           590 out of  4,704   12%
Logic Distribution:
    Number of occupied Slices:                         575 out of  2,352   24%
    Number of Slices containing only related logic:    575 out of    575  100%
    Number of Slices containing unrelated logic:         0 out of    575    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          676 out of  4,704   14%
      Number used as logic:                       590
      Number used as a route-thru:                 86
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              73
   Number of Tbufs:                 306 out of  2,464   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
##
## 01-Apr-2004
## Fixed full wave rectification bug.
## Fixed sample ordering wrong 50% of the time bug.
## Added 'trigger is active' LED.
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       715 out of  4,704   15%
  Number of 4 input LUTs:           628 out of  4,704   13%
Logic Distribution:
    Number of occupied Slices:                         596 out of  2,352   25%
    Number of Slices containing only related logic:    596 out of    596  100%
    Number of Slices containing unrelated logic:         0 out of    596    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          713 out of  4,704   15%
      Number used as logic:                       628
      Number used as a route-thru:                 85
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              73
   Number of Tbufs:                 305 out of  2,464   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
##
## 01-Apr-2004
## Initial build with interface gate - data being read back through a debug register
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:       789 out of  4,704   16%
  Number of 4 input LUTs:           695 out of  4,704   14%
Logic Distribution:
    Number of occupied Slices:                         666 out of  2,352   28%
    Number of Slices containing only related logic:    666 out of    666  100%
    Number of Slices containing unrelated logic:         0 out of    666    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          781 out of  4,704   16%
      Number used as logic:                       695
      Number used as a route-thru:                 86
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              73
   Number of Tbufs:                 337 out of  2,464   13%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%



Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,323 out of  4,704   28%
  Number of 4 input LUTs:         1,120 out of  4,704   23%
Logic Distribution:
    Number of occupied Slices:                       1,121 out of  2,352   47%
    Number of Slices containing only related logic:  1,121 out of  1,121  100%
    Number of Slices containing unrelated logic:         0 out of  1,121    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,217 out of  4,704   25%
      Number used as logic:                     1,120
      Number used as a route-thru:                 97
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,054 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.215ns   | 5    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,326 out of  4,704   28%
  Number of 4 input LUTs:         1,165 out of  4,704   24%
Logic Distribution:
    Number of occupied Slices:                       1,147 out of  2,352   48%
    Number of Slices containing only related logic:  1,147 out of  1,147  100%
    Number of Slices containing unrelated logic:         0 out of  1,147    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,258 out of  4,704   26%
      Number used as logic:                     1,165
      Number used as a route-thru:                 93
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,086 out of  2,464   44%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 12.883ns   | 10   
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------



##
## Build with Interface gate and 1 partial gate included
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,351 out of  4,704   28%
  Number of 4 input LUTs:         1,170 out of  4,704   24%
Logic Distribution:
    Number of occupied Slices:                       1,158 out of  2,352   49%
    Number of Slices containing only related logic:  1,158 out of  1,158  100%
    Number of Slices containing unrelated logic:         0 out of  1,158    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,295 out of  4,704   27%
      Number used as logic:                     1,170
      Number used as a route-thru:                125
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
All constraints were met.
   
##
## Build with Interface gate and 2 partial gates included
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,407 out of  4,704   29%
  Number of 4 input LUTs:         1,280 out of  4,704   27%
Logic Distribution:
    Number of occupied Slices:                       1,235 out of  2,352   52%
    Number of Slices containing only related logic:  1,235 out of  1,235  100%
    Number of Slices containing unrelated logic:         0 out of  1,235    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,408 out of  4,704   29%
      Number used as logic:                     1,280
      Number used as a route-thru:                128
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,421 out of  4,704   30%
  Number of 4 input LUTs:         1,322 out of  4,704   28%
Logic Distribution:
    Number of occupied Slices:                       1,246 out of  2,352   52%
    Number of Slices containing only related logic:  1,246 out of  1,246  100%
    Number of Slices containing unrelated logic:         0 out of  1,246    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,451 out of  4,704   30%
      Number used as logic:                     1,322
      Number used as a route-thru:                129
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   

##
## All 10 gates - no where near complete yet!  Without pipelining enabled
##   
--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 14.707ns   | 5    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------
* NET "pLCLK_BUFGP/IBUFG" PERIOD =  15 nS   | 15.000ns   | 15.449ns   | 4    
   HIGH 50.000000 %                         |            |            |      
--------------------------------------------------------------------------------
* TS_Fe2xClk2SramADat = MAXDELAY FROM TIMEG | 11.000ns   | 11.428ns   | 2    
  RP "ADC_2xClk_FE" TO TIMEGRP  "PADS(pSram |            |            |      
  A_Data*)" 11 nS                           |            |            |      
--------------------------------------------------------------------------------
* TS_FpgaCs2LD = MAXDELAY FROM TIMEGRP "PAD | 13.000ns   | 13.954ns   | 3    
  S(pnFpgaCs)" TO TIMEGRP "PADS(pLD*)"  13  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------

##
## All 10 gates - no where near complete yet!  With pipelining enabled
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,916 out of  4,704   40%
  Number of 4 input LUTs:         2,537 out of  4,704   53%
Logic Distribution:
    Number of occupied Slices:                       2,052 out of  2,352   87%
    Number of Slices containing only related logic:  2,052 out of  2,052  100%
    Number of Slices containing unrelated logic:         0 out of  2,052    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,706 out of  4,704   57%
      Number used as logic:                     2,537
      Number used as a route-thru:                169
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 14.535ns   | 12   
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------
* TS_Fe2xClk2SramAAdd = MAXDELAY FROM TIMEG | 11.000ns   | 11.098ns   | 2    
  RP "ADC_2xClk_FE" TO TIMEGRP  "PADS(pSram |            |            |      
  A_Addr*)" 11 nS                           |            |            |      
--------------------------------------------------------------------------------
* TS_Fe2xClk2SramADat = MAXDELAY FROM TIMEG | 11.000ns   | 11.374ns   | 2    
  RP "ADC_2xClk_FE" TO TIMEGRP  "PADS(pSram |            |            |      
  A_Data*)" 11 nS                           |            |            |      
--------------------------------------------------------------------------------
* TS_FpgaCs2LD = MAXDELAY FROM TIMEGRP "PAD | 13.000ns   | 13.733ns   | 3    
  S(pnFpgaCs)" TO TIMEGRP "PADS(pLD*)"  13  |            |            |      
  nS                                        |            |            |      
--------------------------------------------------------------------------------

##
## All 10 gates, TBUFs to MUX triggers onto Trigger in Gate
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,860 out of  4,704   39%
  Number of 4 input LUTs:         2,198 out of  4,704   46%
Logic Distribution:
    Number of occupied Slices:                       1,856 out of  2,352   78%
    Number of Slices containing only related logic:  1,856 out of  1,856  100%
    Number of Slices containing unrelated logic:         0 out of  1,856    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,358 out of  4,704   50%
      Number used as logic:                     2,198
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,145 out of  2,464   46%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 14.468ns   | 5    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------
* NET "pLCLK_BUFGP/IBUFG" PERIOD =  15 nS   | 15.000ns   | 16.425ns   | 4    
   HIGH 50.000000 %                         |            |            |      
--------------------------------------------------------------------------------
* TS_Fe2xClk2SramADat = MAXDELAY FROM TIMEG | 11.000ns   | 11.723ns   | 2    
  RP "ADC_2xClk_FE" TO TIMEGRP  "PADS(pSram |            |            |      
  A_Data*)" 11 nS                           |            |            |      
--------------------------------------------------------------------------------




--------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic 
                                            |            |            | Levels
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.122ns   | 7    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------
* TS_Fe2xClk2SramADat = MAXDELAY FROM TIMEG | 11.000ns   | 11.059ns   | 2    
  RP "ADC_2xClk_FE" TO TIMEGRP  "PADS(pSram |            |            |      
  A_Data*)" 11 nS                           |            |            |      
--------------------------------------------------------------------------------



Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,921 out of  4,704   40%
  Number of 4 input LUTs:         2,199 out of  4,704   46%
Logic Distribution:
    Number of occupied Slices:                       1,893 out of  2,352   80%
    Number of Slices containing only related logic:  1,893 out of  1,893  100%
    Number of Slices containing unrelated logic:         0 out of  1,893    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,358 out of  4,704   50%
      Number used as logic:                     2,199
      Number used as a route-thru:                159
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
--------------------------------------------------------------------------------
* NET "ADC_2xClk" PERIOD =  10 nS   HIGH 50 | 10.000ns   | 10.024ns   | 4    
  .000000 %                                 |            |            |      
--------------------------------------------------------------------------------


Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     1,925 out of  4,704   40%
  Number of 4 input LUTs:         2,262 out of  4,704   48%
Logic Distribution:
    Number of occupied Slices:                       1,863 out of  2,352   79%
    Number of Slices containing only related logic:  1,863 out of  1,863  100%
    Number of Slices containing unrelated logic:         0 out of  1,863    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,422 out of  4,704   51%
      Number used as logic:                     2,262
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
All constraints were met.


##
## 09-Apr-2004
## 10 Gates, with bipolar functionality included for the first time.
## Not functionally tested.
##
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,282 out of  4,704   48%
  Number of 4 input LUTs:         2,579 out of  4,704   54%
Logic Distribution:
    Number of occupied Slices:                       2,088 out of  2,352   88%
    Number of Slices containing only related logic:  2,088 out of  2,088  100%
    Number of Slices containing unrelated logic:         0 out of  2,088    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,741 out of  4,704   58%
      Number used as logic:                     2,579
      Number used as a route-thru:                162
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,046 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
All constraints were met.

## Amp peak selection for Max and last peaks added
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,400 out of  4,704   51%
  Number of 4 input LUTs:         2,643 out of  4,704   56%
Logic Distribution:
    Number of occupied Slices:                       2,173 out of  2,352   92%
    Number of Slices containing only related logic:  2,173 out of  2,173  100%
    Number of Slices containing unrelated logic:         0 out of  2,173    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        2,803 out of  4,704   59%
      Number used as logic:                     2,643
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,036 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

## Dist peak selection for Max and Last peaks added   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,726 out of  4,704   57%
  Number of 4 input LUTs:         3,190 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,230 out of  2,350   94%
    Number of Slices containing unrelated logic:       120 out of  2,350    5%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,350 out of  4,704   71%
      Number used as logic:                     3,190
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,045 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,744 out of  4,704   58%
  Number of 4 input LUTs:         3,145 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,256 out of  2,350   96%
    Number of Slices containing unrelated logic:        94 out of  2,350    4%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,305 out of  4,704   70%
      Number used as logic:                     3,145
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,045 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,864 out of  4,704   60%
  Number of 4 input LUTs:         3,175 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,168 out of  2,350   92%
    Number of Slices containing unrelated logic:       182 out of  2,350    7%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,461 out of  4,704   73%
      Number used as logic:                     3,175
      Number used as a route-thru:                286
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,045 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,842 out of  4,704   60%
  Number of 4 input LUTs:         3,377 out of  4,704   71%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,144 out of  2,350   91%
    Number of Slices containing unrelated logic:       206 out of  2,350    8%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,537 out of  4,704   75%
      Number used as logic:                     3,377
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,045 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,847 out of  4,704   60%
  Number of 4 input LUTs:         3,384 out of  4,704   71%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,140 out of  2,350   91%
    Number of Slices containing unrelated logic:       210 out of  2,350    8%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,544 out of  4,704   75%
      Number used as logic:                     3,384
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,044 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,864 out of  4,704   60%
  Number of 4 input LUTs:         3,240 out of  4,704   68%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,146 out of  2,350   91%
    Number of Slices containing unrelated logic:       204 out of  2,350    8%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,400 out of  4,704   72%
      Number used as logic:                     3,240
      Number used as a route-thru:                160
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,862 out of  4,704   60%
  Number of 4 input LUTs:         3,307 out of  4,704   70%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,127 out of  2,350   90%
    Number of Slices containing unrelated logic:       223 out of  2,350    9%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,475 out of  4,704   73%
      Number used as logic:                     3,307
      Number used as a route-thru:                168
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

# With no pipeline in data rectifier - Timing slightly worse... :-(
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,846 out of  4,704   60%
  Number of 4 input LUTs:         3,310 out of  4,704   70%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,136 out of  2,350   90%
    Number of Slices containing unrelated logic:       214 out of  2,350    9%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,469 out of  4,704   73%
      Number used as logic:                     3,310
      Number used as a route-thru:                159
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,828 out of  4,704   60%
  Number of 4 input LUTs:         3,439 out of  4,704   73%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,099 out of  2,350   89%
    Number of Slices containing unrelated logic:       251 out of  2,350   10%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,590 out of  4,704   76%
      Number used as logic:                     3,439
      Number used as a route-thru:                151
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:                 882 out of  2,464   35%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

## Standard build   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,865 out of  4,704   60%
  Number of 4 input LUTs:         3,314 out of  4,704   70%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,118 out of  2,350   90%
    Number of Slices containing unrelated logic:       232 out of  2,350    9%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,482 out of  4,704   74%
      Number used as logic:                     3,314
      Number used as a route-thru:                168
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

## Build with modified comparision logic
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,818 out of  4,704   59%
  Number of 4 input LUTs:         3,214 out of  4,704   68%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,201 out of  2,350   93%
    Number of Slices containing unrelated logic:       149 out of  2,350    6%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,344 out of  4,704   71%
      Number used as logic:                     3,214
      Number used as a route-thru:                130
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,828 out of  4,704   60%
  Number of 4 input LUTs:         3,328 out of  4,704   70%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,149 out of  2,350   91%
    Number of Slices containing unrelated logic:       201 out of  2,350    8%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,457 out of  4,704   73%
      Number used as logic:                     3,328
      Number used as a route-thru:                129
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,818 out of  4,704   59%
  Number of 4 input LUTs:         3,220 out of  4,704   68%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,194 out of  2,350   93%
    Number of Slices containing unrelated logic:       156 out of  2,350    6%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,349 out of  4,704   71%
      Number used as logic:                     3,220
      Number used as a route-thru:                129
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,042 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,771 out of  4,704   58%
  Number of 4 input LUTs:         2,923 out of  4,704   62%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,236 out of  2,350   95%
    Number of Slices containing unrelated logic:       114 out of  2,350    4%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,052 out of  4,704   64%
      Number used as logic:                     2,923
      Number used as a route-thru:                129
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,032 out of  2,464   41%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     2,771 out of  4,704   58%
  Number of 4 input LUTs:         2,923 out of  4,704   62%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,238 out of  2,350   95%
    Number of Slices containing unrelated logic:       112 out of  2,350    4%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,052 out of  4,704   64%
      Number used as logic:                     2,923
      Number used as a route-thru:                129
   Number of bonded IOBs:           236 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,032 out of  2,464   41%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

##
## 23-04-2004   
##
## 2 stages of FFs on data threshold values to gates
## Do not remove duplicate registers enabled for signals producing 'DataLessThreshold' signals
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     3,138 out of  4,704   66%
  Number of 4 input LUTs:         2,920 out of  4,704   62%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,985 out of  2,350   84%
    Number of Slices containing unrelated logic:       365 out of  2,350   15%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,049 out of  4,704   64%
      Number used as logic:                     2,920
      Number used as a route-thru:                129
   Number of bonded IOBs:           238 out of    284   83%
      IOB Flip Flops:                              72
   Number of Tbufs:               1,032 out of  2,464   41%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,973 out of  4,704   63%
  Number of 4 input LUTs:         3,054 out of  4,704   64%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,077 out of  2,350   88%
    Number of Slices containing unrelated logic:       273 out of  2,350   11%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,210 out of  4,704   68%
      Number used as logic:                     3,054
      Number used as a route-thru:                144
      Number used as Shift registers:              12
   Number of bonded IOBs:           256 out of    284   90%
      IOB Flip Flops:                             105
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     2,948 out of  4,704   62%
  Number of 4 input LUTs:         2,981 out of  4,704   63%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  2,121 out of  2,350   90%
    Number of Slices containing unrelated logic:       229 out of  2,350    9%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,128 out of  4,704   66%
      Number used as logic:                     2,981
      Number used as a route-thru:                135
      Number used as Shift registers:              12
   Number of bonded IOBs:           256 out of    284   90%
      IOB Flip Flops:                             105
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
#
# 3-May-2004
# Added write Shaft Encoder values to sampling RAM functionality
#
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     3,351 out of  4,704   71%
  Number of 4 input LUTs:         3,125 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,914 out of  2,350   81%
    Number of Slices containing unrelated logic:       436 out of  2,350   18%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,273 out of  4,704   69%
      Number used as logic:                     3,125
      Number used as a route-thru:                136
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                             107
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     3,420 out of  4,704   72%
  Number of 4 input LUTs:         3,151 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,776 out of  2,350   75%
    Number of Slices containing unrelated logic:       574 out of  2,350   24%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,300 out of  4,704   70%
      Number used as logic:                     3,151
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                              92
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     3,420 out of  4,704   72%
  Number of 4 input LUTs:         3,167 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,821 out of  2,350   77%
    Number of Slices containing unrelated logic:       529 out of  2,350   22%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,316 out of  4,704   70%
      Number used as logic:                     3,167
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                              92
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    1
Logic Utilization:
  Number of Slice Flip Flops:     3,310 out of  4,704   70%
  Number of 4 input LUTs:         3,151 out of  4,704   66%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,828 out of  2,350   77%
    Number of Slices containing unrelated logic:       522 out of  2,350   22%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,300 out of  4,704   70%
      Number used as logic:                     3,151
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                              92
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   3 out of      4   75%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     3,310 out of  4,704   70%
  Number of 4 input LUTs:         3,172 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,810 out of  2,350   77%
    Number of Slices containing unrelated logic:       540 out of  2,350   22%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,321 out of  4,704   70%
      Number used as logic:                     3,172
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
      IOB Flip Flops:                              92
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     3,401 out of  4,704   72%
  Number of 4 input LUTs:         3,174 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,761 out of  2,350   74%
    Number of Slices containing unrelated logic:       589 out of  2,350   25%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,323 out of  4,704   70%
      Number used as logic:                     3,174
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
   Number of Tbufs:               1,065 out of  2,464   43%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

#
# 05-May-2004
# Using simple code for comparator
#
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     3,401 out of  4,704   72%
  Number of 4 input LUTs:         3,191 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,869 out of  2,350   79%
    Number of Slices containing unrelated logic:       481 out of  2,350   20%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,340 out of  4,704   71%
      Number used as logic:                     3,191
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
   Number of Tbufs:               1,049 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
#
# Using seperate module with RLOCs for comparator
#
Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:     3,401 out of  4,704   72%
  Number of 4 input LUTs:         3,161 out of  4,704   67%
Logic Distribution:
    Number of occupied Slices:                       2,350 out of  2,352   99%
    Number of Slices containing only related logic:  1,774 out of  2,350   75%
    Number of Slices containing unrelated logic:       576 out of  2,350   24%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        3,310 out of  4,704   70%
      Number used as logic:                     3,161
      Number used as a route-thru:                137
      Number used as Shift registers:              12
   Number of bonded IOBs:           258 out of    284   90%
   Number of Tbufs:               1,049 out of  2,464   42%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%