---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: DistRam32.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card (Shared component)
--
-- Design Description:
-- Module to to infer Xilinx Distributed RAM - 32 deep
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity DistRam32 is
  generic(gDataWidth:    integer range 1 to 64 := 64);
  port(pClk     : in  std_ulogic;
       pWriteEn : in  std_ulogic;
       pAddr    : in  std_logic_vector(4 downto 0);
       pDataIn  : in  std_logic_vector(gDataWidth-1 downto 0);
       pDataOut : out std_logic_vector(gDataWidth-1 downto 0));
end entity DistRam32;


architecture syn of DistRam32 is

  component RAM32X1S
    port (O    : out std_ulogic;
          A0   : in  std_ulogic;
          A1   : in  std_ulogic;
          A2   : in  std_ulogic;
          A3   : in  std_ulogic;
          A4   : in  std_ulogic;
          D    : in  std_ulogic;
          WCLK : in  std_ulogic;
          WE   : in  std_ulogic);
  end component;

begin

  GenRam0: for i in 0 to gDataWidth-1 generate
    GenRam1: RAM32X1S
      -- Edit the following generic to change the inital contents
      -- of the RAM.
      port map (O    => pDataOut(i),
                A0   => pAddr(0),
                A1   => pAddr(1),
                A2   => pAddr(2),
                A3   => pAddr(3),
                A4   => pAddr(4),
                D    => pDataIn(i),
                WCLK => pClk,
                WE   => pWriteEn);
  end generate;
  
end syn;
