---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: DspFpgaTop.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Top Level for NDTS2100 DSP FPGA
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_arith.all;

library UNISIM;
use UNISIM.vcomponents.all;

library work;
use work.DspFpgaPkg.all;

entity DspFpgaTop is
  port (-- Local bus
        nLRESET    : in    std_ulogic;
        LCLK       : in    std_ulogic;
        LWnR       : inout std_ulogic;
        LD         : inout std_logic_vector(31 downto 0);
        DP         : inout std_logic_vector(3 downto 0);
        LA         : inout std_logic_vector(31 downto 2);
        nADS       : inout std_ulogic;
        nBLAST     : inout std_ulogic;
        nREADY     : inout std_ulogic;
        nWAIT      : inout std_ulogic;
        nBTERM     : inout std_ulogic;
        nLBE       : inout std_logic_vector(3 downto 0);
        BREQi      : out   std_ulogic;
        BREQo      : in    std_ulogic;
        nDREQ0     : out   std_ulogic;
        nDREQ1     : out   std_ulogic;
        nDACK0     : in    std_ulogic;
        nDACK1     : in    std_ulogic;
        nLINTi     : out   std_ulogic;
        nLINTo     : in    std_ulogic;
        nLSERR     : in    std_ulogic;
        nBIGEND    : out   std_ulogic;
        LHOLD      : in    std_ulogic;
        LHOLDA     : out   std_ulogic;
        USERi      : out   std_ulogic;
        USERo      : in    std_ulogic;
        nEOT       : in    std_ulogic;
        nCCS       : out   std_ulogic;
        nPMEIN     : out   std_ulogic;
        GPIO       : inout std_logic_vector(3 downto 0);
        -- A to D Signals
        AD_DcoP    : in    std_ulogic;
        AD_DcoN    : in    std_ulogic;
        AD_DP      : in    std_logic_vector(11 downto 0);
        AD_DN      : in    std_logic_vector(11 downto 0);
        AD_OrP     : in    std_ulogic;
        AD_OrN     : in    std_ulogic;
        nAD_Reset  : out   std_ulogic;
        nAD_Cs     : out   std_ulogic;
        AD_SClk    : out   std_ulogic;
        AD_SDio    : inout std_ulogic;
        -- DDS
        DdsFSync   : out   std_ulogic;
        DdsSClk    : out   std_ulogic;
        DdsSData   : out   std_ulogic;
        DdsSleep   : out   std_ulogic;
        DdsReset   : out   std_ulogic;
        DdsPSelect : out   std_ulogic;
        DdsFSelect : out   std_ulogic;
        nDdsOscInh : out   std_ulogic;
        -- Pulser and filters
        PulsePFetP : out   std_ulogic;
        PulsePFetN : out   std_ulogic;
        PulseNFetP : out   std_ulogic;
        PulseNFetN : out   std_ulogic;

        ChTxP      : out   std_logic_vector(7 downto 0);
        ChTxN      : out   std_logic_vector(7 downto 0);
        ChCkP      : out   std_logic_vector(7 downto 0);
        ChCkN      : out   std_logic_vector(7 downto 0);
        ChRxP      : out   std_logic_vector(7 downto 0);
        ChRxN      : out   std_logic_vector(7 downto 0);

        IoOutTxP   : out   std_ulogic;
        IoOutTxN   : out   std_ulogic;
        IoOutCkP   : out   std_ulogic;
        IoOutCkN   : out   std_ulogic;
        IoOutRxP   : out   std_ulogic;
        IoOutRxN   : out   std_ulogic;

        IoInTxP    : in    std_ulogic;
        IoInTxN    : in    std_ulogic;
        IoInCkP    : in    std_ulogic;
        IoInCkN    : in    std_ulogic;
        IoInRxP    : in    std_ulogic;
        IoInRxN    : in    std_ulogic;
        -- Encoder and Pulse inputs
        OpPha      : in    std_logic_vector(4 downto 1);
        OpPhb      : in    std_logic_vector(4 downto 1);
        OpIndex    : in    std_logic_vector(4 downto 1);

        FSerData   : out   std_ulogic;
        nFSerOE    : out   std_ulogic;
        FSerRClk   : out   std_ulogic;
        FSerClk    : out   std_ulogic;
        FSel0db    : out   std_ulogic;
        FSelN20db  : out   std_ulogic;
        FSelN40db  : out   std_ulogic;
        FSelP20db  : out   std_ulogic;
        -- HV PSU
        nHVEnable  : out   std_ulogic;
        HVFeedback : in    std_ulogic;
        nHVDisChg  : out   std_ulogic;
        nHVSync    : out   std_ulogic;
        HVSClk     : out   std_ulogic;
        HVSDIn     : out   std_ulogic;
        -- TCG RAM
        TcgDacClk  : out   std_ulogic;
        TcgDacSleep: out   std_ulogic;
        TcgDacD    : inout std_logic_vector(11 downto 0);
        TcgDacA    : out   std_logic_vector(17 downto 0);
        nTcgDacBHE : out   std_ulogic;
        nTcgDacBLE : out   std_ulogic;
        nTcgDacOe  : out   std_ulogic;
        nTcgDacCs  : out   std_ulogic;
        nTcgDacWr  : out   std_ulogic;
        -- SDRAM
        SR_Ck      : out   std_logic_vector(1 downto 0);
        nSR_Ck     : out   std_logic_vector(1 downto 0);
        SR_Cke     : out   std_logic_vector(1 downto 0);
        SR_Dq      : inout std_logic_vector(63 downto 0);
        SR_Dqs     : inout std_logic_vector(7 downto 0);
        nSR_Dqs    : inout std_logic_vector(7 downto 0);
        SR_DM      : out   std_logic_vector(7 downto 0);
        SR_A       : out   std_logic_vector(13 downto 0);
        SR_Ba      : out   std_logic_vector(2 downto 0);
        nSR_We     : out   std_ulogic;
        nSR_Ras    : out   std_ulogic;
        nSR_Cas    : out   std_ulogic;
        SR_ODT     : out   std_logic_vector(1 downto 0);
        nSR_S      : out   std_logic_vector(1 downto 0);
        SR_SCL     : out   std_ulogic;
        SR_SDA     : inout std_ulogic;
        SR_SA      : out   std_logic_vector(1 downto 0);
        SR_DqsDiv  : inout std_ulogic;  -- i/o delay equalisation pin
        -- Ethernet Phy
        PhyClkToMac: in    std_ulogic;
        nPhyReset  : out   std_ulogic;
        PhyRxCrs   : in    std_ulogic;
        PhyRxCol   : in    std_ulogic;
        PhyRxClk   : in    std_ulogic;
        PhyRxDv    : in    std_ulogic;
        PhyRxEr    : in    std_ulogic;
        PhyRxD     : in    std_logic_vector(7 downto 0);
        PhyGTxClk  : out   std_ulogic;
        PhyTxClk   : in    std_ulogic;
        PhyTxEn    : in    std_ulogic;
        PhyTxEr    : in    std_ulogic;
        PhyTxD     : out   std_logic_vector(7 downto 0);
        PhyMdc     : out   std_ulogic;
        PhyMdio    : inout std_ulogic;
        nPhyInt    : in    std_ulogic;
        PhyMdixEn  : out   std_ulogic;
        PhyMultiEn : out   std_ulogic;
        PhyAd      : out   std_logic_vector(4 downto 0);
        PhyAnEn    : out   std_ulogic;
        PhyDuplex  : out   std_ulogic;
        PhySpeed   : out   std_logic_vector(1 downto 0);
        -- MRAM
        MRamIO     : inout std_logic_vector(15 downto 0);
        MRamA      : out   std_logic_vector(17 downto 0);
        nMRamCs    : out   std_ulogic;
        nMRamWe    : out   std_ulogic;
        nMRamOe    : out   std_ulogic;
        nMRamBle   : out   std_ulogic;
        nMRamBhe   : out   std_ulogic;
        -- Misc IO
        FTrigger   : in    std_ulogic;
        FSync      : out   std_ulogic;
        Ident      : in    std_logic_vector(3 downto 0);
        nSDVterm   : out   std_ulogic;
        Relay      : out   std_ulogic;
        DBugD      : inout std_logic_vector(3 downto 0);

        BuzzP      : in    std_logic_vector(11 downto 0);
        BuzzN      : in    std_logic_vector(11 downto 0));
end entity DspFpgaTop;


architecture Str of DspFpgaTop is
  component DataRectifier
    port(nReset         : in  std_ulogic;
         Clk            : in  std_ulogic;
         AdcOffset      : in  std_logic_vector(12 downto 0);
         DropSamples    : in  std_logic_vector(15 downto 0);
         Mode           : in  std_logic_vector(1 downto 0);
         Mod8Bit        : in  std_ulogic;
         SignExtendMode : in  std_ulogic;
         SignAndMagMode : in  std_ulogic;
         DataIn         : in  std_logic_vector(11 downto 0);
         SampleEn       : out std_ulogic;
         SampleData     : out std_logic_vector(15 downto 0);
         DataOut        : out std_logic_vector(11 downto 0);
         RectifiedOut   : out std_logic_vector(10 downto 0));
  end component;

  component InterfaceGate
    port(nReset         : in  std_ulogic;
         Clk            : in  std_ulogic;
         SampleEn       : in  std_ulogic;
         TriggerIn      : in  std_ulogic;
         Enable         : in  std_ulogic;
         StartCount     : in  std_logic_vector(23 downto 0);
         StopCount      : in  std_logic_vector(23 downto 0);
         Threshold      : in  std_logic_vector(10 downto 0);
         TriggerMode    : in  std_ulogic;
         PolarityMode   : in  std_logic_vector(1 downto 0);
         RectifiedData  : in  std_logic_vector(10 downto 0);
         PolarityIn     : in  std_ulogic;
         GateFiring     : out std_ulogic;
         GateFired      : out std_ulogic;
         GateDidNotFire : out std_ulogic;
         GateOutputData : out std_logic_vector(13 downto 0));
  end component;

  component Gate
    port(nReset         : in  std_ulogic;
         Clk            : in  std_ulogic;
         SampleEn       : in  std_ulogic;
         TriggersIn     : in  std_logic_vector(15 downto 0);
         NoTriggersIn   : in  std_logic_vector(15 downto 0);
         Enable         : in  std_ulogic;
         StartCount     : in  std_logic_vector(23 downto 0);
         StopCount      : in  std_logic_vector(23 downto 0);
         ForceStop      : in  std_ulogic;
         Threshold      : in  std_logic_vector(10 downto 0);
         TriggerNum     : in  std_logic_vector(3 downto 0);
         TriggerMode    : in  std_ulogic;
         ZeroCrossMode  : in  std_ulogic;
         PolarityMode   : in  std_logic_vector(1 downto 0);
         DistMetric     : in  std_logic_vector(1 downto 0);
         PeakSelAmp     : in  std_logic_vector(3 downto 0);
         PeakSelDist    : in  std_logic_vector(3 downto 0);
         Holdoff        : in  std_logic_vector(7 downto 0);
         SampleData     : in  std_logic_vector(11 downto 0);
         RectifiedData  : in  std_logic_vector(10 downto 0);
         StoreNoTrig    : in  std_ulogic;
         GateDistFire   : out std_ulogic;
         GateDistClear  : out std_ulogic;
         GateFiring     : out std_ulogic;
         GateUnTrigger  : out std_ulogic;
         GateFired      : out std_ulogic;
         GateDidNotFire : out std_ulogic;
         GateReFire     : out std_ulogic;
         GateOutputData : out std_logic_vector(13 downto 0));
  end component;

  component GateResultSelect
    port(nReset         : in  std_ulogic;
         SysClk         : in  std_ulogic;
         SampleEn       : in  std_ulogic;
         TriggersIn     : in  std_logic_vector(15 downto 0);
         UnTriggersIn   : in  std_logic_vector(15 downto 0);
         NoTriggersIn   : in  std_logic_vector(15 downto 0);
         ReTriggersIn   : in  std_logic_vector(15 downto 0);
         GateSelect     : in  std_logic_vector(2 downto 0);
         GateDistance   : in  std_ulogic;
         GateDataIn     : in  tGateData14;
--         GateDataIn     : in  tGateData24;
--         GateDistIn     : in  tGateData24;
         GateData       : out std_logic_vector(31 downto 0));
  end component;

  component RamWriteCtrl
    port (nReset            : in  std_ulogic;
          SysClk            : in  std_ulogic;
          LClk              : in  std_ulogic;
          -- Sample data
          SampleIn          : in  std_logic_vector(15 downto 0);
          SampleValid       : in  std_ulogic;
          TestMode          : in  std_ulogic;
          AScanStart        : in  std_ulogic;
          StartCapture      : in  std_ulogic;
          SequenceActive    : in  std_ulogic;
          AScanDone         : out std_ulogic;
          -- Encoder and Gata Data
          EncoderCount0     : in  std_logic_vector(31 downto 0);
          EncoderCount1     : in  std_logic_vector(31 downto 0);
          EncoderCount2     : in  std_logic_vector(31 downto 0);
          EncoderCount3     : in  std_logic_vector(31 downto 0);
          DualEncoderCount  : in  std_logic_vector(31 downto 0);
          PulseCount0       : in  std_logic_vector(31 downto 0);
          PulseCount1       : in  std_logic_vector(31 downto 0);
          PulseCount2       : in  std_logic_vector(31 downto 0);
          PulseCount3       : in  std_logic_vector(31 downto 0);
          GateData          : in  std_logic_vector(31 downto 0);
          GateSelect        : out std_logic_vector(2 downto 0);
          GateDistance      : out std_ulogic;
          -- RAM write controls out
          WriteData         : out std_logic_vector(31 downto 0);
          WriteAEn          : out std_ulogic;
          WriteCEn          : out std_ulogic;
          ResetAScanAddr    : out std_ulogic;
          ResetCScanAddr    : out std_ulogic;
          BankSel           : out std_ulogic;
          -- Register signals
          GateEnable        : in  std_logic_vector(7 downto 0);
          AScanRange        : in  std_logic_vector(23 downto 0);
          SequencesPerBank  : in  std_logic_vector(15 downto 0);
          SequenceSteps     : in  std_logic_vector(4 downto 0);
          StartSequence     : in  std_ulogic;
          SequencesInRam    : out std_logic_vector(15 downto 0);
          SequenceStep      : out std_logic_vector(4 downto 0);
          StorageMode       : in  std_logic_vector(1 downto 0);
          SetDataReady      : out std_ulogic;
          SetNewTrigger     : out std_ulogic;
          SetEarlyTrigError : out std_ulogic;
          SetDataFullError  : out std_ulogic;
          SomeDataReady     : out std_ulogic;
          DataReady         : in  std_ulogic;
          EarlyDataReq      : in  std_ulogic;
          ResetSampling     : in  std_ulogic);
  end component;

  component RamArbitrate
    port (nReset          : in  std_ulogic;
          RamClk          : in  std_ulogic;
          -- SDRAM interface i/o
          RamDIn          : out std_logic_vector(127 downto 0);
          RamDMask        : out std_logic_vector(15 downto 0);
          RamDOut         : in  std_logic_vector(127 downto 0);
          RamAddr         : out std_logic_vector(30 downto 5);
          RamWr           : out std_ulogic;
          RamWrPop        : in  std_ulogic;
          RamAck          : in  std_ulogic;
          RamRd           : out std_ulogic;
          RamRdPush       : in  std_ulogic;
          -- Local Processor bus
          LClk            : in  std_ulogic;
          LWrData         : in  std_logic_vector(31 downto 0);
          LRdData         : out std_logic_vector(31 downto 0);
          LAddr           : in  std_logic_vector(30 downto 0);
          LWr             : in  std_ulogic;
          LRd             : in  std_ulogic;
          LAck            : out std_ulogic;
          -- Data input
          SysClk          : in  std_ulogic;
          DataIn          : in  std_logic_vector(31 downto 0);
          DataWrA         : in  std_ulogic;
          DataWrC         : in  std_ulogic;
          ResetAScanAddr  : in  std_ulogic;
          ResetCScanAddr  : in  std_ulogic;
          BankSel         : in  std_ulogic;
          -- Register signals
          CScanOffsetAddr : in  std_logic_vector(30 downto 0);
          BankSize        : in  std_logic_vector(30 downto 0);
          ResetSampling   : in  std_ulogic);
  end component;

  component SDRAMIf
    port (ClkIn     : in    std_ulogic;
          nReset    : in    std_ulogic;
          MemClkOut : out   std_ulogic;
          -- User i/o
          uDIn      : in    std_logic_vector(127 downto 0);
          uDMask    : in    std_logic_vector(15 downto 0);
          uDOut     : out   std_logic_vector(127 downto 0);
          uAddr     : in    std_logic_vector(30 downto 5);
          uWr       : in    std_ulogic;
          uWrPop    : out   std_ulogic;
          uRd       : in    std_ulogic;
          uRdPush   : out   std_ulogic;
          uAck      : out   std_ulogic;
          -- SDRAM
          SR_Ck     : out   std_logic_vector(1 downto 0);
          nSR_Ck    : out   std_logic_vector(1 downto 0);
          SR_Cke    : out   std_logic_vector(1 downto 0);
          SR_Dq     : inout std_logic_vector(63 downto 0);
          SR_Dqs    : inout std_logic_vector(7 downto 0);
          nSR_Dqs   : inout std_logic_vector(7 downto 0);
          SR_DM     : out   std_logic_vector(7 downto 0);
          SR_A      : out   std_logic_vector(13 downto 0);
          SR_Ba     : out   std_logic_vector(2 downto 0);
          nSR_We    : out   std_ulogic;
          nSR_Ras   : out   std_ulogic;
          nSR_Cas   : out   std_ulogic;
          SR_ODT    : out   std_logic_vector(1 downto 0);
          nSR_S     : out   std_logic_vector(1 downto 0);
          SR_SCL    : out   std_ulogic;
          SR_SDA    : inout std_ulogic;
          SR_SA     : out   std_logic_vector(1 downto 0);
          RstDqsDiv : inout std_ulogic;
          RfrshReq  : out   std_ulogic;
          RfrshDone : out   std_ulogic;
          SoDimmSize: out   std_logic_vector(3 downto 0);
          SoDimmVal : out   std_ulogic);
  end component;

  component DspLBusInterface
    port (-- Local bus
          nReset            : in  std_ulogic;
          LClk              : in  std_ulogic;
          LWnR              : in  std_ulogic;
          LDIn              : in  std_logic_vector(31 downto 0);
          LDOut             : out std_logic_vector(31 downto 0);
          nLDOe             : out std_ulogic;
          LAin              : in  std_logic_vector(31 downto 2);
          nAds              : in  std_ulogic;
          nBLast            : in  std_ulogic;
          nReady            : out std_ulogic;
          nBTerm            : out std_ulogic;
          LHold             : in  std_ulogic;
          LHoldA            : out std_ulogic;
          BReqi             : out std_ulogic;
          nLINTi            : out std_ulogic;
          -- TCG RAM processor bus
          TCGRamWrData      : out std_logic_vector(11 downto 0);
          TCGRamRdData      : in  std_logic_vector(11 downto 0);
          TCGRamAddr        : out std_logic_vector(17 downto 0);
          TCGRamWr          : out std_ulogic;
          TCGRamRd          : out std_ulogic;
          TCGRamAck         : in  std_ulogic;
          -- SDRAM processor bus
          LRamWrData        : out std_logic_vector(31 downto 0);
          LRamRdData        : in  std_logic_vector(31 downto 0);
          LRamAddr          : out std_logic_vector(30 downto 0);
          LRamWr            : out std_ulogic;
          LRamRd            : out std_ulogic;
          LRamAck           : in  std_ulogic;
          -- ADC controls
          RawAdcRd          : out std_ulogic;
          RawAdcData        : in  std_logic_vector(11 downto 0);
          AdcOffset         : out std_logic_vector(12 downto 0);
          DropSamples       : out std_logic_vector(15 downto 0);
          RectMode          : out std_logic_vector(1 downto 0);
          RectMod8Bit       : out std_ulogic;
          TestPatternMode   : out std_ulogic;
          SignExtendMode    : out std_ulogic;
          SignAndMagMode    : out std_ulogic;
          AdcSerWr          : out std_ulogic;
          AdcSerInst        : out std_logic_vector(15 downto 0);
          AdcSerDOut        : out std_logic_vector(7 downto 0);
          AdcSerDIn         : in  std_logic_vector(7 downto 0);
          AdcResetWr        : out std_ulogic;
          AdcBusy           : in  std_ulogic;
          -- DDS  Controls
          DdsData           : out std_logic_vector(15 downto 0);
          DdsWr             : out std_ulogic;
          DdsBusy           : in  std_ulogic;
          DdsSleep          : out std_ulogic;
          DdsReset          : out std_ulogic;
          DdsPSelect        : out std_ulogic;
          DdsFSelect        : out std_ulogic;
          nDdsOscInh        : out std_ulogic;
          -- HV Controls
          HVDACData         : out std_logic_vector(15 downto 0);
          HVDACWr           : out std_ulogic;
          HVDACBusy         : in  std_ulogic;
          nHVEnable         : out std_ulogic;
          nHVDisChg         : out std_ulogic;
          HVFeedback        : in  std_ulogic;
          -- Gate controls
          Holdoff           : out std_logic_vector(7 downto 0);
          GateStart         : out tGateData24;
          GateStop          : out tGateData24;
          GateAttrib        : out tGateData32;
          -- Data capture controls
          AScanRepRate      : out std_logic_vector(23 downto 0);
          AScanRange        : out std_logic_vector(23 downto 0);
          BankSize          : out std_logic_vector(30 downto 0);
          BankSel           : in  std_ulogic;
          CScanOffsetAddr   : out std_logic_vector(30 downto 0);
          StorageMode       : out std_logic_vector(1 downto 0);
          SetDataReady      : in  std_ulogic;
          SetNewTrigger     : in  std_ulogic;
          SetEarlyTrigError : in  std_ulogic;
          SetDataFullError  : in  std_ulogic;
          SomeDataReady     : in  std_ulogic;
          DataReady         : out std_ulogic;
          EarlyDataReq      : out std_ulogic;
          ResetSampling     : out std_ulogic;
          -- Sequence controls
          SequenceRepRate   : out std_logic_vector(31 downto 0);
          SequencesPerBank  : out std_logic_vector(15 downto 0);
          SequenceSteps     : out std_logic_vector(4 downto 0);
          StartSequence     : out std_ulogic;
          SequencesInRam    : in  std_logic_vector(15 downto 0);
          SequenceStep      : in  std_logic_vector(4 downto 0);
          -- Trigger pulse controls
          TriggerDelay      : out std_logic_vector(23 downto 0);
          PulseWidth        : out std_logic_vector(15 downto 0);
          PulseTrain        : out std_logic_vector(3 downto 0);
          ExtTriggerEn      : out std_ulogic;
          FreeRunningEn     : out std_ulogic;
          EncoderTriggerEn  : out std_ulogic;
          ForceTrigger      : out std_ulogic;
          SyncPulseEn       : out std_ulogic;
          -- TCG controls
          TCGAbsoluteTrig   : out std_ulogic;
          TCGEnable         : out std_ulogic;
          TCGBEAGate        : out std_logic_vector(2 downto 0);
          TCGBEAEnable      : out std_ulogic;
          TCGPoints         : out std_logic_vector(18 downto 0);
          TCGSamples        : out std_logic_vector(15 downto 0);
          -- Encoder Controls
          EncoderReset      : out std_logic_vector(8 downto 0);
          EncoderSelect     : out std_logic_vector(3 downto 0);
          ClicksPerSeq      : out std_logic_vector(23 downto 0);
          FractClicks       : out std_logic_vector(15 downto 0);
          EncoderCount0     : in  std_logic_vector(31 downto 0);
          EncoderCount1     : in  std_logic_vector(31 downto 0);
          EncoderCount2     : in  std_logic_vector(31 downto 0);
          EncoderCount3     : in  std_logic_vector(31 downto 0);
          DualEncoderCount  : in  std_logic_vector(31 downto 0);
          PulseCount0       : in  std_logic_vector(31 downto 0);
          PulseCount1       : in  std_logic_vector(31 downto 0);
          PulseCount2       : in  std_logic_vector(31 downto 0);
          PulseCount3       : in  std_logic_vector(31 downto 0);
          -- Misc Controls
          InputSelUpdate    : out std_ulogic;
          FilterCtrlUpdate  : out std_ulogic;
          IpSelReg          : out std_logic_vector(31 downto 0);
          FilterCtrlReg     : out std_logic_vector(15 downto 0);
          Relay             : out std_ulogic;
          Ident             : in  std_logic_vector(3 downto 0);
          SoDimmSize        : in  std_logic_vector(3 downto 0);
          SoDimmVal         : in  std_ulogic);
  end component;

  component BeaSwitch
    port(nReset         : in  std_ulogic;
         Clk            : in  std_ulogic;
         TriggersIn     : in  std_logic_vector(7 downto 0);
         TriggerNum     : in  std_logic_vector(2 downto 0);
         BeaEnable      : in  std_ulogic;
         BeaSwitch      : out std_ulogic);
  end component;

  component SIPOCtrl
    generic(gHCycle: integer := 2);
    port (nReset        : in  std_ulogic;
          Clk           : in  std_ulogic;
          Update        : in  std_ulogic;
          IpSelReg      : in  std_logic_vector(31 downto 0);
          FilterCtrlReg : in  std_logic_vector(15 downto 0);
          Bea           : in  std_ulogic;
          --
          FSerData      : out std_ulogic;
          nFSerOE       : out std_ulogic;
          FSerRClk      : out std_ulogic;
          FSerClk       : out std_ulogic;
          FSel0db       : out std_ulogic;
          FSelN20db     : out std_ulogic;
          FSelN40db     : out std_ulogic;
          FSelP20db     : out std_ulogic);
  end component;

  component SpiAD
    generic(gHCycle: integer := 2);
    port(nReset   : in    std_ulogic;
         Clk      : in    std_ulogic;
         SerWr    : in    std_ulogic;
         Inst     : in    std_logic_vector(15 downto 0);
         DataIn   : out   std_logic_vector(7 downto 0);
         DataOut  : in    std_logic_vector(7 downto 0);
         ResetWr  : in    std_ulogic;
         Busy     : out   std_ulogic;
         --
         CSB      : out   std_ulogic;
         SClk     : out   std_ulogic;
         SDIO     : inout std_logic;
         Reset    : out   std_ulogic);
  end component;

  component Spi16
    generic(gHCycle: integer := 2);
    port (nReset    : in  std_ulogic;
          Clk       : in  std_ulogic;
          Wr        : in  std_ulogic;
          Data      : in  std_logic_vector(15 downto 0);
          Busy      : out std_ulogic;
          --
          SClk      : out std_ulogic;
          SData     : out std_ulogic;
          nSync     : out std_ulogic);
  end component;

  component TriggerGenerator
    port (nReset          : in  std_ulogic;
          Clk             : in  std_ulogic; -- 200MHz sample clock
          LClk            : in  std_ulogic; -- 66MHz sample clock
          -- Register interface signals
          AScanRepRate    : in  std_logic_vector(23 downto 0);  -- 10ns resolution
          SequenceRepRate : in  std_logic_vector(31 downto 0);  -- 10ns resolution
          SequenceSteps   : in  std_logic_vector(4 downto 0);
          StartSequence   : in  std_ulogic;
          TriggerDelay    : in  std_logic_vector(23 downto 0);  -- 5ns resolution
          PulseWidth      : in  std_logic_vector(15 downto 0);  -- 5ns resolution
          PulseTrain      : in  std_logic_vector(3 downto 0);
          ExtTriggerEn    : in  std_ulogic;
          FreeRunningEn   : in  std_ulogic;
          EncoderTriggerEn: in  std_ulogic;
          -- Trigger/Pulse i/o
          ForceTrigger    : in  std_ulogic;
          ExtTriggerIn    : in  std_ulogic;
          EncoderTriggerIn: in  std_ulogic;
          TriggerPulse    : out std_ulogic;
          DelayedTrigger  : out std_ulogic;
          AScanStart      : out std_ulogic;
          SequenceStart   : out std_ulogic;
          SequenceActive  : out std_ulogic;
          CaptureDone     : out std_ulogic);
  end component;

  component EncoderCounter
    port (-- Local bus
          nReset          : in  std_ulogic;
          LClk            : in  std_ulogic;
          -- Register interface signals
          EncoderReset    : in  std_logic_vector(8 downto 0);
          EncoderSelect   : in  std_logic_vector(3 downto 0);
          ClicksPerSeq    : in  std_logic_vector(23 downto 0);
          FractClicks     : in  std_logic_vector(15 downto 0);
          EncoderCount0   : out std_logic_vector(31 downto 0);
          EncoderCount1   : out std_logic_vector(31 downto 0);
          EncoderCount2   : out std_logic_vector(31 downto 0);
          EncoderCount3   : out std_logic_vector(31 downto 0);
          DualEncoderCount: out std_logic_vector(31 downto 0);
          PulseCount0     : out std_logic_vector(31 downto 0);
          PulseCount1     : out std_logic_vector(31 downto 0);
          PulseCount2     : out std_logic_vector(31 downto 0);
          PulseCount3     : out std_logic_vector(31 downto 0);
          -- Encoder/Pulse inputs
          EncoderPhA      : in  std_logic_vector(3 downto 0);
          EncoderPhB      : in  std_logic_vector(3 downto 0);
          PulseIn         : in  std_logic_vector(3 downto 0);
          -- Seq control
          SeqActiveIn     : in  std_ulogic;
          SeqTriggerOut   : out std_ulogic;
          SeqTriggerIn    : in  std_ulogic);
  end component;

  component TCGControl
    port (nReset          : in  std_ulogic;
          SysClk          : in  std_ulogic;
          TCGEnable       : in  std_ulogic;
          TCGAbsoluteTrig : in  std_ulogic;
          TCGPoints       : in  std_logic_vector(18 downto 0);
          TCGSamples      : in  std_logic_vector(15 downto 0);
          TrigAbsolute    : in  std_ulogic;
          TrigInterface   : in  std_ulogic;
          SampleEn        : in  std_ulogic;
          CaptureDone     : in  std_ulogic;
          -- LBUS RAM access Signals
          LClk            : in  std_ulogic;
          TCGRAMWr        : in  std_ulogic;
          TCGRAMRd        : in  std_ulogic;
          TCGRAMAck       : out std_ulogic;
          TCGRAMAddr      : in  std_logic_vector(17 downto 0);
          -- DAC SRAM Signals
          nTcgDacDOe      : out std_ulogic;
          TcgDacA         : out std_logic_vector(17 downto 0);
          nTcgDacCs       : out std_ulogic;
          nTcgDacBLE      : out std_ulogic;
          nTcgDacBHE      : out std_ulogic;
          nTcgDacOe       : out std_ulogic;
          nTcgDacWr       : out std_ulogic;
          -- Actual DAC Signals
          TcgDacSleep     : out std_ulogic;
          TcgDacClk       : out std_ulogic);
  end component;

  component StrobeExtender
    generic(gLfsrBits: integer range 3 to 32 := 3);
    port(nReset    : in  std_ulogic;
         Clk       : in  std_ulogic;
         StrobeIn  : in  std_ulogic;
         StrobeOut : out std_ulogic);
  end component;

  signal nReset : std_ulogic;
  signal Reset  : std_ulogic;
  signal LClkBuf: std_ulogic;

  signal LDOut      : std_logic_vector(31 downto 0);
  signal nLDOe      : std_ulogic;
  signal nTcgDacDOe : std_ulogic;

  signal TCGRamWrData : std_logic_vector(11 downto 0);
  signal TCGRamAddr   : std_logic_vector(17 downto 0);
  signal TCGRamWr     : std_ulogic;
  signal TCGRamRd     : std_ulogic;
  signal TCGRamAck    : std_ulogic;

  signal LRamWrData : std_logic_vector(31 downto 0);
  signal LRamRdData : std_logic_vector(31 downto 0);
  signal LRamAddr   : std_logic_vector(30 downto 0);
  signal LRamWr     : std_ulogic;
  signal LRamRd     : std_ulogic;
  signal LRamAck    : std_ulogic;

  signal RamClk     : std_ulogic;
  signal RamDIn     : std_logic_vector(127 downto 0);
  signal RamDMask   : std_logic_vector(15 downto 0);
  signal RamDOut    : std_logic_vector(127 downto 0);
  signal RamAddr    : std_logic_vector(30 downto 5);
  signal RamWr      : std_ulogic;
  signal RamWrPop   : std_ulogic;
  signal RamRd      : std_ulogic;
  signal RamRdPush  : std_ulogic;
  signal RamAck     : std_ulogic;

  signal SysClkx2     : std_ulogic;
  signal SysClk       : std_ulogic;
  signal SysClkLocked : std_ulogic;
  signal SysClk0      : std_ulogic;

  signal PulsePFet: std_ulogic;
  signal PulseNFet: std_ulogic;

  signal AdcD   : std_logic_vector(11 downto 0);
  signal AdcOr  : std_ulogic;
  signal AdcD1  : std_logic_vector(11 downto 0);
  signal AdcD2  : std_logic_vector(11 downto 0);
  signal AdcOr1 : std_ulogic;
  signal RawAdcRd   : std_ulogic;
  signal RawAdcRdD  : std_logic_vector(2 downto 0);
  signal AdcSample  : std_logic_vector(11 downto 0);
  signal AdcSerWr   : std_ulogic;
  signal AdcSerInst : std_logic_vector(15 downto 0);
  signal AdcSerDOut : std_logic_vector(7 downto 0);
  signal AdcSerDIn  : std_logic_vector(7 downto 0);
  signal AdcResetWr : std_ulogic;
  signal AdcBusy    : std_ulogic;

  signal AdcOffset  : std_logic_vector(12 downto 0);
  signal DropSamples: std_logic_vector(15 downto 0);
  signal RectMode   : std_logic_vector(1 downto 0);
  signal RectMod8Bit: std_ulogic;
  signal TestPatternMode : std_ulogic;
  signal SignExtendMode  : std_ulogic;
  signal SignAndMagMode  : std_ulogic;
  signal RectValid  : std_ulogic;
  signal UnRectData : std_logic_vector(11 downto 0);
  signal RectData   : std_logic_vector(10 downto 0);
  signal SampleData : std_logic_vector(15 downto 0);
  signal SampleValid: std_ulogic;

  signal RamDataIn      : std_logic_vector(31 downto 0);
  signal RamDataAEn     : std_ulogic;
  signal RamDataCEn     : std_ulogic;
  signal ResetAScanAddr : std_ulogic;
  signal ResetCScanAddr : std_ulogic;
  signal BankSel        : std_ulogic;

  signal IoTx : std_ulogic;
  signal IoCk : std_ulogic;
  signal IoRx : std_ulogic;
  signal Buzz : std_logic_vector(11 downto 0);

  signal InputSelUpdate   : std_ulogic;
  signal FilterCtrlUpdate : std_ulogic;
  signal IpSelReg         : std_logic_vector(31 downto 0);
  signal FilterCtrlReg    : std_logic_vector(15 downto 0);
  signal SIPOUpdate       : std_ulogic;

  signal DdsData   : std_logic_vector(15 downto 0);
  signal DdsWr     : std_ulogic;
  signal DdsBusy   : std_ulogic;
  signal HVDACData : std_logic_vector(15 downto 0);
  signal HVDACWr   : std_ulogic;
  signal HVDACBusy : std_ulogic;

  signal AScanRepRate     : std_logic_vector(23 downto 0);
  signal AScanRange       : std_logic_vector(23 downto 0);
  signal BankSize         : std_logic_vector(30 downto 0);
  signal CScanOffsetAddr  : std_logic_vector(30 downto 0);
  signal StorageMode      : std_logic_vector(1 downto 0);
  signal SetDataReady     : std_ulogic;
  signal SetNewTrigger    : std_ulogic;
  signal SetEarlyTrigError: std_ulogic;
  signal SetDataFullError : std_ulogic;
  signal SomeDataReady    : std_ulogic;
  signal DataReady        : std_ulogic;
  signal EarlyDataReq     : std_ulogic;
  signal ResetSampling    : std_ulogic;

  signal TriggerPulse     : std_ulogic;
  signal DelayedTrigger   : std_ulogic;
  signal AScanStart       : std_ulogic;
  signal AScanDone        : std_ulogic;
  signal SequenceStart    : std_ulogic;

  signal SequenceRepRate  : std_logic_vector(31 downto 0);
  signal SequencesPerBank : std_logic_vector(15 downto 0);
  signal SequenceSteps    : std_logic_vector(4 downto 0);
  signal StartSequence    : std_ulogic;
  signal SequencesInRam   : std_logic_vector(15 downto 0);
  signal SequenceStep     : std_logic_vector(4 downto 0);
  signal TriggerDelay     : std_logic_vector(23 downto 0);
  signal PulseWidth       : std_logic_vector(15 downto 0);
  signal PulseTrain       : std_logic_vector(3 downto 0);
  signal ExtTriggerEn     : std_ulogic;
  signal FreeRunningEn    : std_ulogic;
  signal EncoderTriggerEn : std_ulogic;
  signal ForceTrigger     : std_ulogic;
  signal SyncPulse        : std_ulogic;
  signal SyncPulseEn      : std_ulogic;

  signal GateEnables      : std_logic_vector(7 downto 0);
  signal GateTriggers     : std_logic_vector(15 downto 0);
  signal GateNoTriggers   : std_logic_vector(15 downto 0);
  signal GateUnTriggers   : std_logic_vector(15 downto 0);
  signal GateReTriggers   : std_logic_vector(15 downto 0);

  signal GateSelect       : std_logic_vector(2 downto 0);
  signal GateDistance     : std_ulogic;
  signal GateData         : std_logic_vector(31 downto 0);
  signal GateDataOut      : tGateData14;
  signal GateStart        : tGateData24;
  signal GateStop         : tGateData24;
  signal GateAttrib       : tGateData32;
  signal HoldOff          : std_logic_vector(7 downto 0);

  signal TCGAbsoluteTrig  : std_ulogic;
  signal TCGEnable        : std_ulogic;
  signal TCGBEAGate       : std_logic_vector(2 downto 0);
  signal TCGBEAEnable     : std_ulogic;
  signal TCGPoints        : std_logic_vector(18 downto 0);
  signal TCGSamples       : std_logic_vector(15 downto 0);
  signal BeaSw            : std_ulogic;

  signal EncoderReset     : std_logic_vector(8 downto 0);
  signal EncoderSelect    : std_logic_vector(3 downto 0);
  signal ClicksPerSeq     : std_logic_vector(23 downto 0);
  signal FractClicks      : std_logic_vector(15 downto 0);
  signal EncoderCount0    : std_logic_vector(31 downto 0);
  signal EncoderCount1    : std_logic_vector(31 downto 0);
  signal EncoderCount2    : std_logic_vector(31 downto 0);
  signal EncoderCount3    : std_logic_vector(31 downto 0);
  signal DualEncoderCount : std_logic_vector(31 downto 0);
  signal PulseCount0      : std_logic_vector(31 downto 0);
  signal PulseCount1      : std_logic_vector(31 downto 0);
  signal PulseCount2      : std_logic_vector(31 downto 0);
  signal PulseCount3      : std_logic_vector(31 downto 0);
  signal SequenceActive   : std_ulogic;
  signal CaptureDone      : std_ulogic;
  signal EncoderTrigger   : std_ulogic;

  signal FSerOE     : std_ulogic;
  signal nFSerRClk  : std_ulogic;
  signal nFSerClk   : std_ulogic;
  signal nFSelP20db : std_ulogic;

  signal inAD_Cs    : std_ulogic;
  signal iAD_SClk   : std_ulogic;
  signal inAD_Reset : std_ulogic;

  signal RfrshReq   : std_ulogic;
  signal RfrshDone  : std_ulogic;
  signal SoDimmSize : std_logic_vector(3 downto 0);
  signal SoDimmVal  : std_ulogic;

  signal Test: std_logic_vector(8 downto 0) := (others => '0');

begin

  nReset <= nLRESET;

  -- Local Bus clock buffer
  IBUFG0: IBUFG
    port map(I   => LClk,
             O   => LClkBuf);

  -- Main System Clock LVDS clock buffer
  IBUFGDS0 : IBUFGDS
    generic map (IOSTANDARD => "LVDS_25")
    port map (O => SysClkx2,
              I => AD_DcoP,
              IB => AD_DcoN);

  -- LVDS input buffers for ADC signals
  AdcIBUFDS: for i in 0 to 11 generate
    IBUFDS0 : IBUFDS
      generic map (IOSTANDARD => "LVDS_25")
      port map (O => AdcD(i),
                I => AD_DP(i),
                IB => AD_DN(i));
  end generate;

  IBUFDS0 : IBUFDS
    generic map (IOSTANDARD => "LVDS_25")
    port map (O => AdcOr,
              I => AD_OrP,
              IB => AD_OrN);

  -- IOB FFs for ADC signals
  AdcFF : process (SysClkx2) is
  begin
    if SysClkx2'event and SysClkx2 = '1' then
      AdcD1 <= AdcD;
      AdcOr1 <= AdcOr;
    end if;  
  end process AdcFF;    

  AdcFFSys : process (SysClk) is
  begin
    if SysClk'event and SysClk = '1' then
      AdcD2 <= AdcD1;
    end if;  
  end process AdcFFSys;    

  -- Sample ADC Data for raw ADC data read
  AdcSamp: process(SysClkx2)
  begin
    if SysClkx2'event and SysClkx2 = '1' then
      -- Latch sample data on rising edge of control signal
      if RawAdcRdD(2 downto 1) = "01" then
        Adcsample <= ADCD1;
      end if;

      -- Clock control signal into SysClk domain and detect rising edge
      RawAdcRdD <= RawAdcRdD(1 downto 0) & RawAdcRd;
    end if;
  end process AdcSamp;

  ClkDcmRstGen : SRL16
    generic map(INIT => X"FFFF")
    port map (Q   => Reset,
              A0  => '1',
              A1  => '1',
              A2  => '1',
              A3  => '1',
              CLK => SysClkx2,
              D   => '0');

  SysClkDcm: DCM
    generic map(DLL_FREQUENCY_MODE    => "LOW",
                CLKIN_DIVIDE_BY_2 => TRUE,
                CLKIN_PERIOD => 5.0,
                CLK_FEEDBACK => "1X",
                DUTY_CYCLE_CORRECTION => true)
    port map (CLKIN    => SysClkx2,
              CLKFB    => SysClk,
              DSSEN    => '0',
              PSINCDEC => '0',
              PSEN     => '0',
              PSCLK    => '0',
              RST      => Reset,
              CLK0     => SysClk0,
              CLK90    => open,
              CLK180   => open,
              CLK270   => open,
              CLK2X    => open,
              CLK2X180 => open,
              CLKDV    => open,
              CLKFX    => open,
              CLKFX180 => open,
              LOCKED   => SysClkLocked,
              PSDONE   => open,
              STATUS   => open);

  Clkx2Bufg: BUFG
    port map(I  => SysClk0,
             O  => SysClk);

  -- Data rectifier
  DataRect: DataRectifier
    port map (nReset          => nReset,
              Clk             => SysClk,
              AdcOffset       => AdcOffset,
              DropSamples     => DropSamples,
              Mode            => RectMode,
              Mod8Bit         => RectMod8Bit,
              SignExtendMode  => SignExtendMode,
              SignAndMagMode  => SignAndMagMode,
              DataIn          => AdcD2,
              SampleEn        => SampleValid,
              SampleData      => SampleData,
              DataOut         => UnRectData,
              RectifiedOut    => RectData);

  -- Gates
  Gate0: InterfaceGate
    port map(nReset         => nReset,
             Clk            => SysClk,
             SampleEn       => SampleValid,
             TriggerIn      => DelayedTrigger,
             Enable         => GateEnables(0),
             StartCount     => GateStart(0),
             StopCount      => GateStop(0),
             Threshold      => GateAttrib(1)(10 downto 0),
             TriggerMode    => GateAttrib(1)(20),
             PolarityMode   => GateAttrib(1)(19 downto 18),
             RectifiedData  => RectData,
             PolarityIn     => UnRectData(11),
             GateFiring     => GateTriggers(0), 
             GateFired      => GateUnTriggers(0),
             GateDidNotFire => open,
             GateOutputData => GateDataOut(0));

  Gate1: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(1),
              StartCount     => GateStart(1),
              StopCount      => GateStop(1),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(1)(10 downto 0),
              TriggerNum     => GateAttrib(1)(15 downto 12),
              TriggerMode    => GateAttrib(1)(20),
              ZeroCrossMode  => GateAttrib(1)(16),
              PolarityMode   => GateAttrib(1)(19 downto 18),
              DistMetric     => GateAttrib(1)(22 downto 21),
              PeakSelAmp     => GateAttrib(1)(27 downto 24),
              PeakSelDist    => GateAttrib(1)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(1),
              GateUnTrigger  => GateUnTriggers(1),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(1),
              GateReFire     => GateReTriggers(1),
              GateOutputData => GateDataOut(1));
  
  Gate2: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(2),
              StartCount     => GateStart(2),
              StopCount      => GateStop(2),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(2)(10 downto 0),
              TriggerNum     => GateAttrib(2)(15 downto 12),
              TriggerMode    => GateAttrib(2)(20),
              ZeroCrossMode  => GateAttrib(2)(16),
              PolarityMode   => GateAttrib(2)(19 downto 18),
              DistMetric     => GateAttrib(2)(22 downto 21),
              PeakSelAmp     => GateAttrib(2)(27 downto 24),
              PeakSelDist    => GateAttrib(2)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(2),
              GateUnTrigger  => GateUnTriggers(2),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(2),
              GateReFire     => GateReTriggers(2),
              GateOutputData => GateDataOut(2));

  Gate3: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(3),
              StartCount     => GateStart(3),
              StopCount      => GateStop(3),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(3)(10 downto 0),
              TriggerNum     => GateAttrib(3)(15 downto 12),
              TriggerMode    => GateAttrib(3)(20),
              ZeroCrossMode  => GateAttrib(3)(16),
              PolarityMode   => GateAttrib(3)(19 downto 18),
              DistMetric     => GateAttrib(3)(22 downto 21),
              PeakSelAmp     => GateAttrib(3)(27 downto 24),
              PeakSelDist    => GateAttrib(3)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(3),
              GateUnTrigger  => GateUnTriggers(3),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(3),
              GateReFire     => GateReTriggers(3),
              GateOutputData => GateDataOut(3));
  Gate4: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(4),
              StartCount     => GateStart(4),
              StopCount      => GateStop(4),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(4)(10 downto 0),
              TriggerNum     => GateAttrib(4)(15 downto 12),
              TriggerMode    => GateAttrib(4)(20),
              ZeroCrossMode  => GateAttrib(4)(16),
              PolarityMode   => GateAttrib(4)(19 downto 18),
              DistMetric     => GateAttrib(4)(22 downto 21),
              PeakSelAmp     => GateAttrib(4)(27 downto 24),
              PeakSelDist    => GateAttrib(4)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(4),
              GateUnTrigger  => GateUnTriggers(4),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(4),
              GateReFire     => GateReTriggers(4),
              GateOutputData => GateDataOut(4));

  Gate5: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(5),
              StartCount     => GateStart(5),
              StopCount      => GateStop(5),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(5)(10 downto 0),
              TriggerNum     => GateAttrib(5)(15 downto 12),
              TriggerMode    => GateAttrib(5)(20),
              ZeroCrossMode  => GateAttrib(5)(16),
              PolarityMode   => GateAttrib(5)(19 downto 18),
              DistMetric     => GateAttrib(5)(22 downto 21),
              PeakSelAmp     => GateAttrib(5)(27 downto 24),
              PeakSelDist    => GateAttrib(5)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(5),
              GateUnTrigger  => GateUnTriggers(5),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(5),
              GateReFire     => GateReTriggers(5),
              GateOutputData => GateDataOut(5));

  Gate6: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(6),
              StartCount     => GateStart(6),
              StopCount      => GateStop(6),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(6)(10 downto 0),
              TriggerNum     => GateAttrib(6)(15 downto 12),
              TriggerMode    => GateAttrib(6)(20),
              ZeroCrossMode  => GateAttrib(6)(16),
              PolarityMode   => GateAttrib(6)(19 downto 18),
              DistMetric     => GateAttrib(6)(22 downto 21),
              PeakSelAmp     => GateAttrib(6)(27 downto 24),
              PeakSelDist    => GateAttrib(6)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(6),
              GateUnTrigger  => GateUnTriggers(6),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(6),
              GateReFire     => GateReTriggers(6),
              GateOutputData => GateDataOut(6));

  Gate7: Gate
    port map (nReset         => nReset,
              Clk            => SysClk,
              SampleEn       => SampleValid,
              TriggersIn     => GateTriggers,
              NoTriggersIn   => GateNoTriggers,
              Enable         => GateEnables(7),
              StartCount     => GateStart(7),
              StopCount      => GateStop(7),
              ForceStop      => AScanDone,
              Threshold      => GateAttrib(7)(10 downto 0),
              TriggerNum     => GateAttrib(7)(15 downto 12),
              TriggerMode    => GateAttrib(7)(20),
              ZeroCrossMode  => GateAttrib(7)(16),
              PolarityMode   => GateAttrib(7)(19 downto 18),
              DistMetric     => GateAttrib(7)(22 downto 21),
              PeakSelAmp     => GateAttrib(7)(27 downto 24),
              PeakSelDist    => GateAttrib(7)(31 downto 28),
              Holdoff        => Holdoff,
              SampleData     => UnRectData,
              RectifiedData  => RectData,
              StoreNoTrig    => '0',
              GateDistFire   => open,
              GateDistClear  => open,
              GateFiring     => GateTriggers(7),
              GateUnTrigger  => GateUnTriggers(7),
              GateFired      => open,
              GateDidNotFire => GateNoTriggers(7),
              GateReFire     => GateReTriggers(7),
              GateOutputData => GateDataOut(7));

  GateEnables <= (0 => GateAttrib(0)(23),
                  1 => GateAttrib(1)(23),
                  2 => GateAttrib(2)(23),
                  3 => GateAttrib(3)(23),
                  4 => GateAttrib(4)(23),
                  5 => GateAttrib(5)(23),
                  6 => GateAttrib(6)(23),
                  7 => GateAttrib(7)(23));

  ResSel: GateResultSelect
    port map (nReset        => nReset,
              SysClk        => SysClk,
              SampleEn      => SampleValid,
              TriggersIn    => GateTriggers,
              UnTriggersIn  => GateUnTriggers,
              NoTriggersIn  => GateNoTriggers,
              ReTriggersIn  => GateReTriggers,
              GateSelect    => GateSelect,
              GateDistance  => GateDistance,
              GateDataIn    => GateDataOut,
--              GateDataIn    => GateStart,
--              GateDistIn    => GateStop,
              GateData      => GateData);

  -- Sample RAM write control
  RamWrite: RamWriteCtrl
  port map (nReset            => nReset,
            SysClk            => SysClk,
            LClk              => LClkBuf,
            -- Sample data
            SampleIn          => SampleData,
            SampleValid       => SampleValid,
            TestMode          => TestPatternMode,
            AScanStart        => AScanStart,
            StartCapture      => DelayedTrigger,
            SequenceActive    => SequenceActive,
            AScanDone         => AScanDone,
            -- Encoder and Gata Data
            EncoderCount0     => EncoderCount0,
            EncoderCount1     => EncoderCount1,
            EncoderCount2     => EncoderCount2,
            EncoderCount3     => EncoderCount3,
            DualEncoderCount  => DualEncoderCount,
            PulseCount0       => PulseCount0,
            PulseCount1       => PulseCount1,
            PulseCount2       => PulseCount2,
            PulseCount3       => PulseCount3,
            GateData          => GateData,
            GateSelect        => GateSelect,
            GateDistance      => GateDistance,
            -- RAM write controls out
            WriteData         => RamDataIn,
            WriteAEn          => RamDataAEn,
            WriteCEn          => RamDataCEn,
            ResetAScanAddr    => ResetAScanAddr,
            ResetCScanAddr    => ResetCScanAddr,
            BankSel           => BankSel,
            -- Register signals
            GateEnable        => GateEnables,
            AScanRange        => AScanRange,
            SequencesPerBank  => SequencesPerBank,
            SequenceSteps     => SequenceSteps,
            StartSequence     => StartSequence,
            SequencesInRam    => SequencesInRam,
            SequenceStep      => SequenceStep,
            StorageMode       => StorageMode,
            SetDataReady      => SetDataReady,
            SetNewTrigger     => SetNewTrigger,
            SetEarlyTrigError => SetEarlyTrigError,
            SetDataFullError  => SetDataFullError,
            SomeDataReady     => SomeDataReady,
            DataReady         => DataReady,
            EarlyDataReq      => EarlyDataReq,
            ResetSampling     => ResetSampling);

  -- Sample RAM arbitration
  RamArb: RamArbitrate
    port map (nReset          => nReset,
              RamClk          => RamClk,
              -- SDRAM interface i/o
              RamDIn          => RamDIn,
              RamDMask        => RamDMask,
              RamDOut         => RamDOut,
              RamAddr         => RamAddr,
              RamWr           => RamWr,
              RamWrPop        => RamWrPop,
              RamRd           => RamRd,
              RamRdPush       => RamRdPush,
              RamAck          => RamAck,
              -- Local Processor bus
              LClk            => LClkBuf,
              LWrData         => LRamWrData,
              LRdData         => LRamRdData,
              LAddr           => LRamAddr,
              LWr             => LRamWr,
              LRd             => LRamRd,
              LAck            => LRamAck,
              -- Data input
              SysClk          => SysClk,
              DataIn          => RamDataIn,
              DataWrA         => RamDataAEn,
              DataWrC         => RamDataCEn,
              ResetAScanAddr  => ResetAScanAddr,
              ResetCScanAddr  => ResetCScanAddr,
              BankSel         => BankSel,
              -- Register signals
              CScanOffsetAddr => CScanOffsetAddr,
              BankSize        => BankSize,
              ResetSampling   => ResetSampling);

  -- DDR2 RAM interface
  RAMIf: SDRAMIf
    port map (ClkIn     => LClkBuf,
              nReset    => nReset,
              MemClkOut => RamClk,
              -- User i/o
              uDIn      => RamDIn,
              uDMask    => RamDMask,
              uDOut     => RamDOut,
              uAddr     => RamAddr,
              uWr       => RamWr,
              uWrPop    => RamWrPop,
              uRd       => RamRd,
              uRdPush   => RamRdPush,
              uAck      => RamAck,
              -- SDRAM
              SR_Ck     => SR_Ck,
              nSR_Ck    => nSR_Ck,
              SR_Cke    => SR_Cke,
              SR_Dq     => SR_Dq,
              SR_Dqs    => SR_Dqs,
              nSR_Dqs   => nSR_Dqs,
              SR_DM     => SR_DM,
              SR_A      => SR_A,
              SR_Ba     => SR_Ba,
              nSR_We    => nSR_We,
              nSR_Ras   => nSR_Ras,
              nSR_Cas   => nSR_Cas,
              SR_ODT    => SR_ODT,
              nSR_S     => nSR_S,
              SR_SCL    => SR_SCL,
              SR_SDA    => SR_SDA,
              SR_SA     => SR_SA,
              RstDqsDiv => SR_DqsDiv,
              RfrshReq  => RfrshReq,
              RfrshDone => RfrshDone,
              SoDimmSize=> SoDimmSize,
              SoDimmVal => SoDimmVal);


  -- Tristate data i/o
  LD <= LDOut when nLDOe = '0' else (others => 'Z');

  -- Tie-off unused LBUS outputs
  LWnR <= 'Z';
  DP <= (others => 'Z');
  LA <= (others => 'Z');
  nADS <= 'Z';
  nBLAST <= 'Z';
  nWAIT <= 'Z';
  nLBE  <= (others => 'Z');

  nBIGEND <= 'Z';
  nCCS <= 'Z';
  USERi <= 'Z';
  nPMEIN <= 'Z';
  nDREQ0 <= 'Z';
  nDREQ1 <= 'Z';

  -- Local bus interface
  LBus: DspLBusInterface
    port map (-- Local bus
              nReset            => nReset,
              LClk              => LClkBuf,
              LWnR              => LWnR,
              LDIn              => LD,
              LDOut             => LDOut,
              nLDOe             => nLDOe,
              LAin              => LA,
              nAds              => nADS,
              nBLast            => nBLAST,
              nReady            => nREADY,
              nBTerm            => nBTERM,
              LHold             => LHOLD,
              LHoldA            => LHOLDA,
              BReqi             => BREQi,
              nLINTi            => nLINTi,
              -- TCG RAM processor bus
              TCGRamWrData      => TCGRamWrData,
              TCGRamRdData      => TcgDacD,
              TCGRamAddr        => TCGRamAddr,
              TCGRamWr          => TCGRamWr,
              TCGRamRd          => TCGRamRd,
              TCGRamAck         => TCGRamAck,
              -- SDRAM processor bus
              LRamWrData        => LRamWrData,
              LRamRdData        => LRamRdData,
              LRamAddr          => LRamAddr,
              LRamWr            => LRamWr,
              LRamRd            => LRamRd,
              LRamAck           => LRamAck,
              -- ADC controls
              RawAdcRd          => RawAdcRd,
              RawAdcData        => AdcSample,
              AdcOffset         => AdcOffset,
              DropSamples       => DropSamples,
              RectMode          => RectMode,
              RectMod8Bit       => RectMod8Bit,
              TestPatternMode   => TestPatternMode,
              SignExtendMode    => SignExtendMode,
              SignAndMagMode    => SignAndMagMode,
              AdcSerWr          => AdcSerWr,
              AdcSerInst        => AdcSerInst,
              AdcSerDOut        => AdcSerDOut,
              AdcSerDIn         => AdcSerDIn,
              AdcResetWr        => AdcResetWr,
              AdcBusy           => AdcBusy,
              -- DDS  Controls
              DdsData           => DdsData,
              DdsWr             => DdsWr,
              DdsBusy           => DdsBusy,
              DdsSleep          => DdsSleep,
              DdsReset          => DdsReset,
              DdsPSelect        => DdsPSelect,
              DdsFSelect        => DdsFSelect,
              nDdsOscInh        => nDdsOscInh,
              -- HV Controls
              HVDACData         => HVDACData,
              HVDACWr           => HVDACWr,
              HVDACBusy         => HVDACBusy,
              nHVEnable         => nHVEnable,
              nHVDisChg         => nHVDisChg,
              HVFeedback        => HVFeedback,
              -- Gate controls
              Holdoff           => Holdoff,
              GateStart         => GateStart,
              GateStop          => GateStop,
              GateAttrib        => GateAttrib,
              -- Data capture controls
              AScanRepRate      => AScanRepRate,
              AScanRange        => AScanRange,
              BankSize          => BankSize,
              BankSel           => BankSel,
              CScanOffsetAddr   => CScanOffsetAddr,
              StorageMode       => StorageMode,
              SetDataReady      => SetDataReady,
              SetNewTrigger     => SetNewTrigger,
              SetEarlyTrigError => SetEarlyTrigError,
              SetDataFullError  => SetDataFullError,
              SomeDataReady     => SomeDataReady,
              DataReady         => DataReady,
              EarlyDataReq      => EarlyDataReq,
              ResetSampling     => ResetSampling,
              -- Sequence controls
              SequenceRepRate   => SequenceRepRate,
              SequencesPerBank  => SequencesPerBank,
              SequenceSteps     => SequenceSteps,
              StartSequence     => StartSequence,
              SequencesInRam    => SequencesInRam,
              SequenceStep      => SequenceStep,
              -- Trigger pulse controls
              TriggerDelay      => TriggerDelay,
              PulseWidth        => PulseWidth,
              PulseTrain        => PulseTrain,
              ExtTriggerEn      => ExtTriggerEn,
              FreeRunningEn     => FreeRunningEn,
              EncoderTriggerEn  => EncoderTriggerEn,
              ForceTrigger      => ForceTrigger,
              SyncPulseEn       => SyncPulseEn,
              -- TCG controls
              TCGAbsoluteTrig   => TCGAbsoluteTrig,
              TCGEnable         => TCGEnable,
              TCGBEAGate        => TCGBEAGate,
              TCGBEAEnable      => TCGBEAEnable,
              TCGPoints         => TCGPoints,
              TCGSamples        => TCGSamples,
              -- Encoder Controls
              EncoderReset      => EncoderReset,
              EncoderSelect     => EncoderSelect,
              ClicksPerSeq      => ClicksPerSeq,
              FractClicks       => FractClicks,
              EncoderCount0     => EncoderCount0,
              EncoderCount1     => EncoderCount1,
              EncoderCount2     => EncoderCount2,
              EncoderCount3     => EncoderCount3,
              DualEncoderCount  => DualEncoderCount,
              PulseCount0       => PulseCount0,
              PulseCount1       => PulseCount1,
              PulseCount2       => PulseCount2,
              PulseCount3       => PulseCount3,
              -- Misc Controls
              InputSelUpdate    => InputSelUpdate,
              FilterCtrlUpdate  => FilterCtrlUpdate,
              IpSelReg          => IpSelReg,
              FilterCtrlReg     => FilterCtrlReg,
              Relay             => Relay,
              Ident             => Ident,
              SoDimmSize        => SoDimmSize,
              SoDimmVal         => SoDimmVal);

  SIPOUpdate <= InputSelUpdate or FilterCtrlUpdate;

  BeaCtrl: BeaSwitch
    port map (nReset         => nReset,
              Clk            => SysClk,
              TriggersIn     => GateTriggers(7 downto 0),
              TriggerNum     => TCGBEAGate,
              BeaEnable      => TCGBEAEnable,
              BeaSwitch      => BeaSw);

  -- Input Sel/Filter control
  IpSelFilt: SIPOCtrl
    generic map(gHCycle => 10)
    port map (nReset        => nReset,
              Clk           => LClkBuf,
              Update        => SIPOUpdate,
              IpSelReg      => IpSelReg,
              FilterCtrlReg => FilterCtrlReg,
              Bea           => BeaSw,
              --
              FSerData      => FSerData,
              nFSerOE       => FSerOE,
              FSerRClk      => nFSerRClk,
              FSerClk       => nFSerClk,
              FSel0db       => FSel0db,
              FSelN20db     => FSelN20db,
              FSelN40db     => FSelN40db,
              FSelP20db     => nFSelP20db);

  -- Analog switches act as inverters so invert signals
  -- except data as that is ivnerted twice
  nFSerOE  <= not FSerOE;
  FSerRClk <= not nFSerRClk;
  FSerClk <= not nFSerClk;
  FSelP20db <= not nFSelP20db;

  -- ADC SPI interface
  AdcSpi: SpiAD
    generic map(gHCycle => 10)
    port map (nReset   => nReset,
              Clk      => LClkBuf,
              SerWr    => AdcSerWr,
              Inst     => AdcSerInst,
              DataIn   => AdcSerDIn,
              DataOut  => AdcSerDOut,
              ResetWr  => AdcResetWr,
              Busy     => AdcBusy,
              --
              CSB      => inAD_Cs,
              SClk     => iAD_SClk,
              SDIO     => AD_SDio,
              Reset    => inAD_Reset);

  nAD_Cs <= inAD_Cs;
  AD_SClk <= iAD_SClk;
  nAD_Reset <= inAD_Reset;

  -- DDS control
  DdsSpi: Spi16
    generic map(gHCycle => 2)
    port map (nReset    => nReset,
              Clk       => LClkBuf,
              Wr        => DdsWr,
              Data      => DdsData,
              Busy      => DdsBusy,
              --
              SClk      => DdsSClk,
              SData     => DdsSData,
              nSync     => DdsFSync);

  -- HV DAC control
  HVSpi: Spi16
    generic map(gHCycle => 2)
    port map (nReset    => nReset,
              Clk       => LClkBuf,
              Wr        => HVDACWr,
              Data      => HVDACData,
              Busy      => HVDACBusy,
              --
              SClk      => HVSClk,
              SData     => HVSDIn,
              nSync     => nHVSync);

  -- Trigger pulse generation
  TrigGen: TriggerGenerator
    port map (nReset            => nReset,
              Clk               => SysClk,
              LClk              => LClkBuf,
              -- Register interface signals
              AScanRepRate      => AScanRepRate,
              SequenceRepRate   => SequenceRepRate,
              SequenceSteps     => SequenceSteps,
              StartSequence     => StartSequence,
              TriggerDelay      => TriggerDelay,
              PulseWidth        => PulseWidth,
              PulseTrain        => PulseTrain,
              ExtTriggerEn      => ExtTriggerEn,
              FreeRunningEn     => FreeRunningEn,
              EncoderTriggerEn  => EncoderTriggerEn,
              -- Trigger/Pulse i/o
              ForceTrigger      => ForceTrigger,
              ExtTriggerIn      => FTrigger,
              EncoderTriggerIn  => EncoderTrigger,
              TriggerPulse      => TriggerPulse,
              DelayedTrigger    => DelayedTrigger,
              AScanStart        => AScanStart,
              SequenceStart     => SequenceStart,
              SequenceActive    => SequenceActive,
              CaptureDone       => CaptureDone);

  PulsePFet <= TriggerPulse;
  PulseNFet <= TriggerPulse;

  GateTriggers(15) <= DelayedTrigger;
  GateNoTriggers(15) <= '0';
  GateNoTriggers(0) <= '0';

  SyncPulse <= SequenceStart and SyncPulseEn;

  -- Produce 80us pulse on the sync output for each B-Scan
  SyncExtender: StrobeExtender
    generic map(gLfsrBits => 14)
    port map(nReset    => nReset,
             Clk       => SysClk,
             StrobeIn  => SyncPulse,
             StrobeOut => FSync);


  OBUFDS0 : OBUFDS
    generic map ( IOSTANDARD => "LVDS_25")
    port map (O => PulsePFetP,
              OB => PulsePFetN,
              I => PulsePFet);
  OBUFDS1 : OBUFDS
    generic map ( IOSTANDARD => "LVDS_25")
    port map (O => PulseNFetP,
              OB => PulseNFetN,
              I => PulseNFet);

  -- TCG control
  TcgDacD <= TCGRamWrData when nTcgDacDOe = '0' else (others => 'Z');

  TCG: TCGControl
  port map (nReset          => nReset,
            SysClk          => SysClk,
            TCGEnable       => TCGEnable,
            TCGAbsoluteTrig => TCGAbsoluteTrig,
            TCGPoints       => TCGPoints,
            TCGSamples      => TCGSamples,
            TrigAbsolute    => GateTriggers(15),
            TrigInterface   => GateTriggers(1),
            SampleEn        => SampleValid,
            CaptureDone     => CaptureDone,
            -- LBUS RAM access Signals
            LClk            => LClkBuf,
            TCGRAMWr        => TCGRamWr,
            TCGRAMRd        => TCGRamRd,
            TCGRAMAck       => TCGRamAck,
            TCGRAMAddr      => TCGRamAddr,
            -- DAC SRAM Signals
            nTcgDacDOe      => nTcgDacDOe,
            TcgDacA         => TcgDacA,
            nTcgDacCs       => nTcgDacCs,
            nTcgDacBLE      => nTcgDacBLE,
            nTcgDacBHE      => nTcgDacBHE,
            nTcgDacOe       => nTcgDacOe,
            nTcgDacWr       => nTcgDacWr,
            -- Actual DAC Signals
            TcgDacSleep     => TcgDacSleep,
            TcgDacClk       => TcgDacClk);

  -- Encoder interface
  Encoder: EncoderCounter
    port map (-- Local bus
              nReset          => nReset,
              LClk            => LClkBuf,
              -- Register interface signals
              EncoderReset    => EncoderReset,
              EncoderSelect   => EncoderSelect,
              ClicksPerSeq  => ClicksPerSeq,
              FractClicks     => FractClicks,
              EncoderCount0   => EncoderCount0,
              EncoderCount1   => EncoderCount1,
              EncoderCount2   => EncoderCount2,
              EncoderCount3   => EncoderCount3,
              DualEncoderCount=> DualEncoderCount,
              PulseCount0     => PulseCount0,
              PulseCount1     => PulseCount1,
              PulseCount2     => PulseCount2,
              PulseCount3     => PulseCount3,
              -- Encoder/Pulse inputs
              EncoderPhA      => OpPha,
              EncoderPhB      => OpPhb,
              PulseIn         => OpIndex,
              -- Seq control
              SeqActiveIn   => SequenceActive,
              SeqTriggerOut => EncoderTrigger,
              SeqTriggerIn  => '0');

  -- Tie-off processor ram signals
  MRamIO <= (others => '0');
  MRamA <= (others => '0');
  nMRamCs <= '1';
  nMRamWe <= '1';
  nMRamOe <= '1';
  nMRamBle <= '1';
  nMRamBhe <= '1';

  -- Tie-off Ethernet PHY signals
  nPhyReset <= nLRESET;
  PhyGTxClk <= '0';
  --PhyTxClk;
  PhyTxD <= (others => '0');
  --PhyTxEn;
  --PhyTxEr;
  --PhyRxD;
  --PhyRxCrs;
  --PhyRxCol;
  --PhyRxClk;
  --PhyRxDv;
  --PhyRxEr;
  PhyAd <= "00000";
  PhyMdc <= '0';
  -- PhyMdio;
  PhyMdixEn  <= '0';
  PhyMultiEn <= '0';
  PhyAnEn <= '0';
  PhyDuplex <= '0';
  PhySpeed <= "00";
  --nPhyInt;

  -- Tie off i/o

  ChIBUFDS: for i in 0 to 7 generate
    ChIBUFDS1 : OBUFDS
      generic map ( IOSTANDARD => "LVDS_25")
      port map (O => ChTxP(i),
                OB => ChTxN(i),
                I => '0');
    ChIBUFDS2 : OBUFDS
      generic map ( IOSTANDARD => "LVDS_25")
      port map (O => ChCkP(i),
                OB => ChCkN(i),
                I => '0');
    ChIBUFDS3 : OBUFDS
      generic map ( IOSTANDARD => "LVDS_25")
      port map (O => ChRxP(i),
                OB => ChRxN(i),
                I => '0');
  end generate;

  OutTxIBUFDS : OBUFDS
    generic map ( IOSTANDARD => "LVDS_25")
    port map (O => IoOutTxP,
              OB => IoOutTxN,
              I => '0');
  OutCkIBUFDS : OBUFDS
    generic map ( IOSTANDARD => "LVDS_25")
    port map (O => IoOutCkP,
              OB => IoOutCkN,
              I => '0');
  OutRxIBUFDS : OBUFDS
    generic map ( IOSTANDARD => "LVDS_25")
    port map (O => IoOutRxP,
              OB => IoOutRxN,
              I => '0');

  InTxIBUFDS : IBUFDS
    generic map (IOSTANDARD => "LVDS_25")
    port map (O => IoTx,
              I => IoInTxP,
              IB => IoInTxN);

  InCkIBUFDS : IBUFDS
    generic map (IOSTANDARD => "LVDS_25")
    port map (O => IoCk,
              I => IoInCkP,
              IB => IoInCkN);

  InRxIBUFDS : IBUFDS
    generic map (IOSTANDARD => "LVDS_25")
    port map (O => IoRx,
              I => IoInRxP,
              IB => IoInRxN);

  nSDVterm <= '0';

  -- Buzz
  -- single ended inputs
  Buzz(7 downto 0) <= BuzzP(7 downto 0) or BuzzN(7 downto 0);

  -- LVDS inputs
  BuzzIBUFDS: for i in 8 to 11 generate
    IBUFDS1 : IBUFDS
      generic map (IOSTANDARD => "LVDS_25")
      port map (O => Buzz(i),
                I => BuzzP(i),
                IB => BuzzN(i));
  end generate;

  DBugD <= (0 => ForceTrigger,
            1 => RamDataAEn,
            2 => ResetAScanAddr,
            3 => BankSel);

end architecture Str;