---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: DspFpgaPkg.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- VHDL package for DSP FPGA
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

package DspFpgaPkg is

  -- cFpgaRevision should be updated with the current revision number
  constant cFpgaRevision: std_logic_vector(11 downto 0) := X"030";  -- From 0.01 to F.FF
  constant cFpgaVersion: std_logic_vector(3 downto 0) := X"D";  -- From 0 to F

  -----------------------------------------------------------------------------
  -- Record to define the parameters for a register
  type tRegParam is record
    Address: std_logic_vector(31 downto 0);
    ResetVal: std_logic_vector(31 downto 0);
    WriteMask: std_logic_vector(31 downto 0);
    ReadMask: std_logic_vector(31 downto 0);
    RegCount: integer;
  end record;

  -- Register indexes
  constant cDspBase             : integer := 0;
  -- Sequence Step registers
  constant cInputSel            : integer := 1;
  constant cFilterCtrl          : integer := 2;
  constant cRectifierMode       : integer := 3;
  constant cDropSamples         : integer := 4;
  constant cAScanRepRate        : integer := 5;
  constant cPulseWidth          : integer := 6;
  constant cPulseTrain          : integer := 7;
  constant cAScanRange          : integer := 8;
  constant cTCGConfigure        : integer := 9;
  constant cTCGPoints           : integer := 10;
  constant cTCGNoOfSamples      : integer := 11;
  constant cTriggerDelay        : integer := 12;
  constant cSeqStepCtrl         : integer := 13;
  constant cAdcOffset           : integer := 14;
  constant cGateStart           : integer := 15;
  constant cGateStop            : integer := 16;
  constant cGateAttributes      : integer := 17;
  constant cGateTrailFlankHO    : integer := 18;
  --
  constant cCheckReg            : integer := 19;
  constant cADCSerialCtrl       : integer := 20;
  constant cRawADCData          : integer := 21;
  constant cDDSCtrl             : integer := 22;
  constant cHVDACData           : integer := 23;
  constant cHVDACCtrl           : integer := 24;
  constant cHVCtrl              : integer := 25;
  constant cRAMBankSize         : integer := 26;
  constant cSeqRepRate          : integer := 27;
  constant cSeqPerBank          : integer := 28;
  constant cRAMControl          : integer := 29;
  constant cEncoderClickPerSeq  : integer := 30;
  constant cFractEncClickPerSeq : integer := 31;
  constant cSeqTriggerEncSel    : integer := 32;
  constant cSeqTriggerMode      : integer := 33;
  constant cSeqTriggerForce     : integer := 34;
  constant cSeqInRam            : integer := 35;
  constant cSampleCtrl          : integer := 36;
  constant cCScanDataRamOffset  : integer := 37;
  constant cDataSamplingStatus  : integer := 38;
  constant cRAMPageOffset       : integer := 39;
  constant cShaftEncoder0Op     : integer := 40;
  constant cShaftEncoder1Op     : integer := 41;
  constant cShaftEncoder2Op     : integer := 42;
  constant cShaftEncoder3Op     : integer := 43;
  constant cDualEncoderCounter  : integer := 44;
  constant cDigIOPulseCounter0  : integer := 45;
  constant cDigIOPulseCounter1  : integer := 46;
  constant cDigIOPulseCounter2  : integer := 47;
  constant cDigIOPulseCounter3  : integer := 48;
  constant cRelayCtrl           : integer := 49;
  constant cSeqCtrl             : integer := 50;
  constant cMultiBoardCtrl      : integer := 51;
  --
  constant cDspFpgaVer          : integer := 52;

  constant cLastReg             : integer := cDspFpgaVer;
  constant cLastSeqReg          : integer := cGateTrailFlankHO;

  -- Register Addresses
  constant cDspBaseAddr             : std_logic_vector(31 downto 0) := x"00301000";
  constant cInputSelAddr            : std_logic_vector(31 downto 0) := x"00301000";
  constant cFilterCtrlAddr          : std_logic_vector(31 downto 0) := x"00301004";
  constant cRectifierModeAddr       : std_logic_vector(31 downto 0) := x"00301008";
  constant cDropSamplesAddr         : std_logic_vector(31 downto 0) := x"0030100C";
  constant cAScanRepRateAddr        : std_logic_vector(31 downto 0) := x"00301010";
  constant cPulseWidthAddr          : std_logic_vector(31 downto 0) := x"00301014";
  constant cPulseTrainAddr          : std_logic_vector(31 downto 0) := x"00301018";
  constant cAScanRangeAddr          : std_logic_vector(31 downto 0) := x"0030101C";
  constant cTCGConfigureAddr        : std_logic_vector(31 downto 0) := x"00301020";
  constant cTCGPointsAddr           : std_logic_vector(31 downto 0) := x"00301024";
  constant cTCGNoOfSamplesAddr      : std_logic_vector(31 downto 0) := x"00301028";
  constant cTriggerDelayAddr        : std_logic_vector(31 downto 0) := x"0030102C";
  constant cSeqStepCtrlAddr         : std_logic_vector(31 downto 0) := x"00301030";
  constant cAdcOffsetAddr           : std_logic_vector(31 downto 0) := x"00301034";
  constant cGateStartAddr           : std_logic_vector(31 downto 0) := x"00301040"; -- 8 Registers
  constant cGateStopAddr            : std_logic_vector(31 downto 0) := x"00301060"; -- 8 Registers
  constant cGateAttributesAddr      : std_logic_vector(31 downto 0) := x"00301080"; -- 8 Registers
  constant cGateTrailFlankHOAddr    : std_logic_vector(31 downto 0) := x"003010A0";
  --
  constant cCheckRegAddr            : std_logic_vector(31 downto 0) := x"00305000";
  constant cADCSerialCtrlAddr       : std_logic_vector(31 downto 0) := x"00305004";
  constant cRawADCDataAddr          : std_logic_vector(31 downto 0) := x"00305008";
  constant cDDSCtrlAddr             : std_logic_vector(31 downto 0) := x"0030500C";
  constant cHVDACDataAddr           : std_logic_vector(31 downto 0) := x"00305010";
  constant cHVDACCtrlAddr           : std_logic_vector(31 downto 0) := x"00305014";
  constant cHVCtrlAddr              : std_logic_vector(31 downto 0) := x"00305018";
  constant cRAMBankSizeAddr         : std_logic_vector(31 downto 0) := x"0030501C";
  constant cSeqRepRateAddr          : std_logic_vector(31 downto 0) := x"00305020";
  constant cSeqPerBankAddr          : std_logic_vector(31 downto 0) := x"00305024";
  constant cRAMControlAddr          : std_logic_vector(31 downto 0) := x"00305028";
  constant cEncoderClickPerSeqAddr  : std_logic_vector(31 downto 0) := x"0030502C";
  constant cFractEncClickPerSeqAddr : std_logic_vector(31 downto 0) := x"00305030";
  constant cSeqTriggerEncSelAddr    : std_logic_vector(31 downto 0) := x"00305034";
  constant cSeqTriggerModeAddr      : std_logic_vector(31 downto 0) := x"00305038";
  constant cSeqTriggerForceAddr     : std_logic_vector(31 downto 0) := x"0030503C";
  constant cSeqInRamAddr            : std_logic_vector(31 downto 0) := x"00305040";
  constant cSampleCtrlAddr          : std_logic_vector(31 downto 0) := x"00305044";
  constant cCScanDataRamOffsetAddr  : std_logic_vector(31 downto 0) := x"00305048";
  constant cDataSamplingStatusAddr  : std_logic_vector(31 downto 0) := x"0030504C";
  constant cRAMPageOffsetAddr       : std_logic_vector(31 downto 0) := x"00305050";
  constant cShaftEncoder0OpAddr     : std_logic_vector(31 downto 0) := x"00305060";
  constant cShaftEncoder1OpAddr     : std_logic_vector(31 downto 0) := x"00305064";
  constant cShaftEncoder2OpAddr     : std_logic_vector(31 downto 0) := x"00305068";
  constant cShaftEncoder3OpAddr     : std_logic_vector(31 downto 0) := x"0030506C";
  constant cDualEncoderCounterAddr  : std_logic_vector(31 downto 0) := x"00305070";
  constant cDigIOPulseCounter0Addr  : std_logic_vector(31 downto 0) := x"00305074";
  constant cDigIOPulseCounter1Addr  : std_logic_vector(31 downto 0) := x"00305078";
  constant cDigIOPulseCounter2Addr  : std_logic_vector(31 downto 0) := x"0030507C";
  constant cDigIOPulseCounter3Addr  : std_logic_vector(31 downto 0) := x"00305080";
  constant cRelayCtrlAddr           : std_logic_vector(31 downto 0) := x"003050A0";
  constant cSeqCtrlAddr             : std_logic_vector(31 downto 0) := x"003050A4";
  constant cMultiBoardCtrlAddr      : std_logic_vector(31 downto 0) := x"003050A8";
  --
  constant cDspFpgaVerAddr          : std_logic_vector(31 downto 0) := x"00305FFC";

  constant cDspRegMask              : std_logic_vector(31 downto 0) := x"FFFFF000";
  constant cDspRegOffsetBits        : integer := 15;
  constant cDspSeqRegOffsetBits     : integer := 8;

  constant cTCGRAMAddr              : std_logic_vector(31 downto 0) := x"00000000";
  constant cTCGRAMOffsetBits        : integer := 20; -- 0x0000_0000 - 0x000F_FFFF = 256KDWords
  constant cSampRAMAddr             : std_logic_vector(31 downto 0) := x"00400000";
  constant cSampRAMOffsetBits       : integer := 22; -- 0x0040_0000 - 0x007F_FFFF = 4MBytes

  -- Type to hold array of registers
  type tRegSet is array(0 to cLastReg) of tRegParam;

  -- Constant definitions for registers                      Reset        Write        Read       RegCount
  constant cRegSet: tRegSet := ((cDspBaseAddr,             x"00000000", x"00000000", x"00000000", 0), 
                                (cInputSelAddr,            x"00000000", x"FF7F7FFF", x"FF7F7FFF", 1), 
                                (cFilterCtrlAddr,          x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cRectifierModeAddr,       x"00000000", x"00000007", x"00000007", 1),
                                (cDropSamplesAddr,         x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cAScanRepRateAddr,        x"00000000", x"00FFFFFF", x"00FFFFFF", 1),
                                (cPulseWidthAddr,          x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cPulseTrainAddr,          x"00000000", x"0000000F", x"0000000F", 1),
                                (cAScanRangeAddr,          x"00000000", x"00FFFFFF", x"00FFFFFF", 1),
                                (cTCGConfigureAddr,        x"00000000", x"00000F03", x"00000F03", 1),
                                (cTCGPointsAddr,           x"00000000", x"0007FFFF", x"0007FFFF", 1),
                                (cTCGNoOfSamplesAddr,      x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cTriggerDelayAddr,        x"00000000", x"00FFFFFF", x"00FFFFFF", 1),
                                (cSeqStepCtrlAddr,         x"00000000", x"00000001", x"00000001", 1),
                                (cAdcOffsetAddr,           x"00000000", x"00001FFF", x"00001FFF", 1),
                                (cGateStartAddr,           x"00000000", x"00FFFFFF", x"00FFFFFF", 8),
                                (cGateStopAddr,            x"00000000", x"00FFFFFF", x"00FFFFFF", 8),
                                (cGateAttributesAddr,      x"00000000", x"FFFFFFFF", x"FFFFFFFF", 8),
                                (cGateTrailFlankHOAddr,    x"00000000", x"000000FF", x"000000FF", 1),
                                (cCheckRegAddr,            x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cADCSerialCtrlAddr,       x"00000000", x"03FFFFFF", x"80FFFFFF", 1),
                                (cRawADCDataAddr,          x"00000000", x"00000000", x"00000FFF", 1),
                                (cDDSCtrlAddr,             x"00000000", x"400FFFFF", x"800EFFFF", 1),
                                (cHVDACDataAddr,           x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cHVDACCtrlAddr,           x"00000000", x"00000001", x"80000000", 1),
                                (cHVCtrlAddr,              x"00000000", x"00000003", x"80000003", 1),
                                (cRAMBankSizeAddr,         x"00000000", x"7FFFFFFF", x"7FFFFFFF", 1),
                                (cSeqRepRateAddr,          x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cSeqPerBankAddr,          x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cRAMControlAddr,          x"00000000", x"0000001F", x"0000001F", 1),
                                (cEncoderClickPerSeqAddr,  x"00000000", x"00FFFFFF", x"00FFFFFF", 1),
                                (cFractEncClickPerSeqAddr, x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cSeqTriggerEncSelAddr,    x"00000000", x"0000000F", x"0000000F", 1),
                                (cSeqTriggerModeAddr,      x"00000000", x"0000000F", x"0000000F", 1),
                                (cSeqTriggerForceAddr,     x"00000000", x"00000001", x"00000000", 1),
                                (cSeqInRamAddr,            x"00000000", x"0000FFFF", x"0000FFFF", 1),
                                (cSampleCtrlAddr,          x"00000002", x"80000007", x"80000007", 1),
                                (cCScanDataRamOffsetAddr,  x"00000000", x"7FFFFFFF", x"7FFFFFFF", 1),
                                (cDataSamplingStatusAddr,  x"00000000", x"00000003", x"0000003F", 1),
                                (cRAMPageOffsetAddr,       x"00000000", x"7FC00000", x"7FC00000", 1),
                                (cShaftEncoder0OpAddr,     x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cShaftEncoder1OpAddr,     x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cShaftEncoder2OpAddr,     x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cShaftEncoder3OpAddr,     x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cDualEncoderCounterAddr,  x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cDigIOPulseCounter0Addr,  x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cDigIOPulseCounter1Addr,  x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cDigIOPulseCounter2Addr,  x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cDigIOPulseCounter3Addr,  x"00000000", x"FFFFFFFF", x"FFFFFFFF", 1),
                                (cRelayCtrlAddr,           x"00000000", x"00000001", x"00000001", 1),
                                (cSeqCtrlAddr,             x"00000000", x"8000001F", x"8000001F", 1),
                                (cMultiBoardCtrlAddr,      x"00000000", x"00FFFFF0", x"00FFFFFF", 1),
                                (cDspFpgaVerAddr,          x"0000" & cFpgaVersion & cFpgaRevision,
                                                                        x"00000000", x"0000FFFF", 1));

  constant cLastGate : integer := 7;
  type tGateData14 is array (0 to cLastGate) of std_logic_vector(13 downto 0);
  type tGateData24 is array (0 to cLastGate) of std_logic_vector(23 downto 0);
  type tGateData32 is array (0 to cLastGate) of std_logic_vector(31 downto 0);


  function SizeToBits(constant Size: integer) return integer;
end package DspFpgaPkg;

package body DspFpgaPkg IS
  -- Return the number of bits required to represent Size values
  function SizeToBits(constant Size: integer) return integer is
    variable Bits: integer;
    begin
      for Bits in 1 to 31 loop
        if ((2**Bits) >= Size) then
          return Bits;
        end if;
      end loop;
      return Bits;
  end;

end package body DspFpgaPkg;
