---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: SimCtrl004.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Simulation Control file to test A-Scan capture
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


architecture Test of SimCtrl is

  -- DSP Sequence Table registers
  constant cInputSelReg           : integer := 16#00301000#;
  constant cFilterCtrlReg         : integer := 16#00301004#;
  constant cRectifierModeReg      : integer := 16#00301008#;
  constant cDropSamplesReg        : integer := 16#0030100C#;
  constant cAScanRepRateReg       : integer := 16#00301010#;
  constant cPulseWidthReg         : integer := 16#00301014#;
  constant cPulseTrainReg         : integer := 16#00301018#;
  constant cAScanRangeReg         : integer := 16#0030101C#;
  constant cTCGConfigureAddr      : integer := 16#00301020#;
  constant cTCGPointsAddr         : integer := 16#00301024#;
  constant cTCGNoOfSamplesAddr    : integer := 16#00301028#;
  constant cTriggerDelayReg       : integer := 16#0030102C#;
  constant cSeqStepCtrlReg        : integer := 16#00301030#;
  constant cGateStartAddr         : integer := 16#00301040#; -- 8 Registers
  constant cGateStopAddr          : integer := 16#00301060#; -- 8 Registers
  constant cGateAttributesAddr    : integer := 16#00301080#; -- 8 Registers
  -- Other DSP Registers
  constant cDSPCheckReg           : integer := 16#00305000#;
  constant cRAMBankSizeReg        : integer := 16#0030501C#;
  constant cSeqRepRateReg         : integer := 16#00305020#;
  constant cSeqPerBankReg         : integer := 16#00305024#;
  constant cRAMControlReg         : integer := 16#00305028#;
  constant cSeqTriggerModeReg     : integer := 16#00305038#;
  constant cSeqTriggerForceReg    : integer := 16#0030503C#;
  constant cSeqInRamReg           : integer := 16#00305040#;
  constant cCScanDataRamOffsetAddr: integer := 16#00305048#;
  constant cSampleCtrlReg         : integer := 16#00305044#;
  constant cDataSamplingStatusAddr: integer := 16#0030504C#;
  constant cRAMPageOffsetAddr     : integer := 16#00305050#;
  constant cRelayReg              : integer := 16#003050A0#;
  constant cSeqCtrlReg            : integer := 16#003050A4#;

  constant cRAMOffset             : integer := 16#00400000#;

begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin


    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15.152 ns, ToBusModel, FromBusModel);

    LBusWrite(cRectifierModeReg, 3, ToBusModel, FromBusModel);

    wait for 250 us; -- enough time for SDRAM to initialise

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing Processor RAM access"));
    writeline (OUTPUT, vLine);

    -- write some data
    LBusWrite(cRAMPageOffsetAddr, 0, ToBusModel, FromBusModel);

    for i in 0 to 256 loop
      LBusWrite(cRAMOffset+(i*4), i+1, ToBusModel, FromBusModel);
    end loop;

--    LBusWrite(cRAMPageOffsetAddr, 16#00400000#, ToBusModel, FromBusModel);
--
--    for i in 0 to 256 loop
--      LBusWrite(cRAMOffset+(i*4), i+3, ToBusModel, FromBusModel);
--    end loop;

    -- Read back the data
    LBusWrite(cRAMPageOffsetAddr, 0, ToBusModel, FromBusModel);

    for i in 0 to 256 loop
      LBusRead(cRAMOffset+(i*4), vRData, ToBusModel, FromBusModel);
      if vRData /= i+1 then
        write (vLine, string'("Testbench: Error - Processor RAM read error - Page 0"));
        writeline (OUTPUT, vLine);
        vTestFail := true;
      end if;
    end loop;

--    LBusWrite(cRAMPageOffsetAddr, 16#00400000#, ToBusModel, FromBusModel);
--
--    for i in 0 to 256 loop
--      LBusRead(cRAMOffset+(i*4), vRData, ToBusModel, FromBusModel);
--      if vRData /= i+3 then
--        write (vLine, string'("Testbench: Error - Processor RAM read error - Page 1"));
--        writeline (OUTPUT, vLine);
--        vTestFail := true;
--      end if;
--    end loop;

    write (vLine, string'("Testbench: Processor RAM access tests complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing A-Scan Capture"));
    writeline (OUTPUT, vLine);

    LBusWrite(cRAMBankSizeReg, 1024*1024*1024, ToBusModel, FromBusModel); -- 1GByte
    LBusWrite(cCScanDataRamOffsetAddr, 256*1024*1024, ToBusModel, FromBusModel); -- 256MByte

    LBusWrite(cDropSamplesReg, 1, ToBusModel, FromBusModel); -- 100MHz
    LBusWrite(cAScanRepRateReg, 30000, ToBusModel, FromBusModel); -- 0.3 ms
    LBusWrite(cAScanRangeReg, 5002, ToBusModel, FromBusModel);
    LBusWrite(cTriggerDelayReg, 0, ToBusModel, FromBusModel);

    LBusWrite(cPulseWidthReg, 10, ToBusModel, FromBusModel); -- 100 ns

    -- step 2
    LBusWrite(cDropSamplesReg + 16#200#, 1, ToBusModel, FromBusModel); -- 100MHz
    LBusWrite(cAScanRepRateReg + 16#200#, 10000, ToBusModel, FromBusModel); -- 0.1 ms
    LBusWrite(cAScanRangeReg + 16#200#, 2502, ToBusModel, FromBusModel);
    LBusWrite(cTriggerDelayReg + 16#200#, 0, ToBusModel, FromBusModel);

    LBusWrite(cPulseWidthReg + 16#200#, 20, ToBusModel, FromBusModel); -- 200 ns

    LBusWrite(cSeqRepRateReg, 80000, ToBusModel, FromBusModel); -- 0.8 ms
    LBusWrite(cSeqPerBankReg, 4, ToBusModel, FromBusModel);

    -- setup Gate 1
    LBusWrite(cGateStartAddr + 4, 10, ToBusModel, FromBusModel);
    LBusWrite(cGateStopAddr + 4, 200, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributesAddr + 4, 16#80F0FF#, ToBusModel, FromBusModel); -- enable - Absolute trig
    LBusWrite(cRAMControlReg, 16 + 2, ToBusModel, FromBusModel); -- multiple A & C Scans

    -- Enable TCG
--    LBusWrite(cTCGPointsAddr, 100, ToBusModel, FromBusModel);
--    LBusWrite(cTCGNoOfSamplesAddr, 2, ToBusModel, FromBusModel);
--    LBusWrite(cTCGConfigureAddr, 3, ToBusModel, FromBusModel);
--
--    LBusWrite(cTCGPointsAddr + 16#200#, 50, ToBusModel, FromBusModel);
--    LBusWrite(cTCGNoOfSamplesAddr + 16#200#, 4, ToBusModel, FromBusModel);
--    LBusWrite(cTCGConfigureAddr + 16#200#, 3, ToBusModel, FromBusModel);


--    LBusWrite(cSeqTriggerModeReg, 16#00000002#, ToBusModel, FromBusModel); -- free-running
    LBusWrite(cSeqCtrlReg, 16#80000001#, ToBusModel, FromBusModel); -- 2 step
 
    wait for 10 us;
    -- force sequence trigger
    LBusWrite(cSeqTriggerForceReg, 16#00000001#, ToBusModel, FromBusModel);

    wait for 100 us;

    -- Wait for some data ready
    LBusRead(cDataSamplingStatusAddr, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#00000002#) = 0 loop
      LBusRead(cDataSamplingStatusAddr, vRData, ToBusModel, FromBusModel);
    end loop;

    LBusWrite(cDataSamplingStatusAddr, 2, ToBusModel, FromBusModel); -- Request early data

    -- Wait for data available
    LBusRead(cDataSamplingStatusAddr, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#00000001#) = 0 loop
      LBusRead(cDataSamplingStatusAddr, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Read some data
    for i in 0 to 15 loop
      LBusRead(cRAMOffset+(i*4), vRData, ToBusModel, FromBusModel);
    end loop;

    -- Flag that bank read
    LBusWrite(cDataSamplingStatusAddr, 16#00000001#, ToBusModel, FromBusModel);

    wait for 10 us;

    -- force trigger
    LBusWrite(cSeqTriggerForceReg, 16#00000001#, ToBusModel, FromBusModel);

    write (vLine, string'("Testbench: A-Scan test complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation 004 completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation 004 completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;