---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: Ddr2FifoWrEn0.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Write enable signal to the fifos which are driven by negedge of data strobe
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.Vcomponents.all;

entity Ddr2FifoWrEn0 is
  port (Clk           : in  std_ulogic;
        Reset         : in  std_ulogic;
        DIn           : in  std_ulogic;
        nRstDqsDelay  : out std_ulogic;
        DOut          : out std_ulogic);
end Ddr2FifoWrEn0;

architecture Rtl of Ddr2FifoWrEn0 is

  signal DInDelay : std_ulogic;
  signal DOutNext : std_ulogic;
  
begin

  nRstDqsDelay <= not DInDelay;
  DOutNext     <= DIn or DInDelay;

  DelayFF : FDCE
    port map (Q   => DInDelay,
              C   => Clk,
              CE  => '1',
              CLR => Reset,
              D   => DIn);

  OpFF : FDCE
    port map (Q   => DOut,
              C   => Clk,
              CE  => '1',
              CLR => Reset,
              D   => DOutNext);

end Rtl;
