---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DPRAMMux.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- 32bit to 8 bit DPRAM data mux
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity DPRAMMux is
  port(
    pPAD     : in  std_logic_vector(7 downto 0);
	  pBE      : in  std_logic_vector(1 downto 0);
    pDataIn  : in  std_logic_vector(31 downto 0);
    pDataOut : out std_logic_vector(7 downto 0));
end DPRAMMux;

architecture RTL of DPRAMMux is

  constant cBE0 : std_logic_vector(7 downto 0) := x"38";

begin

  process (pPAD, pBE, pDataIn)
  begin
    if pPAD = cBE0 then
	  case pBE is
	    when "00"   => pDataOut <= pDataIn(7 downto 0);
	    when "01"   => pDataOut <= pDataIn(15 downto 8);
	    when "10"   => pDataOut <= pDataIn(23 downto 16);
	    when "11"   => pDataOut <= pDataIn(31 downto 24);
	    when others => pDataOut <= (others => '0');
	  end case;
	else
		pDataOut <= (others => '0');
	end if;
  end process;

end architecture RTL;

