---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: AD9742.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Hi-Speed DAC Model
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use std.textio.all;

entity AD9742 is
  port (Clk   : in std_ulogic;
        Sleep : in std_ulogic;
        DB    : in std_logic_vector(11 downto 0);
        OutA  : out std_logic_vector(11 downto 0);
        TestFail: out boolean := false);
end entity AD9742;


architecture beh of AD9742 is

  signal A: std_logic_vector(1 downto 0);
  signal D: std_logic_vector(11 downto 0);

  constant tS  : time := 2 ns;
  constant tH  : time := 1.5 ns;
  constant tLPW: time := 1.5 ns;
  constant tPD : time := 1 ns;
begin

  State : process
    variable vClkRise: time := 0 ns;
  begin
    wait on Clk, Sleep, DB;

    if rising_edge(Clk) then
      OutA <= DB after tPD;
      
      if not DB'stable(tS) then
        DBSetupErr: assert false report "Invalid DB setup time for AD9742" severity error;
        TestFail <= true;
      end if;

      vClkRise := now;
    end if;

    if falling_edge(Clk) then
      if (now - vClkRise) < tLPW then
        ClkPeriodErr: assert false report "Invalid Clk Latch pulse width for AD9742" severity error;
        TestFail <= true;
      end if;
    end if;

    if DB'event then
      if (now - vClkRise) < tH then
        DBHoldErr: assert false report "Invalid DB hold time for AD9742" severity error;
        TestFail <= true;
      end if;
    end if;

  end process State;    

end architecture beh;