---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: BlockRam.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card (Shared component)
--
-- Design Description:
-- Module to to infer Xilinx Block RAM
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity BlockRam is
  generic(gAddressWidth: integer range 1 to 32 := 6;
          gDataWidth:    integer range 1 to 32 := 32);
  port(pClk     : in  std_ulogic;
       pWriteEn : in  std_ulogic;
       pAddr    : in  std_logic_vector(gAddressWidth-1 downto 0);
       pDataIn  : in  std_logic_vector(gDataWidth-1 downto 0);
       pDataOut : out std_logic_vector(gDataWidth-1 downto 0));
end entity BlockRam;


architecture syn of BlockRam is

  type tRam is array((2**gAddressWidth)-1 downto 0) of std_logic_vector(gDataWidth-1 downto 0);
  signal Ram : tRam;
  signal readAddr : std_logic_vector(gAddressWidth-1 downto 0);

begin

  process(pClk)
  begin
    if rising_edge(pClk) then
      if pWriteEn = '1' then
        Ram(conv_integer(unsigned(pAddr))) <= pDataIn;
      end if;

      readAddr <= pAddr;
    end if;
  end process;

  pDataOut <= Ram(conv_integer(unsigned(readAddr)));

end syn;
