---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DeMux3_8.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card Control FPGA
--
-- Design Description:
-- 3 input, 8 output demux
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity DeMux3_8 is
  port(
    pDIn  : in  std_logic_vector(2 downto 0);
    pDOut : out std_logic_vector(7 downto 0));
end DeMux3_8;

architecture RTL of DeMux3_8 is
begin
  pDOut(0) <= '1' when (pDIn = "000") else '0';
  pDOut(1) <= '1' when (pDIn = "001") else '0';
  pDOut(2) <= '1' when (pDIn = "010") else '0';
  pDOut(3) <= '1' when (pDIn = "011") else '0';
  pDOut(4) <= '1' when (pDIn = "100") else '0';
  pDOut(5) <= '1' when (pDIn = "101") else '0';
  pDOut(6) <= '1' when (pDIn = "110") else '0';
  pDOut(7) <= '1' when (pDIn = "111") else '0';
  
end architecture RTL;  