Design Summary:
Number of errors:      0
Number of warnings:   47
Logic Utilization:
  Number of Slice Flip Flops:     1,002 out of  1,536   65%
  Number of 4 input LUTs:         1,181 out of  1,536   76%
  Number of Slice Flip Flops:     1,036 out of  1,536   67%
  Number of 4 input LUTs:         1,188 out of  1,536   77%
  Number of Slice Flip Flops:       966 out of  1,536   62%
  Number of 4 input LUTs:         1,156 out of  1,536   75%
Logic Distribution:
    Number of occupied Slices:                         766 out of    768   99%
    Number of Slices containing only related logic:    699 out of    766   91%
    Number of Slices containing unrelated logic:        67 out of    766    8%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,214 out of  1,536   79%
      Number used as logic:                     1,188
      Number used as a route-thru:                 26
   Number of bonded IOBs:           169 out of    176   96%
      IOB Flip Flops:                             121
   Number of Tbufs:                 528 out of    832   63%
   Number of Block RAMs:              1 out of      8   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
   
  Number of Slice Flip Flops:       972 out of  1,536   63%
  Number of 4 input LUTs:         1,161 out of  1,536   75%
  
  Number of Slice Flip Flops:       968 out of  1,536   63%
  Number of 4 input LUTs:         1,155 out of  1,536   75%
  
  Number of Slice Flip Flops:       969 out of  1,536   63%
  Number of 4 input LUTs:         1,149 out of  1,536   74%

  Number of Slice Flip Flops:       970 out of  1,536   63%
  Number of 4 input LUTs:         1,149 out of  1,536   74%

#
# 27-05-2004
# Trigger delay module included.
# High speed (200MHz) clock enable put onto low skew net.
# Multiple cycle paths defined in ucf file.
#
Design Summary:
Number of errors:      0
Number of warnings:   15
Logic Utilization:
  Number of Slice Flip Flops:       967 out of  1,536   62%
  Number of 4 input LUTs:         1,159 out of  1,536   75%
Logic Distribution:
    Number of occupied Slices:                         766 out of    768   99%
    Number of Slices containing only related logic:    745 out of    766   97%
    Number of Slices containing unrelated logic:        21 out of    766    2%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,185 out of  1,536   77%
      Number used as logic:                     1,159
      Number used as a route-thru:                 26
   Number of bonded IOBs:           108 out of    176   61%
      IOB Flip Flops:                              72
   Number of Tbufs:                 406 out of    832   48%
   Number of Block RAMs:              1 out of      8   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
#
All constraints were met.


#
# 25-05-2004
# Multiple trigger firing but no trigger delay
#
Design Summary:
Number of errors:      0
Number of warnings:   15
Logic Utilization:
  Number of Slice Flip Flops:       871 out of  1,536   56%
  Number of 4 input LUTs:           953 out of  1,536   62%
Logic Distribution:
    Number of occupied Slices:                         655 out of    768   85%
    Number of Slices containing only related logic:    655 out of    655  100%
    Number of Slices containing unrelated logic:         0 out of    655    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:          976 out of  1,536   63%
      Number used as logic:                       953
      Number used as a route-thru:                 23
   Number of bonded IOBs:           107 out of    176   60%
      IOB Flip Flops:                              79
   Number of Tbufs:                 421 out of    832   50%
   Number of Block RAMs:              1 out of      8   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%
#
# Trigger Delay added
#
Design Summary:
Number of errors:      0
Number of warnings:   15
Logic Utilization:
  Number of Slice Flip Flops:       967 out of  1,536   62%
  Number of 4 input LUTs:         1,091 out of  1,536   71%
Logic Distribution:
    Number of occupied Slices:                         738 out of    768   96%
    Number of Slices containing only related logic:    738 out of    738  100%
    Number of Slices containing unrelated logic:         0 out of    738    0%
        *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:        1,117 out of  1,536   72%
      Number used as logic:                     1,091
      Number used as a route-thru:                 26
   Number of bonded IOBs:           108 out of    176   61%
      IOB Flip Flops:                              72
   Number of Tbufs:                 406 out of    832   48%
   Number of Block RAMs:              1 out of      8   12%
   Number of GCLKs:                   2 out of      4   50%
   Number of GCLKIOBs:                2 out of      4   50%
   Number of DLLs:                    1 out of      4   25%

