# $Id: ControlFPGA.ucf 74 2005-03-21 09:29:53Z phil $
#
# UCF File for Pulser Receiver Control FPGA
# Xilinx XC2S200-FG456-5
#

# Clock Input
NET "pClock"		LOC = "Y11";

NET "pClock" PERIOD = 10 ns HIGH 50 %;

# Test Port
NET "pTestPort<0>"	LOC = "A8";
NET "pTestPort<1>"	LOC = "B7";
NET "pTestPort<2>"	LOC = "A7";
NET "pTestPort<3>"	LOC = "B6";
NET "pTestPort<4>"	LOC = "B5";
NET "pTestPort<5>"	LOC = "A5";
NET "pTestPort<6>"	LOC = "B4";
NET "pTestPort<7>"	LOC = "B3";

NET "pSap"    LOC = "F1" | SLEW = FAST | DRIVE = 24;
NET "pScreen0" LOC = "C1";
NET "pPRxChK" LOC = "E1";
NET "pScreen1" LOC = "E4";
NET "pTSynch" LOC = "B1" | SLEW = FAST | DRIVE = 24;
# times just to keep it tight
TIMESPEC TS_TSynchDel=FROM:PADS(pTriggerDel):TO:PADS(pTSynch):12;

# Gain Control Voltage Source
NET "pExternalGainEn"	LOC = "P19";
NET "pInternalGainEn"	LOC = "P18";

# Front End High Pass Filter
NET "pHighPass<0>"	LOC = "AA17";
NET "pHighPass<1>"	LOC = "AB17";
NET "pHighPass<2>"	LOC = "AA15";

# Front End Low Pass Filter
NET "pLowPass<0>"	LOC = "V17";
NET "pLowPass<1>"	LOC = "W17";
NET "pLowPass<2>"	LOC = "Y17";

# Back End High Pass Filter
NET "pBeHighPass<0>" LOC = "Y16";	
NET "pBeHighPass<1>" LOC = "V15";	
NET "pBeHighPass<2>" LOC = "Y15";	

# Back End Low Pass Filter
NET "pBeLowPass<0>"	LOC = "V16";
NET "pBeLowPass<1>"	LOC = "AB16";
NET "pBeLowPass<2>"	LOC = "W16";


# Front End Preamp / Attenuator control
NET "pFrontPlus20dB"	LOC = "AA18";
NET "pFrontMinus40dB"	LOC = "Y18"; 
NET "pFront0dB"		LOC = "AB18"; 
NET "pFrontMinus20dB"	LOC = "W18";

NET "pMpx20dB"		LOC = "AA14";
NET "pMpx0dB"		LOC = "V14";

# Receiver Input Impedance Selection
NET "pRin47"		LOC = "AA20";
NET "pRin100"		LOC = "AB20";
NET "pRin270"		LOC = "AA19";
NET "pRin470"		LOC = "AB19";

# Pulse/Echo Channel Selection
NET "pPEChSel<1>"	LOC = "T22";
NET "pPEChSel<2>"	LOC = "T21";
NET "pPEChSel<3>"	LOC = "T20";
NET "pPEChSel<4>"	LOC = "T19";
NET "pPEChSel<5>"	LOC = "T18";
NET "pPEChSel<6>"	LOC = "U22";
NET "pPEChSel<7>"	LOC = "U21";
NET "pPEChSel<8>"	LOC = "U20";

# Receive Channel Selection
NET "pRxChSel<1>"	LOC = "U19";
NET "pRxChSel<2>"	LOC = "V22";
NET "pRxChSel<3>"	LOC = "V21";
NET "pRxChSel<4>"	LOC = "V20";
NET "pRxChSel<5>"	LOC = "W22";
NET "pRxChSel<6>"	LOC = "W21";
NET "pRxChSel<7>"	LOC = "Y21";
NET "pRxChSel<8>"	LOC = "AA22";

# Pulse Outputs
NET "pPulse<1>"		LOC = "C22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<2>"		LOC = "D22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<3>"		LOC = "E22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<4>"		LOC = "F22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<5>"		LOC = "H22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<6>"		LOC = "J22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<7>"		LOC = "K22" | SLEW = FAST | DRIVE = 24;
NET "pPulse<8>"		LOC = "L22" | SLEW = FAST | DRIVE = 24;
# times just to keep it tight
TIMESPEC TS_PulseDel=FROM:PADS(pTriggerDel):TO:PADS(pPulse*):12;

# High Voltage Control
NET "pHighVoltageEn"	LOC = "M3";
NET "pHighVoltageOK"	LOC = "M1";

# Ultran specific pins
NET "pnPowerOn"         LOC = "P21";
NET "pnPowerOOT"        LOC = "R22";
NET "pHTVOOT"           LOC = "D21";
NET "pHTIOOT"           LOC = "E21";
NET "pHTIsEn"           LOC = "N19";
#end of Ultran specific pin

# External Fine Delay Chip
NET "pFineDelay<0>"	LOC = "AB3";
NET "pFineDelay<1>"	LOC = "AB4";
NET "pFineDelay<2>"	LOC = "AA4";
NET "pFineDelay<3>"	LOC = "AB5";
NET "pFineDelay<4>"	LOC = "AA5";
NET "pFineDelay<5>"	LOC = "AB6";
NET "pFineDelay<6>"	LOC = "AA6";
NET "pFineDelay<7>"	LOC = "AA7";

# Dual DAC for Fine Gain Control and High Voltage Magnitude Control
NET "pDAC_nCS"		LOC = "R21";
NET "pDAC_SDI"		LOC = "R18";
NET "pDAC_Clk"		LOC = "R19";

# Trigger I/O
NET "pTriggerDel"	LOC = "AB8" | IOBDELAY = NONE ;
NET "pTrigger"		LOC = "W1" | IOBDELAY = NONE ;
NET "pTriggerOut"	LOC = "Y1" | SLEW = FAST ;
# times just to keep it tight
TIMESPEC TS_TriggerOut=FROM:PADS(pTrigger):TO:PADS(pTriggerOut):7.5;

# Acknowledge Output
NET "pAck"			LOC = "V1" | SLEW = FAST ;
# times just to keep it tight
TIMESPEC TS_TriggerAck=FROM:PADS(pTrigger):TO:PADS(pAck):7.5;

# System FPGA Interface
NET "pnReset"       LOC = "B12";  # F1 on System FPGA
NET "pSTxD"		    LOC = "D11";  # F4 on System FPGA
NET "pSRxD"		    LOC = "C12";  # F5 on System FPGA
NET "pHVStatus"		LOC = "D12";  # G2 on System FPGA
#NET "pOvlStatus"    LOC = "B12";  # G4 on System FPGA

# External Serial Port
#NET "pTxD"		LOC = "A4";
#NET "pRxD"		LOC = "A3";

#
# Multi-cycle paths
#
INST "Pulse_1_CWCount*"      TNM = "ClkEn_Paths";
INST "Pulse_1_PulseCount*"  TNM = "ClkEn_Paths";
INST "Pulse_1_LoadCount"  TNM = "ClkEn_Paths";
INST "Pulse_1_TriggerInt0"  TNM = "ClkEn_Paths";
INST "Pulse_1_PWCount*"     TNM = "ClkEn_Paths";
INST "Pulse_1_TriggerInt2"  TNM = "ClkEn_Paths";
TIMESPEC TS_MultiPath1=FROM:ClkEn_Paths:TO:ClkEn_Paths:10;

INST "SeqTab_1_pSeqTable7*" TNM = "No_Hurry_Start1";
INST "Pulse_1_RepCount_*" TNM = "No_Hurry_Dest1";
TIMESPEC TS_MultiPath2=FROM:No_Hurry_Start1:TO:No_Hurry_Dest1:20;

INST "SeqTab_1_pSeqTable5*"  TNM = "No_Hurry_Start2";
TIMESPEC TS_MultiPath3=FROM:No_Hurry_Start2:TO:ClkEn_Paths:20;

INST "CLKDLL0" LOC=DLL0;
INST "CLKDLL1" LOC=DLL2;
INST "BUFG0" LOC=GCLKBUF0;
INST "BUFG1" LOC=GCLKBUF1;
INST "BUFG2" LOC=GCLKBUF2;
INST "BUFG3" LOC=GCLKBUF3;

#
# $Log$
