JDF G
// Created by Project Navigator ver 1.0
PROJECT PRx System FPGA
DESIGN systemfpga
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s50
DEVICETIME 0
DEVPKG fg256
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 1097488722
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 1097489392
SOURCE ../source/SystemFpga_pkg.vhd
SOURCE ../source/PLXInterface.vhd
SOURCE ../source/SystemFpgaTop.vhd
SOURCE ../source/AddressDecoder.vhd
SOURCE ../../common/source/kcuart_rx.vhd
SOURCE ../../common/source/bbfifo_16x8.vhd
SOURCE ../../common/source/uart_rx.vhd
SOURCE ../source/BitIO.vhd
SOURCE ../../common/source/kcuart_tx.vhd
SOURCE ../../common/source/uart_tx.vhd
SOURCE ../../common/source/kcpsm.vhd
SOURCE ../source/BusArbiter.vhd
SOURCE ../source/EEPROM.vhd
SOURCE ../source/EepromCtrl.vhd
SOURCE ../source/DataMux.vhd
SOURCE ../source/ControlROM/PROG_ROM.VHD
SOURCE ../../common/source/UAR.vhd
SOURCE ../../common/source/UAT.vhd
SOURCE ..\source\DPRAMMux.vhd
SOURCE ..\source\SysControl.vhd
SOURCE ..\source\SysKCPSM.vhd
SOURCE ..\source\ClockReset.vhd
SOURCE ..\source\SysSequenceTable.vhd
SOURCE ..\..\common\source\OutPort32.vhd
SOURCE ..\..\common\source\AddressCounter.vhd
SOURCE ..\source\CheckReg.vhd
SOURCE ..\..\common\source\DPBRAM32x256.vhd
SOURCE ..\source\SysIo.vhd
SOURCE ..\..\common\source\InPort32.vhd
DEPASSOC systemfpgatop ../constraints/SystemFpga.ucf
[Normal]
mpprExtraEffortLevel=xstvhd, spartan2, Implementation.t_mppr, 1070036937, Continue on Impossible
mpprPlacerEffortLevel=xstvhd, spartan2, Implementation.t_mppr, 1070036937, High
mpprRouterEffortLevel=xstvhd, spartan2, Implementation.t_mppr, 1070036937, High
p_xstGenerateRTLNetlist=xstvhd, spartan2, Schematic.t_synthesize, 1070036679, No
p_xstOptimizeInsPrimtives=xstvhd, spartan2, Schematic.t_synthesize, 1073920644, True
p_xstUseSynthConstFile=xstvhd, spartan2, Schematic.t_synthesize, 1073920644, False
p_xstVerilog2001=xstvhd, spartan2, Schematic.t_synthesize, 1073920644, False
xilxBitgCfg_Clk=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_Done=xstvhd, spartan2, Implementation.t_bitFile, 1109091130, Float
xilxBitgCfg_GenOpt_BinaryFile=xstvhd, spartan2, Implementation.t_bitFile, 1079609558, True
xilxBitgCfg_GenOpt_LogicAllocFile=xstvhd, spartan2, Implementation.t_bitFile, 1109070494, False
xilxBitgCfg_GenOpt_MaskFile=xstvhd, spartan2, Implementation.t_bitFile, 1109070436, True
xilxBitgCfg_GenOpt_ReadBack=xstvhd, spartan2, Implementation.t_bitFile, 1109073748, False
xilxBitgCfg_M0=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_M1=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_M2=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_Pgm=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_TCK=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_TDI=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_TDO=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_TMS=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgCfg_Unused=xstvhd, spartan2, Implementation.t_bitFile, 1109071382, Float
xilxBitgReadBk_GenBitStr=xstvhd, spartan2, Implementation.t_bitFile, 1109070756, False
xilxBitgReadBk_Sec=xstvhd, spartan2, Implementation.t_bitFile, 1109073748, Disable Readback
xilxBitgStart_Clk=xstvhd, spartan2, Implementation.t_bitFile, 1109073624, CCLK
xilxBitgStart_Clk_Done=xstvhd, spartan2, Implementation.t_bitFile, 1109073748, Default (4)
xilxBitgStart_Clk_DriveDone=xstvhd, spartan2, Implementation.t_bitFile, 1109070571, True
xilxBitgStart_IntDone=xstvhd, spartan2, Implementation.t_bitFile, 1109071165, False
xilxMapAllowLogicOpt=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1070026823, True
xilxNgdbld_AUL=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1109168246, False
xilxPAReffortLevel=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1110886717, Standard
xilxPARextraEffortLevel=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1110809722, Normal
xilxPARstrat=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1073920366, Normal Place and Route
xilxPostTrceRptLimit=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1079631445, 10
xilxPostTrceRptTiming=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1079631445, 10
xilxPreTrceRptLimit=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1079631455, 10
xilxPreTrceRptTiming=xstvhd, spartan2, Implementation.t_placeAndRouteDes, 1079631455, 10
xilxSynthKeepHierarchy=xstvhd, spartan2, Schematic.t_synthesize, 1110888032, Yes
xilxSynthRegBalancing=xstvhd, spartan2, Schematic.t_synthesize, 1074172032, No
_SynthCaseImplStyle=xstvhd, spartan2, Schematic.t_synthesize, 1073920644, Full
_SynthOptEffort=xstvhd, spartan2, Schematic.t_synthesize, 1071234939, High
[STRATEGY-LIST]
Normal=True
