---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: BeaSwitch.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Module to switch when Bea Gate triggers
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

entity BeaSwitch is
  port(nReset         : in  std_ulogic;
       Clk            : in  std_ulogic;
       TriggersIn     : in  std_logic_vector(7 downto 0);
       TriggerNum     : in  std_logic_vector(2 downto 0);
       BeaEnable      : in  std_ulogic;
       BeaSwitch      : out std_ulogic);
end entity BeaSwitch;


architecture Rtl of BeaSwitch is
begin

  GenSwitch: process(nReset, Clk)
  begin
    if nReset = '0' then
      BeaSwitch <= '0';
    elsif Clk'event and Clk = '1' then
      if BeaEnable = '1' and TriggersIn(conv_integer(unsigned(TriggerNum))) = '1' then
        BeaSwitch <= '1';
      else
        BeaSwitch <= '0';
      end if;
    end if;
  end process GenSwitch;

end architecture Rtl;