---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: AdcTest.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Test data Generator for ADC model
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity AdcTest is
  port (Clk   : in    std_ulogic;
        nReset: in    std_ulogic;
        --
        Vp    : out   integer; -- analog output
        Vn    : out   integer);
end entity AdcTest;


architecture Beh of AdcTest is
  
begin

  process
    variable V : integer;
    variable Rise : boolean;
  begin
    wait on nReset, Clk;
      
    if nReset = '0' then
      V := 0;
      Rise := true;
      Vp <= 0;
      Vn <= 0;
    end if;
    if rising_edge(Clk) then
      if Rise then
        if V = 2047 then
          V := 2046;
          Rise := false;
        else
          V := V + 1;
        end if;
      else
        if V = -2048 then
          V := -2047;
          Rise := True;
        else
          V := V - 1;
        end if;
      end if;
      Vp <= V / 2;
      Vn <= (-V) + (V / 2);
    end if;
  end process;    

end architecture Beh;
