---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DAC7612Model.vhd
-- Language: VHDL '93
-- Project:  PRx Card Control FPGA
--
-- Design Description:
-- DAC Model
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

entity DAC7612Model is
  port(pDacClk     : in std_ulogic;
       pDacnCs     : in std_ulogic;
       pDacnLoad   : in std_ulogic;
       pDacSdi     : in std_ulogic;
       pDacDataA   : out std_logic_vector(11 downto 0);
       pDacDataB   : out std_logic_vector(11 downto 0));
end entity DAC7612Model;



architecture beh of DAC7612Model is

  signal A: std_logic_vector(1 downto 0);
  signal D: std_logic_vector(11 downto 0);

begin

  State : process
  begin
    wait on pDacClk, pDacnLoad;

    if rising_edge(pDacClk) then
      if (pDacnCs = '0') then
        D <= D(10 downto 0) & pDacSdi;
        A <= A(0) & D(11);
      end if;
    end if;

    if falling_edge(pDacnLoad) then
      if (A(1) = '0' or A(0) = '0') then
        pDacDataA <= D;
      end if;
      if (A(1) = '0' or A(0) = '1') then
        pDacDataB <= D;
      end if;
    end if;

  end process State;    

end architecture beh;