---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: ADC128C022.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 System FPGA
--
-- Design Description:
-- 8 channel ADC model for system monitor
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity ADC128C022 is
  port(SClk : in  std_ulogic;
       nCs  : in  std_ulogic;
       DIn  : in  std_ulogic;
       DOut : out std_logic := 'Z';
       -- Testbench interface signals
       In0  : in  integer range 0 to 4095;
       In1  : in  integer range 0 to 4095;
       In2  : in  integer range 0 to 4095;
       In3  : in  integer range 0 to 4095;
       In4  : in  integer range 0 to 4095;
       In5  : in  integer range 0 to 4095;
       In6  : in  integer range 0 to 4095;
       In7  : in  integer range 0 to 4095);
end entity ADC128C022;


architecture Beh of ADC128C022 is
  signal Add: std_logic_vector(2 downto 0) := "000";
  signal IpSel: integer range 0 to 7 := 0;
  signal AdcSample : unsigned(11 downto 0);
  signal Count: integer;
begin

  State : process
  begin
    wait until falling_edge(nCs);
    DOut <= '0' after 30 ns;
    Count <= 1;

    loop
      wait on nCs, SClk;

      if rising_edge(nCs) then
        exit;
      end if;

      if falling_edge(SClk) then

        if Count = 2 then
          IpSel <= conv_integer(unsigned(Add));
          DOut <= '0' after 30 ns;
        end if;

        if Count = 4 then
          case IpSel is
            when 0 =>
              AdcSample <= conv_unsigned(In0, 12);
            when 1 =>
              AdcSample <= conv_unsigned(In1, 12);
            when 2 =>
              AdcSample <= conv_unsigned(In2, 12);
            when 3 =>
              AdcSample <= conv_unsigned(In3, 12);
            when 4 =>
              AdcSample <= conv_unsigned(In4, 12);
            when 5 =>
              AdcSample <= conv_unsigned(In5, 12);
            when 6 =>
              AdcSample <= conv_unsigned(In6, 12);
            when 7 =>
              AdcSample <= conv_unsigned(In7, 12);
            when others =>
          end case;
        end if;

        if Count >= 5 and Count <= 16 then
          Dout <= AdcSample(16 - Count) after 27 ns;
        end if;

      end if;

      if rising_edge(SClk) then
        if Count = 16 then
          Count <= 1;
        else
          Count <= Count + 1;
        end if;

        if Count >= 3 and Count <= 5 then
          Add(5-Count) <= Din;
        end if;
      end if;

    end loop;

    DOut <= 'Z' after 20 ns;

  end process State;    

end architecture Beh;
