---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: UAT.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card
--
-- Design Description:
-- Universal Asynchronous Transmitter - Wrapper around KCPSM companion uart_tx
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity UAT is
  port(
    pClock   : in  std_logic;
    pnReset  : in  std_logic;
    pWE      : in  std_logic;
    pPAD     : in  std_logic_vector(7 downto 0);
    pDataIn  : in  std_logic_vector(7 downto 0);
    pTxD     : out std_logic;
    pDataOut : out std_logic_vector(7 downto 0));
end UAT;

architecture RTL of UAT is

  constant cLoadData       : std_logic_vector(7 downto 0) := x"40";
  constant cBufferFull     : std_logic_vector(7 downto 0) := x"41";
  constant cBufferHalfFull : std_logic_vector(7 downto 0) := x"42";

  signal Reset          : std_logic;
  signal WE             : std_logic;
  signal BufferFull     : std_logic;
  signal BufferHalfFull : std_logic;

  component uart_tx
    port (
      data_in          : in  std_logic_vector(7 downto 0);
      write_buffer     : in  std_logic;
      reset_buffer     : in  std_logic;
      en_16_x_baud     : in  std_logic;
      serial_out       : out std_logic;
      buffer_full      : out std_logic;
      buffer_half_full : out std_logic;
      clk              : in  std_logic);
  end component;

begin

  Reset <= not pnReset;
  WE    <= pWE when pPAD = cLoadData else '0';

  process (pnReset, pWE, pPAD, pDataIn, BufferFull, BufferHalfFull)
  begin
    if pnReset = '0' then
      pDataOut <= (others => '0');
    end if;
    case pPAD is
      when cBufferFull     => pDataOut <= "0000000" & BufferFull;
      when cBufferHalfFull => pDataOut <= "0000000" & BufferHalfFull;
      when others          => pDataOut <= (others => '0');
    end case;
  end process;

  uart_tx_1 : uart_tx
    port map (
      data_in          => pDataIn,
      write_buffer     => WE,
      reset_buffer     => Reset,
      en_16_x_baud     => '1',
      serial_out       => pTxD,
      buffer_full      => BufferFull,
      buffer_half_full => BufferHalfFull,
      clk              => pClock);

end architecture RTL;

