---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SystemFpgaTop.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Local Bus Interface for Pulser Receiver Card (PRx) System FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity PLXInterface is
  port(
    pnReset     : in  std_ulogic;
    pClock      : in  std_ulogic;  -- same Local Bus Clock as sent to PLX chip
    pHOLDA      : in  std_ulogic;
    pPLX_LWR    : in  std_ulogic;        -- PLX Local Bus write NOT read
    pPLX_nADS   : in  std_ulogic;        -- Address Strobe
    pPLX_nBLAST : in  std_ulogic;        -- Burst Last
    pPLX_nREADY : out std_ulogic;        -- Ready
    pPLX_BREQI  : out std_ulogic);
end PLXInterface;

architecture RTL of PLXInterface is

  type   tControlState is (sIdle, sBegin, sBurst);
  signal CState : tControlState;
  signal nREADY : std_ulogic;

begin

  pPLX_nREADY <= nREADY;
  pPLX_BREQI  <= '0';

  ControlFSM : process(pnReset, pClock)
  begin
    if pnReset = '0' then
      CState <= sIdle;
      nREADY <= '1';
    elsif rising_edge(pClock) then
      case CState is

        when sIdle =>
          nREADY <= '1';
          if pPLX_nADS = '0' then       -- Begin cycle 
            CState <= sBegin;
          else
            CState <= sIdle;
          end if;

        when sBegin =>
          nREADY <= '0';
          if pPLX_nBLAST = '0' then     -- just a single access
            CState <= sIdle;
          else                          -- burst access
            CState <= sBurst;
          end if;

        when sBurst =>
          nREADY <= '0';
          if pPLX_nBLAST = '0' then     -- End of burst
            nREADY <= '1';
            CState <= sIdle;
          else
            CState <= sBurst;           -- Continue burst
          end if;
          
        when others =>
          CState <= sIdle;

      end case;
    end if;
  end process ControlFSM;

end architecture RTL;

