---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: AD7314.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 System FPGA
--
-- Design Description:
-- Temperature sensor model for system monitor
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity AD7314 is
  port(SClk : in  std_ulogic;
       Ce   : in  std_ulogic;
       Sdi  : in  std_ulogic;
       Sdo  : out std_ulogic := 'Z';
       -- Testbench interface signals
       Temp : in  integer range -35 to +85); -- temperature in deg C
end entity AD7314;


architecture Beh of AD7314 is
  signal Shutdown: std_ulogic;
  signal TempSample : signed(9 downto 0);
begin

  Sample : process
  begin
      wait for 25 us;
      TempSample <= conv_signed(Temp*4, 10);
      wait for 375 us;
  end process Sample;  

  OpState : process
    variable ShiftReg: std_logic_vector(10 downto 0);
    variable  Count: integer := 0;
  begin
    wait until rising_edge(Ce);
    ShiftReg := '0' & std_logic_vector(TempSample);
    Count := 0;

    loop
      if falling_edge(Ce) then
        Sdo <= 'Z' after 40 ns;
        exit;
      end if;

      if rising_edge(SClk) then
        Count := Count + 1;
        if Count = 15 then
          Shutdown <= Sdi;
          exit;
        else
          Sdo <= ShiftReg(10) after 35 ns;
          ShiftReg := ShiftReg(9 downto 0) & ShiftReg(0);
        end if;
      end if;

      wait on Ce, SClk;
    end loop;

    if Ce = '1' then
      wait until falling_edge(Ce);
      Sdo <= 'Z' after 40 ns;
    end if;

  end process OpState;    

end architecture Beh;
