---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: AddressCounter.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- 32bit Address buffer / counter
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity AddressCounter is
  port(
    pClock      : in  std_logic;
    pnReset     : in  std_logic;
    pWE         : in  std_logic;
    pDataIn     : in  std_logic_vector(7 downto 0);
    pPAD        : in  std_logic_vector(7 downto 0);
    pAddressOut : out std_logic_vector(31 downto 0));
end AddressCounter;

architecture RTL of AddressCounter is

  constant cINC : std_logic_vector(7 downto 0) := x"34";
  constant cBE0 : std_logic_vector(7 downto 0) := x"30";
  constant cBE1 : std_logic_vector(7 downto 0) := x"31";
  constant cBE2 : std_logic_vector(7 downto 0) := x"32";
  constant cBE3 : std_logic_vector(7 downto 0) := x"33";

  signal AddressBuffer : unsigned(31 downto 0);

begin

  pAddressOut <= std_logic_vector(AddressBuffer);

  process (pClock, pnReset, pWE, pPAD, pDataIn)
  begin
    if pnReset = '0' then
      AddressBuffer <= (others => '0');
    elsif rising_edge(pClock) then
      if pWE = '1' then
        case pPAD is
          when cBE0   => AddressBuffer(7 downto 0)   <= unsigned(pDataIn);
          when cBE1   => AddressBuffer(15 downto 8)  <= unsigned(pDataIn);
          when cBE2   => AddressBuffer(23 downto 16) <= unsigned(pDataIn);
          when cBE3   => AddressBuffer(31 downto 24) <= unsigned(pDataIn);
          when cINC   => AddressBuffer               <= AddressBuffer + 1;
          when others => AddressBuffer               <= AddressBuffer;
        end case;
      end if;
    end if;
  end process;

end architecture RTL;

