System FPGA memory map and stuff


Suggest local bus address map something like...

0x00000000 to 0x00400000	:- sample ram image
0x00400000 to 0x00440000	:- system ram
0x00440000 to 0x00440100	:- system registers
0x00440100 to 0x00440200	:- sample system registers



just to make things easier - Some rules...

i)	Sample ram(s) are mapped into allocated slot one at a time.
	Required sample ram is selected by a flag in a register.
	This may help on the PCI setup - dosn't much matter
	with a single AtoD system - can dick with memory 
	map at a later date.

ii)	Fpga cores loaded in system ram in byte format - 
	i.e. just use the bottom 8 bits. Saves jiggling 
	the data about.
	Thats 166980 + 69900 = 236880 bytes. Both fpga's
	will fit into ram at once.
	For bigger fpga cores - do whatever - 1Meg bytes available.

iii)	EEPROM loaded via image at bottom of system ram in 
	one lump of 512 bytes.
	i.e. eeprom addr 0x00 = system ram 0x00400000 etc.

iv)	EEPROM read by dumping its entire contents into 
	bottom of system ram. This will take some time.

v)	Implement a check register in system logic - just 
	to prove its alive ( boots from eeprom ). This simply 
	returns an inverted version of whatever you write to it.


SYSTEM REGISTERS - 32  bit 

0x00440000 - 	r/w - check register - inverts written data

0x00440004 - 	r/w - digital I/O - set / read IO bits 0 to 31

0x00440008 - 	r/w - digital I/O - set / read IO bits 32 to 54
		bits 55 to 63 are not present.
		LED D10 is on IO54.

0x0044000c - 	w - command register

		bit	Function

		0	enable sampling
		1	program fpga's 
				Select required fpga using the CS flags below.
				System ram must be loaded with core images.
				Assumes no change to fpga types - so byte counts
				known

		2	CS0	Chip selects... 
		3	CS1		pick out a sampling system to play with
		4	CS2		or...
		5	CS3		fpga to program

		6	write eeprom - copies bottom 512 bytes of system ram
				into eeprom. Takes ?? ms.	
				Flag set in status register on completion.
	
		7	read eeprom - copies all 512 bytes of eeprom into bottom
				512 bytes of system ram. Takes ?? ms.
				Flag set in status register on completion.

		All other bits spare at the moment

0x0044000c - 	r - status register

		bit	Function

		0 	fpga program flag - set on completion of fpga program cycle.
			Cleared for duration of cycle.
		1	eeprom flag - set on completion of either a read or a
			write cycle. Cleared for duration of cycle.
		2	IRQ0	Flags from sampling systems
		3	IRQ1	set when sample data ready 
		4	IRQ2
		5	IRQ3

		All other bits spare at the moment - ho humm...	
		

SAMPLE SYSTEM REGISTERS - select using CS'n'
0x00440100 -	w - Analogue stuff

		bit	function	

		0	ac/dc 	- input coupling
		1	1M/50R 	- input imedance
		2	ain0	- analogue input selection
		3	ain1	-	"
		4	ain2	-	"
		5	ain3	-	"
		6	gain0	- analogue gain	- also selects calibrator range 
		7	gain1	-	"
		8	gain2 	-	"
		9	gain3	-	"
		10	gain4	-	"
		11	gain5	-	"
		12	port_format - AtoD output port format - might preset this one
		13	data_format - AtoD output data format - ditto
		14	range	- selects AtoD input range
		15	sense	- selects AtoD V ref input characteristics
		16	LED D6	- twinklies
		17	LED D7	-	"
		18	LED D8	-	"
		19	LED D9	-	"

0x00440100 - 	r - hardware status
		
		bits 0 to 11 	- AtoD output at half sample clock rate
		bit 12	- AtoD out of range flag
		bit 13	offset flag. Set on completion of data transfer to offset DtoA
			cleared when write to offset DtoA initiated
		bit 14	gain flag. Set on completion of data transfer to gain DtoA. Cleared
			when write to gain DtoA initiated
 	 

0x00440104 - 	w - 	calibrator
		bits 0 to 11 - dc offset adj
		bits 16 to 28 - gain adj
		all other bits unused.


0x00440108 - 	w - 	DDS control
		This sucker has a whole bunch of its own registers. This system register 
		is used to waggle the dds address/data lines directly. Refer to AD9852 data 
		sheet for information. Two flags are tied directly to dds input pins also 
		presented in this register - thereby transfering 100% of the dds 
		functionality over the PCI bus.
		
		bits 0 to 7 	- dds parallel address bus
		bits 8 to 15 	- dds register
		bit 16	FSK	- dds fsk input flag
		bit 17	KEY	- dds key input	flag
		all other bit unused

0x0044010c - 	w - DAC load.
		Single 32 bit register. Write a formatted **16 bit** data stream to bit 0 to 15.
		First two bytes are the stream length - rest are the two 8 bit data streams.

	
There are assorted LED's and stuff
		