---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: CtrlKCPSM.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card Control FPGA
--
-- Design Description:
-- This file instantiates the KCPSM processor macro and connects the program ROM.
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
--
---------------------------------------------------------------------------
--
--
entity CtrlKCPSM is
    port ( port_id      : out std_logic_vector(7 downto 0);
           write_strobe : out std_ulogic;
           read_strobe  : out std_ulogic;
           out_port     : out std_logic_vector(7 downto 0);
           in_port      : in std_logic_vector(7 downto 0);
           interrupt    : in std_ulogic;
           reset        : in std_ulogic;
           clk          : in std_ulogic);
end CtrlKCPSM;
--
---------------------------------------------------------------------------
--
-- Start of test achitecture
--
architecture Str of CtrlKCPSM is
--
---------------------------------------------------------------------------
--
-- declaration of KCPSM
--
  component kcpsm
    port ( address      : out std_logic_vector(7 downto 0);
           instruction  : in std_logic_vector(15 downto 0);
           port_id      : out std_logic_vector(7 downto 0);
           write_strobe : out std_ulogic;
           out_port     : out std_logic_vector(7 downto 0);
           read_strobe  : out std_ulogic;
           in_port      : in std_logic_vector(7 downto 0);
           interrupt    : in std_ulogic;
           reset        : in std_ulogic;
           clk          : in std_ulogic);
    end component;
--
-- declaration of program ROM
--
  component ctrl_rom 
    port ( address     : in std_logic_vector(7 downto 0);
           instruction : out std_logic_vector(15 downto 0);
           clk         : in std_ulogic);
    end component;
--
---------------------------------------------------------------------------
--
-- Signals used to connect KCPSM to program ROM
--
signal address     : std_logic_vector(7 downto 0);
signal instruction : std_logic_vector(15 downto 0);
--
---------------------------------------------------------------------------
--
-- Start of test circuit description
--
begin

  processor: kcpsm
    port map( address      => address,
              instruction  => instruction,
              port_id      => port_id,
              write_strobe => write_strobe,
              out_port     => out_port,
              read_strobe  => read_strobe,
              in_port      => in_port,
              interrupt    => interrupt,
              reset        => reset,
              clk          => clk);

  program: ctrl_rom
    port map( address     => address,
              instruction => instruction,
              clk         => clk);

end Str;

