---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: delay_value_ram.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card Peripheral FPGA
--
-- Design Description:
-- Simulation model for CoreGen module delay_value_ram.
--
-- This module is for simulation purposes only and should not be
-- synthesised.
---------------------------------------------------------------------------


library IEEE;
Use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


entity delay_value_ram is
  port (addra : in  std_logic_vector(10 downto 0);
        addrb : in  std_logic_vector(8 downto 0);
        clka  : in  std_logic;
        clkb  : in  std_logic;
        dinb  : in  std_logic_vector(31 downto 0);
        douta : out std_logic_vector(7 downto 0);
        web   : in  std_logic);
end entity delay_value_ram;


architecture simulation of delay_value_ram is

  type tRam is array((2**11)-1 downto 0) of std_logic_vector(7 downto 0);
  signal Ram : tRam;
  signal ReadAddr: std_logic_vector(10 downto 0);


begin

  -- Proces to write data from 32-bit bus to memory
  process(clkb)
  begin
    if rising_edge(clkb) then
      if web = '1' then
        Ram(conv_integer(unsigned(addrb))*4 + 0) <= dinb(7 downto 0);
        Ram(conv_integer(unsigned(addrb))*4 + 1) <= dinb(15 downto 8);
        Ram(conv_integer(unsigned(addrb))*4 + 2) <= dinb(23 downto 16);
        Ram(conv_integer(unsigned(addrb))*4 + 3) <= dinb(31 downto 24);
      end if;
    end if;
  end process;


  -- Process to read data from 8-bit bus
  process(clka)
  begin
    if rising_edge(clka) then
      ReadAddr <= addra;
    end if;
  end process;
  douta <= Ram(conv_integer(unsigned(ReadAddr)));


end architecture simulation;