/****************************************************************************************
*
*    File Name:  ddr2_sodimm.v
*
*  Description:  Micron SDRAM DDR2 (Double Data Rate 2) 200 pin small outline dual in-line memory module (SODIMM)
*                - 1GByte or 2 GByte supported
*
*   Limitation:  - SPD (Serial Presence-Detect) is not modeled
*
*   Disclaimer   This software code and all associated documentation, comments or other 
*  of Warranty:  information (collectively "Software") is provided "AS IS" without 
*                warranty of any kind. MICRON TECHNOLOGY, INC. ("MTI") EXPRESSLY 
*                DISCLAIMS ALL WARRANTIES EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED 
*                TO, NONINFRINGEMENT OF THIRD PARTY RIGHTS, AND ANY IMPLIED WARRANTIES 
*                OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. MTI DOES NOT 
*                WARRANT THAT THE SOFTWARE WILL MEET YOUR REQUIREMENTS, OR THAT THE 
*                OPERATION OF THE SOFTWARE WILL BE UNINTERRUPTED OR ERROR-FREE. 
*                FURTHERMORE, MTI DOES NOT MAKE ANY REPRESENTATIONS REGARDING THE USE OR 
*                THE RESULTS OF THE USE OF THE SOFTWARE IN TERMS OF ITS CORRECTNESS, 
*                ACCURACY, RELIABILITY, OR OTHERWISE. THE ENTIRE RISK ARISING OUT OF USE 
*                OR PERFORMANCE OF THE SOFTWARE REMAINS WITH YOU. IN NO EVENT SHALL MTI, 
*                ITS AFFILIATED COMPANIES OR THEIR SUPPLIERS BE LIABLE FOR ANY DIRECT, 
*                INDIRECT, CONSEQUENTIAL, INCIDENTAL, OR SPECIAL DAMAGES (INCLUDING, 
*                WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, 
*                OR LOSS OF INFORMATION) ARISING OUT OF YOUR USE OF OR INABILITY TO USE 
*                THE SOFTWARE, EVEN IF MTI HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH 
*                DAMAGES. Because some jurisdictions prohibit the exclusion or 
*                limitation of liability for consequential or incidental damages, the 
*                above limitation may not apply to you.
*
*                Copyright 2003 Micron Technology, Inc. All rights reserved.
*
****************************************************************************************/
 `timescale 1ps / 1ps

module ddr2_sodimm (
    reset_n,
    ck     ,
    ck_n   ,
    cke    ,
    s_n    , 
    ras_n  ,
    cas_n  ,
    we_n   ,
    ba     ,
    addr   ,
    odt    ,
    dm     ,
    dqs    ,
    dqs_n  ,
    dq     ,
    scl    ,
    sa     ,
    sda
);

`define x8
`include "ddr2_parameters.vh"

    input                  reset_n;
    input            [1:0] ck     ;
    input            [1:0] ck_n   ;
    input            [1:0] cke    ;
    input            [1:0] s_n    ;
    input                  ras_n  ;
    input                  cas_n  ;
    input                  we_n   ;
    input            [2:0] ba     ;
    input           [13:0] addr   ;
    input            [1:0] odt    ;
    input            [7:0] dm     ;
    inout            [7:0] dqs    ;
    inout            [7:0] dqs_n  ;
    inout           [63:0] dq     ;
    input                  scl    ; // no connect
    input            [2:0] sa     ; // no connect
    inout                  sda    ; // no connect

    initial if (DEBUG) $display("%m: Unbuffered SODIMM");
    wire     [BA_BITS-1:0] rba    = ba[BA_BITS-1:0];

  //ddr2      (ck   , ck_n   , cke   , cs_n  , ras_n, cas_n, we_n, dm_dqs , ba , addr               , dq       , dqs   , dqs_n   , rdqs_n   , odt   );
    initial if (DEBUG) $display("%m: Component Width = x8");
    ddr2 U2   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[0], rba, addr[ADDR_BITS-1:0], dq[ 7: 0], dqs[0], dqs_n[0], , odt[0]);
    ddr2 U6   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[1], rba, addr[ADDR_BITS-1:0], dq[15: 8], dqs[1], dqs_n[1], , odt[0]);
    ddr2 U3   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[2], rba, addr[ADDR_BITS-1:0], dq[23:16], dqs[2], dqs_n[2], , odt[0]);
    ddr2 U7   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[3], rba, addr[ADDR_BITS-1:0], dq[31:24], dqs[3], dqs_n[3], , odt[0]);
    ddr2 U4   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[4], rba, addr[ADDR_BITS-1:0], dq[39:32], dqs[4], dqs_n[4], , odt[0]);  
    ddr2 U8   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[5], rba, addr[ADDR_BITS-1:0], dq[47:40], dqs[5], dqs_n[5], , odt[0]);  
    ddr2 U5   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[6], rba, addr[ADDR_BITS-1:0], dq[55:48], dqs[6], dqs_n[6], , odt[0]);  
    ddr2 U9   (ck[0], ck_n[0], cke[0], s_n[0], ras_n, cas_n, we_n, dm[7], rba, addr[ADDR_BITS-1:0], dq[63:56], dqs[7], dqs_n[7], , odt[0]);  

    ddr2 U14  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[0], rba, addr[ADDR_BITS-1:0], dq[ 7: 0], dqs[0], dqs_n[0], , odt[1]);
    ddr2 U18  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[1], rba, addr[ADDR_BITS-1:0], dq[15: 8], dqs[1], dqs_n[1], , odt[1]);
    ddr2 U13  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[2], rba, addr[ADDR_BITS-1:0], dq[23:16], dqs[2], dqs_n[2], , odt[1]);
    ddr2 U17  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[3], rba, addr[ADDR_BITS-1:0], dq[31:24], dqs[3], dqs_n[3], , odt[1]);
    ddr2 U12  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[4], rba, addr[ADDR_BITS-1:0], dq[39:32], dqs[4], dqs_n[4], , odt[1]);  
    ddr2 U16  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[5], rba, addr[ADDR_BITS-1:0], dq[47:40], dqs[5], dqs_n[5], , odt[1]);  
    ddr2 U11  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[6], rba, addr[ADDR_BITS-1:0], dq[55:48], dqs[6], dqs_n[6], , odt[1]);  
    ddr2 U15  (ck[1], ck_n[1], cke[1], s_n[1], ras_n, cas_n, we_n, dm[7], rba, addr[ADDR_BITS-1:0], dq[63:56], dqs[7], dqs_n[7], , odt[1]);  

endmodule
