---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: UAR.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card
--
-- Design Description:
-- Universal Asynchronous Receiver - Wrapper around KCPSM companion uart_rx
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity UAR is
  port(
    pClock   : in  std_logic;
    pnReset  : in  std_logic;
    pOE      : in  std_logic;
    pPAD     : in  std_logic_vector(7 downto 0);
    pRxD     : in  std_logic;
    pDataOut : out std_logic_vector(7 downto 0));
end UAR;

architecture RTL of UAR is

  constant cDataRead          : std_logic_vector(7 downto 0) := x"50";
  constant cBufferDataPresent : std_logic_vector(7 downto 0) := x"51";
  constant cBufferFull        : std_logic_vector(7 downto 0) := x"52";
  constant cBufferHalfFull    : std_logic_vector(7 downto 0) := x"53";

  signal Reset             : std_logic;
  signal OE                : std_logic;
  signal BufferDataPresent : std_logic;
  signal BufferFull        : std_logic;
  signal BufferHalfFull    : std_logic;
  signal DataOut           : std_logic_vector(7 downto 0);

  component uart_rx
    port (
      serial_in           : in  std_logic;
      data_out            : out std_logic_vector(7 downto 0);
      read_buffer         : in  std_logic;
      reset_buffer        : in  std_logic;
      en_16_x_baud        : in  std_logic;
      buffer_data_present : out std_logic;
      buffer_full         : out std_logic;
      buffer_half_full    : out std_logic;
      clk                 : in  std_logic);
  end component;

begin

  Reset <= not pnReset;
  OE    <= pOE when pPAD = cDataRead else '0';

  process (pnReset, pPAD, DataOut, BufferDataPresent, BufferFull, BufferHalfFull)
  begin
    case pPAD is
      when cDataRead          => pDataOut <= DataOut;
      when cBufferDataPresent => pDataOut <= "0000000" & BufferDataPresent;
      when cBufferFull        => pDataOut <= "0000000" & BufferFull;
      when cBufferHalfFull    => pDataOut <= "0000000" & BufferHalfFull;
      when others             => pDataOut <= (others => '0');
    end case;
  end process;

  uart_rx_1 : uart_rx
    port map (
      serial_in           => pRxD,
      data_out            => DataOut,
      read_buffer         => OE,
      reset_buffer        => Reset,
      en_16_x_baud        => '1',
      buffer_data_present => BufferDataPresent,
      buffer_full         => BufferFull,
      buffer_half_full    => BufferHalfFull,
      clk                 => pClock);

end architecture RTL;

