---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: BitIO.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Simple bitwise I/O port
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity BitIO is
  port(
    pClock   : in  std_ulogic;
    pnReset  : in  std_ulogic;
    pPAD     : in  std_logic_vector(7 downto 0);
    pWE      : in  std_ulogic;
    pDataIn  : in  std_ulogic;
    pPortIn  : in  std_logic_vector(7 downto 0);
    pDataOut : out std_ulogic;
    pPortOut : out std_logic_vector(7 downto 0));
end BitIO;

architecture RTL of BitIO is

  constant cBaseAddress : std_logic_vector(7 downto 3) := "00000";

begin

  -- Latch an output bit 
  process (pClock, pnReset)
  begin
    if pnReset = '0' then
      pPortOut <= (others => '0');
    elsif rising_edge(pClock) then
      -- set defaults here for non latching ports
      pPortOut(0)<='0'; -- pEERead
      pPortOut(1)<='0'; -- pEEWrite
      pPortOut(4)<='0'; -- overload clear command clear
      pPortOut(5)<='0'; -- EEPROM rd/wr clear
      pPortOut(6)<='0'; -- Sequence table rd/wr clear
      if pWE = '1' and pPAD(7 downto 3) = cBaseAddress then
        pPortOut(conv_integer(pPAD(2 downto 0))) <= pDataIn;
      end if;
    end if;
  end process;

  -- Read an input port 
  process (pPAD, pPortIn)
  begin
    if pPAD(7 downto 3) = cBaseAddress then
      pDataOut <= pPortIn(conv_integer(pPAD(2 downto 0)));
    else
      pDataOut <= '0';
    end if;
  end process;

end architecture RTL;
