# Xilinx CORE Generator 6.2.02i
# Username = Chris Garry
# COREGenPath = C:\Xilinx\coregen
# ProjectPath = C:\work\VHDL\Test2
# ExpandedProjectPath = C:\work\VHDL\Test2
# OverwriteFiles = True
# Core name: delay_value_ram
# Number of Primitives in design: 4
# Number of CLBs used in design cannot be determined when there is no RPMed logic
# Number of Slices used in design cannot be determined when there is no RPMed logic
# Number of LUT sites used in design: 0
# Number of LUTs used in design: 0
# Number of REG used in design: 0
# Number of SRL16s used in design: 0
# Number of Distributed RAM primitives used in design: 0
# Number of Block Memories used in design: 4
# Number of Dedicated Multipliers used in design: 0
# Number of HU_SETs used: 0
# 
SET BusFormat = BusFormatAngleBracketNotRipped
SET SimulationOutputProducts = VHDL
SET XilinxFamily = Spartan2
SET OutputOption = DesignFlow
SET DesignFlow = VHDL
SET FlowVendor = Other
SET FormalVerification = None
SELECT Dual_Port_Block_Memory Spartan2 Xilinx,_Inc. 5.0
CSET primitive_selection = Optimize_For_Area
CSET port_a_active_clock_edge = Rising_Edge_Triggered
CSET port_a_additional_output_pipe_stages = 0
CSET port_b_active_clock_edge = Rising_Edge_Triggered
CSET port_a_enable_pin = false
CSET port_a_write_enable_polarity = Active_High
CSET port_a_initialization_pin_polarity = Active_High
CSET global_init_value = 0
CSET port_a_init_pin = false
CSET select_primitive = 4kx1
CSET port_b_enable_pin = false
CSET width_b = 32
CSET port_a_init_value = 0
CSET width_a = 8
CSET depth_b = 512
CSET port_a_register_inputs = false
CSET component_name = delay_value_ram
CSET depth_a = 2048
CSET configuration_port_b = Write_Only
CSET port_b_write_enable_polarity = Active_High
CSET configuration_port_a = Read_Only
CSET port_b_init_value = 0
CSET port_b_handshaking_pins = false
CSET port_b_register_inputs = false
CSET port_b_initialization_pin_polarity = Active_High
CSET load_init_file = false
CSET port_a_enable_pin_polarity = Active_High
CSET port_a_handshaking_pins = false
CSET port_b_additional_output_pipe_stages = 0
CSET port_b_enable_pin_polarity = Active_High
CSET port_b_init_pin = false
CSET write_mode_port_b = Read_After_Write
CSET write_mode_port_a = Read_After_Write
GENERATE

