---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: DqsDelay.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- This module generate the delay in the dqs signal
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.Vcomponents.all;


entity DqsDelay is
  port (ClkIn  : in  std_ulogic;
        SelIn  : in  std_logic_vector(4 downto 0);
        ClkOut : out std_ulogic);
end DqsDelay;

architecture Str of DqsDelay is

  signal Delay1 : std_logic;
  signal Delay2 : std_logic;
  signal Delay3 : std_logic;
  signal Delay4 : std_logic;
  signal Delay5 : std_logic;

  attribute syn_noprune  : boolean;
  
  attribute syn_noprune of One   : label is true;
  attribute syn_noprune of Two   : label is true;
  attribute syn_noprune of Three : label is true;
  attribute syn_noprune of Four  : label is true;
  attribute syn_noprune of Five  : label is true;
  attribute syn_noprune of Six   : label is true;

begin

  One: LUT4
    generic map (INIT => x"f3c0")
    port map (I0  => '1',
              I1 => SelIn(4),
              I2 => Delay5,
              I3 => ClkIn,
              O  => ClkOut);
  
  Two: LUT4
    generic map (INIT => x"ee22")
    port map (I0 => ClkIn,
              I1 => SelIn(2),
              I2 => '1',
              I3 => Delay3,
              O  => Delay4);

  Three: LUT4
    generic map (INIT => x"e2e2")
    port map (I0 => ClkIn,
              I1 => SelIn(0),
              I2 => Delay1,
              I3 => '1',
              O  => Delay2);

  Four: LUT4
    generic map (INIT => x"ff00")
    port map (I0 => '1',
              I1 => '1',
              I2 => '1',
              I3 => ClkIn,
              O  => Delay1);

  Five: LUT4
    generic map (INIT => x"f3c0")
    port map (I0 => '1',
              I1 => SelIn(3),
              I2 => Delay4,
              I3 => ClkIn,
              O  => Delay5);

  Six: LUT4
    generic map (INIT => x"e2e2")
    port map (I0 => ClkIn,
              I1 => SelIn(1),
              I2 => Delay2,
              I3 => '1',
              O  => Delay3);

end Str;
