---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: AddressDecoder.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Address Decoder for Pulser Receiver Card (PRx) System FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity AddressDecoder is
  port(
    pPLX_LA      : in  std_logic_vector(31 downto 2);  -- PLX Local bus address 
    pPLX_LWR     : in  std_ulogic;       -- PLX Local Bus write NOT read
    pPLX_nREADY  : in  std_ulogic;       -- Ready
    pWnR         : in  std_ulogic;       -- Write NOT read from local controller
    pnSTROBE     : in  std_ulogic;       -- R/W strobe from local controller
    pnEN_RAM     : out std_ulogic;       -- Enable SRAM chips (CE)
    pnEN_Check   : out std_ulogic;       -- Enable Check register
    pnEN_Version : out std_ulogic;       -- Enable Version register
    pnEN_Command : out std_ulogic;       -- Enable Command / Status Registers
    pnEN_EEPROM  : out std_ulogic;       -- Enable EEPROM Block RAM
    pnEn_SeqTab  : out std_ulogic;       -- Enable Sequence table Block RAM
	  pnEN_GlbConf : out std_ulogic;       -- Enable Global configuration register
    pnEN_IOData0 : out std_ulogic;       -- Enable IO Data Register 0
    pnEN_IODir0  : out std_ulogic;       -- Enable IO Data Direction Register 0
    pnEN_IOData1 : out std_ulogic;       -- Enable IO Data Register 1
    pnEN_IODir1  : out std_ulogic;       -- Enable IO Data Direction Register 1
    pnWE         : out std_ulogic;       -- Write Enable
    pnOE         : out std_ulogic);      -- Output Enable
end AddressDecoder;

architecture RTL of AddressDecoder is
begin

  pnEN_RAM     <= '0' when pPLX_LA(31 downto 20) = x"004" else '1';
  pnEN_EEPROM  <= '0' when pPLX_LA(31 downto 20) = x"006" else '1';
  pnEn_SeqTab  <= '0' when pPLX_LA(31 downto 20) = x"007" else '1';
  pnEN_Check   <= '0' when pPLX_LA & "00" = x"00500000" else '1';
  pnEN_IOData0 <= '0' when pPLX_LA & "00" = x"00500004" else '1';
  pnEN_IODir0  <= '0' when pPLX_LA & "00" = x"00500008" else '1';
  pnEN_IOData1 <= '0' when pPLX_LA & "00" = x"0050000C" else '1';
  pnEN_IODir1  <= '0' when pPLX_LA & "00" = x"00500010" else '1';
  pnEN_Command <= '0' when pPLX_LA & "00" = x"00500014" else '1';
  pnEN_GlbConf <= '0' when pPLX_LA & "00" = x"005000f0" else '1';
  pnEN_Version <= '0' when pPLX_LA & "00" = x"005000fc" else '1';

  pnWE <= '0' when (((pPLX_LWR = '1') and (pPLX_nREADY = '0')) or ((pWnR = '1') and (pnSTROBE= '0')))  else '1';
  pnOE <= '0' when (((pPLX_LWR = '0') and (pPLX_nREADY = '0')) or ((pWnR = '0') and (pnSTROBE= '0')))  else '1';


end architecture RTL;

