# peripheral fpga UCF
NET "pPIO<2>"	LOC = "G4";
NET "pPIO<3>"	LOC = "G3";
NET "pPIO<4>"	LOC = "G1";
NET "pPIO<5>"	LOC = "F4";
NET "pPIO<6>"	LOC = "F2";
NET "pPIO<7>"	LOC = "F1";
NET "pPIO<8>"	LOC = "E2";
NET "pPIO<9>"	LOC = "D2";
NET "pPIO<10>"	LOC = "C2";
NET "pPIO<11>"	LOC = "C1";
NET "pPIO<12>"	LOC = "B3";
NET "pPIO<13>"	LOC = "B4";
NET "pPIO<14>"	LOC = "D5";
NET "pPIO<15>"	LOC = "C5";
NET "pPIO<16>"	LOC = "E6";
NET "pPIO<17>"	LOC = "C6";
NET "pPIO<18>"	LOC = "A6";
NET "pPIO<19>"	LOC = "E7";
NET "pPIO<20>"	LOC = "B7";
NET "pPIO<21>"	LOC = "D8";
NET "pPIO<22>"	LOC = "A8";
NET "pPIO<23>"	LOC = "D9";
NET "pPIO<24>"	LOC = "E10";
NET "pPIO<25>"	LOC = "C10";
NET "pPIO<26>"	LOC = "A10";
NET "pPIO<27>"	LOC = "E11";
NET "pPIO<28>"	LOC = "B11";
NET "pPIO<29>"	LOC = "D12";
NET "pPIO<30>"	LOC = "B12";
NET "pPIO<31>"	LOC = "A12";
NET "pPIO<32>"	LOC = "M13";
NET "pPIO<33>"	LOC = "L16";
NET "pPIO<34>"	LOC = "L15";
NET "pPIO<35>"	LOC = "L14";
NET "pPIO<36>"	LOC = "L13";
NET "pPIO<37>"	LOC = "L12";
NET "pPIO<38>"	LOC = "K16";
NET "pPIO<39>"	LOC = "K15";
NET "pPIO<40>"	LOC = "K14";
NET "pPIO<41>"	LOC = "K13";
NET "pPIO<42>"	LOC = "K12";
NET "pPIO<43>"	LOC = "J15";
NET "pPIO<44>"	LOC = "J14";
NET "pPIO<45>"	LOC = "J13";
NET "pPIO<46>"	LOC = "H16";
NET "pPIO<47>"	LOC = "H15";
NET "pPIO<48>"	LOC = "H14";
NET "pPIO<49>"	LOC = "H13";
NET "pPIO<50>"	LOC = "G15";
NET "pPIO<51>"	LOC = "G14";
NET "pPIO<52>"	LOC = "G13";
NET "pPIO<53>"	LOC = "G12";
NET "pPIO<54>"	LOC = "F16";
NET "pPIO<55>"	LOC = "F14";
NET "pPIO<56>"	LOC = "F13";
NET "pPIO<57>"	LOC = "F12";
NET "pPIO<58>"	LOC = "E15";
NET "pPIO<59>"	LOC = "E14";
NET "pPIO<60>"	LOC = "E13";
NET "pPIO<61>"	LOC = "D16";
NET "pPIO<62>"	LOC = "C16";
#
# Encoder Inputs
#
NET "pEncoder0In<0>"	LOC = "C12" | PULLDOWN;
NET "pEncoder0In<1>"	LOC = "A11" | PULLDOWN;
NET "pEncoder1In<0>"	LOC = "C11" | PULLDOWN;
NET "pEncoder1In<1>"	LOC = "D11" | PULLDOWN;
NET "pEncoder2In<0>"	LOC = "B10" | PULLDOWN;
NET "pEncoder2In<1>"	LOC = "D10" | PULLDOWN;
NET "pEncoder3In<0>"	LOC = "A9" | PULLDOWN;
NET "pEncoder3In<1>"	LOC = "B9" | PULLDOWN;
NET "pEncoder4In<0>"	LOC = "C8" | PULLDOWN;
NET "pEncoder4In<1>"	LOC = "A7" | PULLDOWN;
NET "pEncoder5In<0>"	LOC = "C7" | PULLDOWN;
NET "pEncoder5In<1>"	LOC = "D7" | PULLDOWN;
#
# Sensor Array Connections
#
NET "pProbeDSel"	LOC = "B6";
NET "pProbeSense"	LOC = "E1";
NET "pProbeTx" 		LOC = "B16" | IOBDELAY = NONE | SLEW = FAST;
NET "pProbeDClk" 	LOC = "E3";
NET "pProbeAper<0>"	LOC = "E4";
NET "pProbeAper<1>"	LOC = "F3";
NET "pProbeData<0>"	LOC = "D6";
NET "pProbeData<1>"	LOC = "A5";
NET "pProbeData<2>"	LOC = "B5";
NET "pProbeData<3>"	LOC = "A4";
NET "pProbeData<4>"	LOC = "A3";
NET "pProbeData<5>"	LOC = "A2";
NET "pProbeData<6>"	LOC = "B1";
NET "pProbeData<7>"	LOC = "D1";


#NET "dataclk" LOC = "F5"; #"PIO<89>"
NET "pTriggerOut_" LOC = "G2"; #"PIO<90>";
#NET "PULSE_OUT" 	FAST;
NET "pZ0"  LOC = "T2";
NET "pZ1"  LOC = "T3" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ2"  LOC = "T4" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ3"  LOC = "N5" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ4"  LOC = "P5" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ5"  LOC = "R5" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ6"  LOC = "T5" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ7"  LOC = "M6" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ8"  LOC = "N6" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ9"  LOC = "P6" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ10" LOC = "R6" | IOBDELAY = NONE | SLEW = FAST;
NET "pZ11" LOC = "T6" | IOBDELAY = NONE | SLEW = FAST;
#
# Calibration DAC signals
#
NET "pCalDac_SDI" LOC = "H4";
NET "pCalDac_CLK" LOC = "H3";
NET "pCalDac_nLD" LOC = "H2";
NET "pCalDac_nCS" LOC = "J4";
#
NET "pCAL<0>" LOC = "J3";
NET "pCAL<1>" LOC = "J2";
NET "pCAL<2>" LOC = "J1";
NET "pSEL_1M_50R" LOC = "G5";
NET "pSEL_AC_DC" LOC = "H1";
NET "pAIN<0>" LOC = "K2";
NET "pAIN<1>" LOC = "K3";
NET "pAIN<2>" LOC = "K4";
NET "pAIN<3>" LOC = "K5";
NET "pAUX<0>" LOC = "K1";
NET "pAUX<1>" LOC = "L5";
NET "pGAIN<0>" LOC = "L2";
NET "pGAIN<1>" LOC = "L1";
NET "pGAIN<2>" LOC = "M4";
NET "pGAIN<3>" LOC = "L3";
NET "pGAIN<4>" LOC = "L4";
NET "pGAIN<5>" LOC = "M3";
NET "pATOD_RANGE" LOC = "N1";
NET "pDATA_FORMAT" LOC = "M1";
NET "pSENSE" LOC = "M2";
NET "pDdsKey" LOC = "P1";
NET "pPORT_FORMAT" LOC = "N2";
NET "pDdsFsk" LOC = "R1";
NET "pSampleClk" LOC = "N8";
NET "pLCLK"		LOC = R8  | IOBDELAY = NONE | SLEW = FAST;  # C9 is bodged version
INST "CLKDLL0" LOC=DLL0;
INST "CLKDLL1" LOC=DLL2;
INST "BUFG0" LOC=GCLKBUF0;
INST "BUFG1" LOC=GCLKBUF2;
INST "BUFG2" LOC=GCLKBUF1;
#NET "PCLKIN"		LOC = C9;
#NET "MASTERCLK"	LOC = B8;
NET "pLD<0>" LOC = "D14";
NET "pLD<1>" LOC = "E16";
NET "pLD<2>" LOC = "F15";
NET "pLD<3>" LOC = "G16";
NET "pLD<4>" LOC = "J16";
NET "pLD<5>" LOC = "M16";
NET "pLD<6>" LOC = "N16";
NET "pLD<7>" LOC = "N14";
NET "pLD<8>" LOC = "M7";
NET "pLD<9>" LOC = "N7";
NET "pLD<10>" LOC = "P7";
NET "pLD<11>" LOC = "R7";
NET "pLD<12>" LOC = "T7";
NET "pLD<13>" LOC = "P8";
NET "pLD<14>" LOC = "T8";
NET "pLD<15>" LOC = "N9";
NET "pLD<16>" LOC = "P9";
NET "pLD<17>" LOC = "R9";
NET "pLD<18>" LOC = "T9";
NET "pLD<19>" LOC = "M10";
NET "pLD<20>" LOC = "N10";
NET "pLD<21>" LOC = "P10";
NET "pLD<22>" LOC = "R10";
NET "pLD<23>" LOC = "T10";
NET "pLD<24>" LOC = "M11";
NET "pLD<25>" LOC = "N11";
NET "pLD<26>" LOC = "P11";
NET "pLD<27>" LOC = "R11";
NET "pLD<28>" LOC = "T11";
NET "pLD<29>" LOC = "N12";
NET "pLD<30>" LOC = "P12";
NET "pLD<31>" LOC = "R12";
NET "pLA<2>" LOC = "T12";
NET "pLA<3>" LOC = "P13";
NET "pLA<4>" LOC = "R13";
NET "pLA<5>" LOC = "T13";
NET "pLA<6>" LOC = "T14";
NET "pLA<7>" LOC = "T15";
NET "pLA<8>"		LOC = R16;
NET "pLA<9>"		LOC = P16;
NET "pLWnR" LOC = "M14";
NET "pnLReset" LOC = "M15";
#NET "FPGAINIT"		LOC = N15
#NET "FPGABUSY"		LOC = C15
NET "pnFpgaCs" LOC = "B13";
#NET "FPGAWRITE"	LOC = C13
NET "pLED_D9" LOC = "A14";
NET "pLED_D8" LOC = "A13";
#NET "lclk" TNM_NET = "lclk"
#TIMESPEC "TS_lclk" = PERIOD "lclk" 16 ns HIGH 50 %
#NET "masterclk" TNM_NET = "masterclk"
#TIMESPEC "TS_masterclk" = PERIOD "masterclk" 10 ns HIGH 50 %
#INST "ld<0>" TNM = "local_data"
#INST "ld<1>" TNM = "local_data"
#INST "ld<2>" TNM = "local_data"
#INST "ld<3>" TNM = "local_data"
#INST "ld<4>" TNM = "local_data"
#INST "ld<5>" TNM = "local_data"
#INST "ld<6>" TNM = "local_data"
#INST "ld<7>" TNM = "local_data"
#INST "ld<8>" TNM = "local_data"
#INST "ld<9>" TNM = "local_data"
#INST "ld<10>" TNM = "local_data"
#INST "ld<11>" TNM = "local_data"
#INST "ld<12>" TNM = "local_data"
#INST "ld<13>" TNM = "local_data"
#INST "ld<14>" TNM = "local_data"
#INST "ld<15>" TNM = "local_data"
#INST "ld<16>" TNM = "local_data"
#INST "ld<17>" TNM = "local_data"
#INST "ld<18>" TNM = "local_data"
#INST "ld<19>" TNM = "local_data"
#INST "ld<20>" TNM = "local_data"
#INST "ld<21>" TNM = "local_data"
#INST "ld<22>" TNM = "local_data"
#INST "ld<23>" TNM = "local_data"
#INST "ld<24>" TNM = "local_data"
#INST "ld<25>" TNM = "local_data"
#INST "ld<26>" TNM = "local_data"
#INST "ld<27>" TNM = "local_data"
#INST "ld<28>" TNM = "local_data"
#INST "ld<29>" TNM = "local_data"
#INST "ld<30>" TNM = "local_data"
#INST "ld<31>" TNM = "local_data"
#TIMEGRP "local_data" OFFSET = IN 8 ns BEFORE "lclk"
#TIMESPEC "TSlclk_to_ff" = FROM "lclk" TO "FFS" 10 ns
######## clock constraints ########
NET "pLCLK" PERIOD = 15 ns LOW 50 %;
#NET "Sample2xClk" PERIOD = 5 ns LOW 50 %;
NET "pSampleClk" PERIOD = 10 ns LOW 50 %;
######## clock constraints end ########
######## Create time groups for rising and falling edge FFs ########
##
NET "pLCLK" TNM_NET = "LCLK_BE";
# Timegroup containing all FFs clocked by the rising edge of pLCLK
TIMEGRP "LCLK_RE" = RISING  LCLK_BE;
# Timegroup containing all FFs clocked by the falling edge of pLCLK
TIMEGRP "LCLK_FE" = FALLING  LCLK_BE;
#
#NET "Sample2xClk" TNM_NET = "S2xCLK_BE";
#TIMEGRP "S2xCLK_RE" = RISING  S2xCLK_BE;
#TIMEGRP "S2xCLK_FE" = FALLING  S2xCLK_BE;
#
#
#NET "pSampleClk" TNM_NET = "SCLK_BE";
#TIMEGRP "SCLK_RE" = RISING  SCLK_BE;
#TIMEGRP "SCLK_FE" = FALLING  SCLK_BE;
#
######## Create time groups for rising and falling edge FFs end ########
#
#TIMESPEC TS_SClkRE2SCLKRE=FROM:S2xCLK_RE:TO:S2xCLK_RE:5;
#TIMESPEC TS_S2xClk2SClk=FROM:S2xCLK_RE:TO:SCLK_RE:5;
######## Input Constraints ########
TIMESPEC TS_LD2ReLCLK=FROM:PADS(pLD*):TO:LCLK_RE:12;
TIMESPEC TS_La2ReLCLK=FROM:PADS(pLA*):TO:LCLK_RE:12;
TIMESPEC TS_FpgaCs2ReLCLK=FROM:PADS(pnFpgaCs):TO:LCLK_RE:12;
TIMESPEC TS_LWnR2ReLCLK=FROM:PADS(pLWnR):TO:LCLK_RE:12;
######## Input Constraints End ########
#
######## Output Constraints ########
TIMESPEC TS_ReLClk2DspIf=FROM:LCLK_RE:TO:PADS(pZ*):8;
TIMESPEC TS_ReLClk2LBusDat=FROM:LCLK_RE:TO:PADS(pLD*):13;
#TIMESPEC TS_ReSClk2TriggerOut=FROM:S2xCLK_RE:TO:PADS(pProbeTx):6;  # Just keep it tight
#TIMESPEC TS_RESClk2Probe1=FROM:SCLK_RE:TO:PADS(pProbeData*):15; # Just keep it tight
#TIMESPEC TS_RESClk2Probe2=FROM:SCLK_RE:TO:PADS(pProbeAper*):15; # Just keep it tight
#TIMESPEC TS_RESClk2Probe3=FROM:SCLK_RE:TO:PADS(pProbeDSel):15; # Just keep it tight
#TIMESPEC TS_RESClk2Probe4=FROM:SCLK_RE:TO:PADS(pProbeDClk):15; # Just keep it tight
#
#TIMESPEC TS_RELClk2Probe1=FROM:LCLK_RE:TO:PADS(pProbeData*):15; # Just keep it tight
#TIMESPEC TS_RELClk2Probe2=FROM:LCLK_RE:TO:PADS(pProbeAper*):15; # Just keep it tight
#TIMESPEC TS_RELClk2Probe3=FROM:LCLK_RE:TO:PADS(pProbeDSel):15; # Just keep it tight
#TIMESPEC TS_RELClk2Probe4=FROM:LCLK_RE:TO:PADS(pProbeDClk):15; # Just keep it tight
######## Output Constraints End ########
#
######## Pad to Pad constraints ########
TIMESPEC TS_FpgaCs2LD=FROM:PADS(pnFpgaCs):TO:PADS(pLD*):13;
######## Pad to Pad constraints ########
NET "LCLK" TNM_NET = "LCLK";
#
# Multi-cycle paths
#
#  INST "DelayValueRam0_delay_value_ram0/*" TNM = "DelayRam";
#  INST "FocusUnitCtrl0_pProbeData_*" TNM = "ProbeData";
#  TIMESPEC TS_DelayRam2ProbeData=FROM:DelayRam:TO:ProbeData:30;
#  INST "TriggerPulseGen0_ByteCount*"    TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_DoneLastBits"  TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_StartTrigger"  TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_StartTrigger1" TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_StartTrigger2" TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_FinalBits*"    TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_vTemp*"        TNM = "ClkEn_Paths";
#  INST "TriggerPulseGen0_Tx_nRx"        TNM = "ClkEn_Paths";
#  TIMESPEC TS_MultiPath1=FROM:ClkEn_Paths:TO:ClkEn_Paths:20;
#
#  INST "TriggerPulseGen0_ShiftReg*"     TNM = "TP0_ShiftReg";
#  TIMESPEC TS_MultiPath2=FROM:ClkEn_Paths:TO:TP0_ShiftReg:20;
#
INST "EncoderMonitor0_EncInc*"        TNM = "ClkEn1_Paths";
INST "EncoderMonitor0_EncDec*"        TNM = "ClkEn1_Paths";
INST "EncoderMonitor0_LastInputs*"    TNM = "ClkEn1_Paths";
INST "EncoderMonitor0_EncCounts*"     TNM = "ClkEn2_Paths";
INST "EncoderMonitor0_IncHysterisis"  TNM = "ClkEn2_Paths";
INST "EncoderMonitor0_DecHysterisis"  TNM = "ClkEn2_Paths";
INST "EncoderMonitor0_pBScanTrigger"  TNM = "ClkEn2_Paths";
TIMESPEC TS_MultiPath3=FROM:ClkEn1_Paths:TO:ClkEn2_Paths:30;
TIMESPEC TS_MultiPath4=FROM:ClkEn1_Paths:TO:ClkEn1_Paths:100;
TIMESPEC TS_MultiPath5=FROM:ClkEn2_Paths:TO:ClkEn2_Paths:100;
#
INST "BScanCtrl0_ARepCount*"    TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_BRepCount*"    TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_IncScanCount"  TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_ScanCount*"    TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_RxCount*"      TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_BScanActive"   TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_RxActive"      TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_pTxCount*"     TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_IncRxCount"    TNM = "BScanCtrl_ClkEn_Paths";
INST "BScanCtrl0_pTriggerOut"   TNM = "BScanCtrl_ClkEn_Paths";
TIMESPEC TS_MultiPath6=FROM:BScanCtrl_ClkEn_Paths:TO:BScanCtrl_ClkEn_Paths:50;
#
# Calibration DAC outputs
TIMESPEC TS_ReLCLK2CalDac=FROM:LCLK_RE:TO:PADS(pCalDac_*):10;
#
# Generic IO
TIMESPEC TS_PIO2ReLClk=FROM:PADS(pPIO*):TO:LCLK_RE:25;  # No hurry!
TIMESPEC TS_ReLClk2PIO=FROM:LCLK_RE:TO:PADS(pPIO*):25;  # No hurry!