---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SimCtrlSeq1.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card FPGAs
--
-- Design Description:
--Simulation Control file (001) for Digitiser card testbench - with sequence table
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


entity SimCtrl is
  port(ToBusModel   : out tToBusModel;
       FromBusModel : in tFromBusModel;
       ToAdcModel   : out tToAdcModel;
       FromAdcModel : in tFromAdcModel;
       Trigger      : in std_ulogic;
       Ack          : out std_ulogic);
end entity SimCtrl;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00500000#;
  constant cSysCommandReg: integer := 16#00500014#;
  constant cSysStatusReg:  integer := 16#00500014#;

  constant cPerCheckReg:   integer := 16#00500400#;
  constant cTriggerCtrl:   integer := 16#00500404#;
  constant cPulseGen:      integer := 16#00500408#;
  constant cAScanCtrl:     integer := 16#00500410#;
  constant cBScanTrigCtrl: integer := 16#0050041C#;

  constant cGateStartStop:  integer := 16#00500438#;
  constant cGateAttributes: integer := 16#0050043C#;
  constant cGateSetup:      integer := 16#00500440#;

  constant cPerSequenceStep: integer := 16#0050045C#;
  constant cPerSequenceCtrl: integer := 16#00500460#;

  constant cDspSramCtrl:        integer := 16#00500258#;
  constant cDspTcgConfig:       integer := 16#00500260#;
  constant cDspSramCtrlNoScans: integer := 16#0050026C#;

  constant cDspSequenceStep: integer := 16#00500274#;
  constant cDspSequenceCtrl: integer := 16#00500278#;

  -- Define the base of the system SRAM
  constant cSysSramBase:     integer := 16#00400000#;

  -- Define the base of the sample SRAM
  constant cSampleSramBase:  integer := 16#00000000#;


begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;
    variable vTriggerRiseTime : time;

  begin

    Ack <= '0';

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: 8 step sequence test"));
    writeline (OUTPUT, vLine);

    -- Write to the Trigger Control registers for Steps 0-7
    for i in 0 to 7 loop
      LBusWrite(cPerSequenceStep, i, ToBusModel, FromBusModel);
      LBusWrite(cDspSequenceStep, i, ToBusModel, FromBusModel);

      LBusWrite(cTriggerCtrl, 0, ToBusModel, FromBusModel);
      LBusWrite(cPulseGen, (i+1)*50, ToBusModel, FromBusModel); -- 250ns, 500ns,
      LBusWrite(cAScanCtrl, 2400, ToBusModel, FromBusModel);
      LBusWrite(cDspSramCtrl, 2400, ToBusModel, FromBusModel);
      LBusWrite(cDspTcgConfig, 3, ToBusModel, FromBusModel);
      LBusWrite(cBScanTrigCtrl, 16#00070000#, ToBusModel, FromBusModel);
    end loop;
    -- total of 8 AScans per BScan
    LBusWrite(cDspSramCtrlNoScans, 7, ToBusModel, FromBusModel);
    -- start 8 step sequence
    LBusWrite(cDspSequenceCtrl, 16#00000007#, ToBusModel, FromBusModel);
    LBusWrite(cPerSequenceCtrl, 16#80000007#, ToBusModel, FromBusModel);

    -- Start the scan data (send 8 A-Scans)
    AdcSendPattern(0, 8, ToAdcModel, FromAdcModel);

    for i in 0 to 32 loop
      wait until rising_edge(Trigger);
      vTriggerRiseTime := now;

      wait until falling_edge(Trigger);
      if (now - vTriggerRiseTime /= ((i mod 8) + 1) * 250 ns) then
        write (vLine, string'("Testbench: Error - Tx Pulse width incorrect."));
        writeline (OUTPUT, vLine);
        vTestFail := true;
      end if;
        
      wait for 100 us;
      Ack <= '1', '0' after 100 ns;
    end loop;


    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;