---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: CtrlControl.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card Control FPGA
--
-- Design Description:
-- Central Control Block for Pulser Receiver Card (PRx) Control FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity CtrlControl is
  port(
    pnReset  : in  std_ulogic;           -- Active low reset
    pClock   : in  std_ulogic;           -- System Clock 
    pDataIn  : in  std_logic_vector(7 downto 0);
    pDataOut : out std_logic_vector(7 downto 0);
    pAddress : out std_logic_vector(31 downto 0);
    pPAD     : out std_logic_vector(7 downto 0);
    pOE      : out std_ulogic;
    pWE      : out std_ulogic;
    pSRxD    : in  std_ulogic;           -- Serial receive
    pSTxD    : out std_ulogic);          -- Serial transmit
end CtrlControl;

architecture RTL of CtrlControl is

  component CtrlKCPSM
    port (
      port_id      : out std_logic_vector(7 downto 0);
      write_strobe : out std_ulogic;
      read_strobe  : out std_logic;
      out_port     : out std_logic_vector(7 downto 0);
      in_port      : in  std_logic_vector(7 downto 0);
      interrupt    : in  std_ulogic;
      reset        : in  std_ulogic;
      clk          : in  std_ulogic);
  end component;

  component UAR
    port (
      pClock   : in  std_ulogic;
      pnReset  : in  std_ulogic;
      pOE      : in  std_logic;
      pPAD     : in  std_logic_vector(7 downto 0);
      pRxD     : in  std_ulogic;
      pDataOut : out std_logic_vector(7 downto 0));
  end component;

  component UAT
    port (
      pClock   : in  std_ulogic;
      pnReset  : in  std_ulogic;
      pWE      : in  std_ulogic;
      pPAD     : in  std_logic_vector(7 downto 0);
      pDataIn  : in  std_logic_vector(7 downto 0);
      pTxD     : out std_ulogic;
      pDataOut : out std_logic_vector(7 downto 0));
  end component;

  component AddressCounter
    port (
      pClock      : in  std_ulogic;
      pnReset     : in  std_ulogic;
      pWE         : in  std_ulogic;
      pDataIn     : in  std_logic_vector(7 downto 0);
      pPAD        : in  std_logic_vector(7 downto 0);
      pAddressOut : out std_logic_vector(31 downto 0));
  end component;

  signal DataOut : std_logic_vector(7 downto 0);
  signal DataIn  : std_logic_vector(7 downto 0);
  signal Din1    : std_logic_vector(7 downto 0);
  signal Din2    : std_logic_vector(7 downto 0);
  signal PAD     : std_logic_vector(7 downto 0);
  signal OE      : std_ulogic;
  signal WE      : std_ulogic;

  signal Reset   : std_ulogic;

begin
  
  Reset    <= not pnReset;
  DataIn   <= pDataIn or Din1 or Din2;
  pDataOut <= DataOut;
  pPAD     <= PAD;
  pOE      <= OE;
  pWE      <= WE;

  picoBlaze_1 : CtrlKCPSM
    port map (
      port_id      => PAD,
      write_strobe => WE,
      read_strobe  => OE,
      out_port     => DataOut,
      in_port      => DataIn,
      interrupt    => '0',
      reset        => Reset,
      clk          => pClock);

  UAT_1 : UAT
    port map (
      pClock   => pClock,
      pnReset  => pnReset,
      pWE      => WE,
      pPAD     => PAD,
      pDataIn  => DataOut,
      pTxD     => pSTxD,
      pDataOut => Din1);

  UAR_1 : UAR
    port map (
      pClock   => pClock,
      pnReset  => pnReset,
      pOE      => OE,
      pPAD     => PAD,
      pRxD     => pSRxD,
      pDataOut => Din2);

  AddressCounter_1 : AddressCounter
    port map (
      pClock      => pClock,
      pnReset     => pnReset,
      pWE         => WE,
      pDataIn     => DataOut,
      pPAD        => PAD,
      pAddressOut => pAddress);

end architecture RTL;

