---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: SimCtrl004.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card FPGAs
--
-- Design Description:
--Simulation Control file (009) for Digitiser card testbench
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


entity SimCtrl is
  port(ToBusModel   : out tToBusModel;
       FromBusModel : in tFromBusModel;
       ToAdcModel   : out tToAdcModel;
       FromAdcModel : in tFromAdcModel);
end entity SimCtrl;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00500000#;
  constant cSysCommandReg: integer := 16#00500014#;
  constant cSysStatusReg:  integer := 16#00500014#;

  constant cPerCheckReg:   integer := 16#00500400#;

  constant cGateStartStop:  integer := 16#00500438#;
  constant cGateAttributes: integer := 16#0050043C#;
  constant cGateSetup:      integer := 16#00500440#;

  -- Define the base of the system SRAM
  constant cSysSramBase:   integer := 16#00400000#;

  -- Define the base of the sample SRAM
  constant cSampleSramBase:   integer := 16#00000000#;


begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Doing shortened FPGA configuration to reduce simulation time"));
    writeline (OUTPUT, vLine);

    -- Program the FPGAs - actually skip full configuration simulation
    LBusWrite(cSysSramBase, 16#DEADBEEF#, ToBusModel, FromBusModel);
    LBusWrite(cSysCommandReg, 16#00000011#, ToBusModel, FromBusModel);

    -- Try to access the check register, should be delayed until FPGAs have been configured
    LBusWrite(cSysCheckReg, 16#01234567#, ToBusModel, FromBusModel);
    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FEDCBA98# then
      write (vLine, string'("Testbench: Error - Expected 0xFEDCBA98 from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    else
      write (vLine, string'("Testbench: Shortened FPGA configuration complete"));
      writeline (OUTPUT, vLine);
    end if;

    -- Setup values for the number of samples
    LBusWrite(16#00500258#, 16#0000019F#, ToBusModel, FromBusModel);

    -- Select external trigger
    LBusWrite(16#00500404#, 16#00000000#, ToBusModel, FromBusModel);

    write (vLine, string'("Testbench: Test 1 (Gates 1 to 3) - Bipolar Threshold - Peak - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1 (Gates 1 to 3) - Detecting Distance of 1st, 2nd and largest peaks"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1 (Gate 4) - Bipolar Threshold - peak - relative to gate 2"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1 (Gate 4) - Detecting Distance of 2nd peak"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1 (Gates 5 to 7) - Bipolar Threshold - Peak - relative to gate 3"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 1 (Gates 5 to 7) - Detecting Distance of 1st, 2nd and 3rd peaks"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00D0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00D0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000001#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but distance of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#10D0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but distance of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#F0D0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but distance of 1st peak relative to Gate 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00D0212E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but distance of 1st peak relative to Gate 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00D0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but distance of 2nd peak relative to Gate 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#10D0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to as Gate 1 but distance of 3rd peak relative to Gate 3 (does not exist)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#20D0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F4006A# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F4006A from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400CE# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400CE from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40196# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40196 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC0132# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC0132 from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B19001FA# then
      write (vLine, string'("Testbench: Error - Expected 0xB19001FA from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B190025E# then
      write (vLine, string'("Testbench: Error - Expected 0xB190025E from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1900000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1900000 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    --
    -- Setup new gate values for new tests
    --

    --
    -- Setup new gate values for new test
    --
    write (vLine, string'("Testbench: Test 2 (Gates 1 to 3) - Bipolar Threshold - Trailing Flank - Test pattern 0"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2 (Gates 1 to 3) - Detecting Distance of 1st, 2nd and largest peaks"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2 (Gate 4) - Bipolar Threshold - Trailing Flank - relative to gate 2"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2 (Gate 4) - Detecting Distance of 2nd peak"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2 (Gates 5 to 7) - Bipolar Threshold - Trailing Flank - relative to gate 3"));
    writeline (OUTPUT, vLine);
    write (vLine, string'("Testbench: Test 2 (Gates 5 to 7) - Detecting Distance of 1st, 2nd and 3rd peaks"));
    writeline (OUTPUT, vLine);

    -- Setup values for Interface Gate start/stop + attributes
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0012E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000000#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000000# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 1 start/stop + attributes
    -- Set up to be exactly the same as Interface Gate
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000001#, ToBusModel, FromBusModel);
    vRData := 16#80000001#;
    while vRData /= 16#00000001# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 2 start/stop + attributes
    -- Set up to as Gate 1 but distance of peak 1
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#10B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000002#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000002# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 3 start/stop + attributes
    -- Set up to as Gate 1 but distance of largest peak
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#F0B0F12E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000003#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000003# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 4 start/stop + attributes
    -- Set up to as Gate 1 but distance of 1st peak relative to Gate 2
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0212E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000004#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000004# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 5 start/stop + attributes
    -- Set up to as Gate 1 but distance of 1st peak relative to Gate 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#00B0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000005#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000005# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 6 start/stop + attributes
    -- Set up to as Gate 1 but distance of 2nd peak relative to Gate 3
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#10B0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000006#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000006# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup values for Gate 7 start/stop + attributes
    -- Set up to as Gate 1 but distance of 3rd peak relative to Gate 3 (does not exist)
    LBusWrite(cGateStartStop, 16#02C00000#, ToBusModel, FromBusModel);
    LBusWrite(cGateAttributes, 16#20B0312E#, ToBusModel, FromBusModel);
    LBusWrite(cGateSetup, 16#00000007#, ToBusModel, FromBusModel);
    vRData := 16#80000000#;
    while vRData /= 16#00000007# loop
      LBusRead(cGateSetup, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Setup the No of Scans control register
    -- Multiple A-Scan + Multiple C-Scan - 4 of each
    LBusWrite(16#0050026C#, 16#80000003#, ToBusModel, FromBusModel);

    wait for 2 us;

    -- Start the scan data (send 4 A-Scans)
    AdcSendPattern(0, 4, ToAdcModel, FromAdcModel);

    -- Poll the Data Sampling Status register until the data available bit (0) is 1
    vRData := 0;
    while (vRData mod 2) = 0 loop
      LBusRead(16#00500264#, vRData, ToBusModel, FromBusModel);
      wait for 1 us;
    end loop;

    -- Check the correct C-Scan data has arrived
    LBusRead(16#00300000#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#43534E00# then
      write (vLine, string'("Testbench: Error - Expected 0x43534E00 from Sample SRAM (C-Scan 1 header)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300004#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40069# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40069 from Sample SRAM (Gate 0 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300008#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F40091# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F40091 from Sample SRAM (Gate 1 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030000C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F400F5# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F400F5 from Sample SRAM (Gate 2 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300010#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1F401D1# then
      write (vLine, string'("Testbench: Error - Expected 0xB1F401D1 from Sample SRAM (Gate 3 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300014#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B2BC016A# then
      write (vLine, string'("Testbench: Error - Expected 0xB2BC016A from Sample SRAM (Gate 4 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300018#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1900212# then
      write (vLine, string'("Testbench: Error - Expected 0xB1900212 from Sample SRAM (Gate 5 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#0030001C#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#B1900271# then
      write (vLine, string'("Testbench: Error - Expected 0xB1900271 from Sample SRAM (Gate 6 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusRead(16#00300020#, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#A1900000# then
      write (vLine, string'("Testbench: Error - Expected 0xA1900000 from Sample SRAM (Gate 7 result)"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;