# Local bus
NET "nLRESET" LOC = AH16 | IOSTANDARD = LVCMOS33;
NET "LCLK"	  LOC = AK16 | IOSTANDARD = LVCMOS33;

NET "LCLK" TNM_NET = LCLK;
TIMESPEC TS_LCLK = PERIOD LCLK 15.151 ns HIGH 50%;
TIMEGRP "LBUS" OFFSET = IN 7.5 ns AFTER "LCLK";
TIMEGRP "LBUS" OFFSET = OUT 4.2 ns BEFORE "LCLK";

NET "LWnR"	  LOC = AB16 | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<0>"	  LOC = AK28 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<1>"	  LOC = AH27 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<2>"	  LOC = AJ27 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<3>"	  LOC = AK27 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<4>"	  LOC = AJ26 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<5>"	  LOC = AK26 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<6>"	  LOC = AG26 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<7>"	  LOC = AF25 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<8>"	  LOC = AD24 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<9>"	  LOC = AC23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<10>"  LOC = AD23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<11>"  LOC = AE23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<12>"  LOC = AF23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<13>"  LOC = AG23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<14>"  LOC = AH23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<15>"  LOC = AJ23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<16>"  LOC = AK23 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<17>"  LOC = AB22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<18>"  LOC = AC22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<19>"  LOC = AE22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<20>"  LOC = AF22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<21>"  LOC = AG22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<22>"  LOC = AJ22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<23>"  LOC = AK22 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<24>"  LOC = AD21 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<25>"  LOC = AE21 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<26>"  LOC = AH21 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<27>"  LOC = AJ21 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<28>"  LOC = AB21 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<29>"  LOC = AA20 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<30>"  LOC = AC20 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LD<31>"  LOC = AD20 | IOBDELAY = NONE  | SLEW = FAST | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<2>"   LOC = AE20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<3>"   LOC = AF20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<4>"   LOC = AG20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<5>"   LOC = AH20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<6>"   LOC = AJ20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<7>"   LOC = AK20 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<8>"   LOC = AA19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<9>"   LOC = AB19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<10>"  LOC = AC19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<11>"  LOC = AD19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<12>"  LOC = AE19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<13>"  LOC = AF19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<14>"  LOC = AG19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<15>"  LOC = AH19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<16>"  LOC = AJ19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<17>"  LOC = AK19 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<18>"  LOC = AA18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<19>"  LOC = AB18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<20>"  LOC = AC18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<21>"  LOC = AE18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<22>"  LOC = AF18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<23>"  LOC = AG18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<24>"  LOC = AJ18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<25>"  LOC = AK18 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<26>"  LOC = AA17 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<27>"  LOC = AB17 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<28>"  LOC = AE17 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<29>"  LOC = AH17 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<30>"  LOC = AJ17 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LA<31>"  LOC = AA16 | IOBDELAY = NONE | TNM= "LBUS" | IOSTANDARD = LVCMOS33;

NET "nADS"    LOC = "AC16" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nBLAST"  LOC = "AD16" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nREADY"  LOC = "AE16" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nWAIT"   LOC = "AF16" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nBTERM"  LOC = "W29" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLBE<0>" LOC = "T27" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLBE<1>" LOC = "T28" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLBE<2>" LOC = "T29" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLBE<3>" LOC = "T30" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;

NET "BREQi"	  LOC = "V29" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "BREQo"	  LOC = "T26" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nDREQ0"  LOC = "T25" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nDREQ1"  LOC = "T24" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nDACK0"  LOC = "T23" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nDACK1"  LOC = "T22" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLINTi"  LOC = "T21" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLINTo"  LOC = "U29" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nLSERR"  LOC = "U28" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "DP<0>"	  LOC = "U25" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "DP<1>"	  LOC = "U24" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "DP<2>"	  LOC = "U22" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "DP<3>"	  LOC = "U21" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nBIGEND" LOC = "V30" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LHOLD"	  LOC = "W26" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "LHOLDA"  LOC = "V25" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "USERi"	  LOC = "V23" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "USERo"	  LOC = "V22" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nEOT"	  LOC = "V21" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nCCS"	  LOC = "W21" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;
NET "nPMEIN"  LOC = "W30" | TNM= "LBUS" | IOSTANDARD = LVCMOS33;

NET "GPIO<0>" LOC = "Y30" | IOSTANDARD = LVCMOS33;
NET "GPIO<1>" LOC = "Y29" | IOSTANDARD = LVCMOS33;
NET "GPIO<2>" LOC = "Y28" | IOSTANDARD = LVCMOS33;
NET "GPIO<3>" LOC = "Y27" | IOSTANDARD = LVCMOS33;

# A to D Signals
NET "AD_DcoP" LOC = "AH15" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = IBUF;
NET "AD_DcoN" LOC = "AJ15" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = IBUF;
NET "AD_DP<0>" LOC = "AF15" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<0>" LOC = "AG15" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<1>" LOC = "AH14" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<1>" LOC = "AJ14" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<2>" LOC = "AJ13" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<2>" LOC = "AK13" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<3>" LOC = "AF13" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<3>" LOC = "AG13" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<4>" LOC = "AJ12" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<4>" LOC = "AK12" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<5>" LOC = "AG12" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<5>" LOC = "AH12" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<6>" LOC = "AJ11" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<6>" LOC = "AK11" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<7>" LOC = "AG11" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<7>" LOC = "AH11" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<8>" LOC = "AH10" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<8>" LOC = "AJ10" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<9>" LOC = "AF9" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<9>" LOC = "AG9" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<10>" LOC = "AJ8" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<10>" LOC = "AK8" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DP<11>" LOC = "AG7" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_DN<11>" LOC = "AH7" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_OrP" LOC = "AD7" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "AD_OrN" LOC = "AE7" | IOSTANDARD = "LVDS_25_DCI" | IOBDELAY = NONE;
NET "nAD_Reset" LOC = "AG5" | IOSTANDARD = "LVCMOS25";
NET "nAD_Cs" LOC = "AF6" | IOSTANDARD = "LVCMOS25";
NET "AD_SClk" LOC = "AH6" | IOSTANDARD = "LVCMOS25";
NET "AD_SDio" LOC = "AJ6" | IOSTANDARD = "LVCMOS25";
NET "AD_DcoP" TNM_NET = SYSCLK;
NET "AD_DcoN" TNM_NET = SYSCLK;
TIMESPEC TS_SYSCLK = PERIOD SYSCLK 5.0 ns HIGH 50%;
#NET "AD_DP<*>" OFFSET = IN 0.3 ns AFTER "AD_DcoP";
#NET "AD_DN<*>" OFFSET = IN 0.3 ns AFTER "AD_DcoP";
INST "AD_DP<*>" TNM= "AD_DATA";
INST "AD_DN<*>" TNM= "AD_DATA";
TIMEGRP "AD_DATA" OFFSET = IN 0.5 VALID 4 AFTER "AD_DcoP";

INST "AdcD2*" AREA_GROUP = ADC_D2;
AREA_GROUP "ADC_D2" RANGE = SLICE_X0Y0:SLICE_X127Y1;

NET "LBus/Reg_*" TIG;

#INST "TrigGen/AScanTimeCount*" TNM="TRIG_TIMER";
#INST "TrigGen/SeqTimeCount*" TNM="TRIG_TIMER";
#INST "TrigGen/SequenceCount*" TNM="TRIG_TIMER";
#INST "TrigGen/iSequenceActive" TNM="TRIG_TIMER";
#INST "TrigGen/FreeRunningPulse" TNM="TRIG_TIMER";
#INST "TrigGen/IntTrigger" TNM="TRIG_TIMER";
#TIMESPEC TS_TRIG_TIMER = FROM "TRIG_TIMER" TO "TRIG_TIMER" TS_SYSCLK*2;
#
#INST "RamWrite/StepCount*" TNM="WRI_SEQCOUNT";
#INST "RamWrite/SequencesCount*" TNM="WRI_SEQCOUNT";
#TIMESPEC TS_WRI_SEQCOUNT = FROM "WRI_SEQCOUNT" TO "WRI_SEQCOUNT" TS_SYSCLK*2;
#INST "RamWrite/EncoderSel*" TNM="WRI_ENCSEL";
#TIMESPEC TS_WRI_ENCSEL = FROM "WRI_ENCSEL" TO "WRI_ENCSEL" TS_SYSCLK*2;
#INST "RamWrite/CtrlState*" TNM="WRI_CTRLST";
#TIMESPEC TS_WRI_ENCSEL_CTRLST = FROM "WRI_ENCSEL" TO "WRI_CTRLST" TS_SYSCLK*2;
#INST "RamArb/AScanAddr*" TNM="ARB_ADDRCOUNT";
#TIMESPEC TS_ARB_ADDRCOUNT = FROM "ARB_ADDRCOUNT" TO "ARB_ADDRCOUNT" TS_SYSCLK*2;

INST "LBus/Addr*" TNM="ARB_LBUSADDR";
INST "RamArb/RamAddr*" TNM="ARB_RAMADDR";
INST "RamArb/RamDMask*" TNM="ARB_RAMADDR";
INST "RamArb/LRdData*" TNM="ARB_RAMADDR";
TIMESPEC TS_LBUS_RAM_ADDR = FROM "ARB_LBUSADDR" TO "ARB_RAMADDR" TS_LCLK;
INST "LBus/LRamWr"  TNM="ARB_LBUSRDWR";
INST "LBus/LRamRd"  TNM="ARB_LBUSRDWR";
INST "RamArb/iRamWr" TNM="ARB_RAMRDWR";
INST "RamArb/iRamRd" TNM="ARB_RAMRDWR";
INST "RamArb/LDelay" TNM="ARB_RAMRDWR";
TIMESPEC TS_LBUS_RAM_WR = FROM "ARB_LBUSRDWR" TO "ARB_RAMRDWR" TS_LCLK;
INST "LBus/WrData*" TNM="ARB_LBUSWRDATA";
INST "RamArb/RamDIn*" TNM="ARB_RAMWRDATA";
TIMESPEC TS_LBUS_RAM_WRDATA = FROM "ARB_LBUSWRDATA" TO "ARB_RAMWRDATA" TS_LCLK;

INST "TrigGen/AScanStart" RLOC=X0Y0;
INST "TrigGen/AScanStart" U_SET = AScan_Counter;
INST "RamWrite/AScanCount_0" RLOC=X1Y0;
INST "RamWrite/AScanCount_0" U_SET = AScan_Counter;
INST "RamWrite/AScanEn" RLOC=X0Y1;
INST "RamWrite/AScanEn" U_SET = AScan_Counter;

INST "RamArb/Fifo0" LOC = RAMB16_X1Y13;
INST "RamArb/Fifo1" LOC = RAMB16_X1Y14;
INST "RamArb/Fifo2" LOC = RAMB16_X1Y15;
INST "RamArb/Fifo3" LOC = RAMB16_X1Y16;

INST "TrigGen/DelayedTrigger" RLOC=X0Y0;
INST "TrigGen/DelayedTrigger" U_SET = Del_Trigger;
INST "RamWrite/TrigPulse/iDOut" RLOC=X0Y1;
INST "RamWrite/TrigPulse/iDOut" U_SET = Del_Trigger;

#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<0>" RLOC=X0Y2;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<0>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*0" RLOC=X0Y2;
#INST "Gate1/MaxCurrentPeak*0" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<1>" RLOC=X0Y3;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<1>" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<2>" RLOC=X0Y3;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<2>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*1" RLOC=X0Y3;
#INST "Gate1/MaxCurrentPeak*1" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*2" RLOC=X0Y3;
#INST "Gate1/MaxCurrentPeak*2" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<3>" RLOC=X0Y4;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<3>" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<4>" RLOC=X0Y4;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<4>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*3" RLOC=X0Y4;
#INST "Gate1/MaxCurrentPeak*3" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*4" RLOC=X0Y4;
#INST "Gate1/MaxCurrentPeak*4" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<5>" RLOC=X0Y5;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<5>" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<6>" RLOC=X0Y5;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<6>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*5" RLOC=X0Y5;
#INST "Gate1/MaxCurrentPeak*5" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*6" RLOC=X0Y5;
#INST "Gate1/MaxCurrentPeak*6" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<7>" RLOC=X0Y6;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<7>" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<8>" RLOC=X0Y6;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<8>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*7" RLOC=X0Y6;
#INST "Gate1/MaxCurrentPeak*7" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*8" RLOC=X0Y6;
#INST "Gate1/MaxCurrentPeak*8" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<9>" RLOC=X0Y7;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<9>" U_SET = Gate1;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<10>" RLOC=X0Y7;
#INST "Gate1/Mcompar_MaxPeakUpdate_cmp_lt0000_cy<10>" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*9" RLOC=X0Y7;
#INST "Gate1/MaxCurrentPeak*9" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak*10" RLOC=X0Y7;
#INST "Gate1/MaxCurrentPeak*10" U_SET = Gate1;
#INST "Gate1/MaxCurrentPeak_not00021" RLOC=X0Y8;
#INST "Gate1/MaxCurrentPeak_not00021" U_SET = Gate1;
#INST "Gate1/MaxPeakUpdate" RLOC=X0Y8;
#INST "Gate1/MaxPeakUpdate" U_SET = Gate1;
#INST "Gate1/PeakMaxima" RLOC=X0Y9;
#INST "Gate1/PeakMaxima" U_SET = Gate1;
#
#INST "Gate1/NewSampleData_0" RLOC=X1Y0;
#INST "Gate1/NewSampleData_0" U_SET = Gate1;
#INST "Gate1/NewSampleData_1" RLOC=X1Y3;
#INST "Gate1/NewSampleData_1" U_SET = Gate1;
#INST "Gate1/NewSampleData_2" RLOC=X1Y2;
#INST "Gate1/NewSampleData_2" U_SET = Gate1;
#INST "Gate1/NewSampleData_3" RLOC=X1Y2;
#INST "Gate1/NewSampleData_3" U_SET = Gate1;
#INST "Gate1/NewSampleData_4" RLOC=X1Y5;
#INST "Gate1/NewSampleData_4" U_SET = Gate1;
#INST "Gate1/NewSampleData_5" RLOC=X1Y5;
#INST "Gate1/NewSampleData_5" U_SET = Gate1;
#INST "Gate1/NewSampleData_6" RLOC=X1Y4;
#INST "Gate1/NewSampleData_6" U_SET = Gate1;
#INST "Gate1/NewSampleData_7" RLOC=X1Y4;
#INST "Gate1/NewSampleData_7" U_SET = Gate1;
#INST "Gate1/NewSampleData_8" RLOC=X1Y8;
#INST "Gate1/NewSampleData_8" U_SET = Gate1;
#INST "Gate1/NewSampleData_9" RLOC=X1Y8;
#INST "Gate1/NewSampleData_9" U_SET = Gate1;
#INST "Gate1/NewSampleData_10" RLOC=X1Y9;
#INST "Gate1/NewSampleData_10" U_SET = Gate1;
#
#INST "Gate1/Mcompar_vSampleLessPeakValue_cmp_lt0000_lut<0>" RLOC=X3Y2;
#INST "Gate1/Mcompar_vSampleLessPeakValue_cmp_lt0000_lut<0>" U_SET = Gate1;
#
#INST "Gate1/MaxTrigPeak_0" RLOC=X2Y2;
#INST "Gate1/MaxTrigPeak_0" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_1" RLOC=X2Y2;
#INST "Gate1/MaxTrigPeak_1" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_2" RLOC=X2Y3;
#INST "Gate1/MaxTrigPeak_2" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_3" RLOC=X2Y3;
#INST "Gate1/MaxTrigPeak_3" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_4" RLOC=X2Y4;
#INST "Gate1/MaxTrigPeak_4" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_5" RLOC=X2Y4;
#INST "Gate1/MaxTrigPeak_5" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_6" RLOC=X2Y5;
#INST "Gate1/MaxTrigPeak_6" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_7" RLOC=X2Y5;
#INST "Gate1/MaxTrigPeak_7" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_8" RLOC=X2Y6;
#INST "Gate1/MaxTrigPeak_8" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_9" RLOC=X2Y6;
#INST "Gate1/MaxTrigPeak_9" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_10" RLOC=X2Y7;
#INST "Gate1/MaxTrigPeak_10" U_SET = Gate1;
#INST "Gate1/MaxTrigPeak_not00021" RLOC=X2Y7;
#INST "Gate1/MaxTrigPeak_not00021" U_SET = Gate1;
#INST "Gate1/NewMaxPeak_not0001_F" RLOC=X2Y8;
#INST "Gate1/NewMaxPeak_not0001_F" U_SET = Gate1;
#INST "Gate1/NewMaxPeak_not0001_G" RLOC=X2Y8;
#INST "Gate1/NewMaxPeak_not0001_G" U_SET = Gate1;
#INST "Gate1/NewMaxPeak" RLOC=X2Y9;
#INST "Gate1/NewMaxPeak" U_SET = Gate1;
#INST "Gate1/NewSampleDataC_0" RLOC=X3Y0;
#INST "Gate1/NewSampleDataC_0" U_SET = Gate1;
#INST "Gate1/NewSampleDataC_1" RLOC=X3Y1;
#INST "Gate1/NewSampleDataC_1" U_SET = Gate1;
#INST "Gate1/TriggerRst1" RLOC=X3Y8;
#INST "Gate1/TriggerRst1" U_SET = Gate1;
#
#INST "Gate1/TimeCount_0" RLOC=X0Y0;
#INST "Gate1/TimeCount_0" U_SET = Gate1Time;
#INST "Gate1/Mcompar_GateActiveNext_cmp_eq0000_lut<0>" RLOC=X1Y0;
#INST "Gate1/Mcompar_GateActiveNext_cmp_eq0000_lut<0>" U_SET = Gate1Time;
#INST "Gate1/TimeDon" RLOC=X1Y10;
#INST "Gate1/TimeDon" U_SET = Gate1Time;
#INST "Gate1/GateAct" RLOC=X2Y6;
#INST "Gate1/GateAct" U_SET = Gate1Time;
#INST "Gate1/GateClose" RLOC=X2Y7;
#INST "Gate1/GateClose" U_SET = Gate1Time;
##INST "RamArb/AScanDone1" RLOC=X1Y9;
##INST "RamArb/AScanDone1" U_SET = Gate1Time;
#
#INST "Gate1/FirstZeroAfterPeak" AREA_GROUP = Gate1Zero;
#AREA_GROUP "Gate1Zero" GROUP = CLOSED;

# Relax gates to 100MHz operation
#INST "Gate*" TNM="GATE_GENERAL";
#INST "ResSel*" TNM="GATE_GENERAL";
#TIMESPEC TS_GATE_GENERAL = FROM "GATE_GENERAL" TO "GATE_GENERAL" TS_SYSCLK*2;

#INST "Gate0/MaxDataValue*" TNM="GATE0_MAXDATA";
#TIMESPEC TS_GATE0_MAXDATA = FROM "GATE0_MAXDATA" TO "GATE0_MAXDATA" TS_SYSCLK*2;
#INST "Gate0/SampleData*" TNM="GATE_NEWSAMPDATA";
#INST "Gate*/NewSampleEarly*" TNM="GATE_NEWSAMPEARLY";
#INST "Gate*/NewSampleData*" TNM="GATE_NEWSAMPDATA";
#TIMESPEC TS_GATE_NEWSAMPLEDATA = FROM "GATE_NEWSAMPEARLY" TO "GATE_NEWSAMPDATA" TS_SYSCLK*2;
#INST "Gate*/MaxDataValue*" TNM="GATEMAXVALUE";
#TIMESPEC TS_GATE_MAXDATARAW = FROM "GATE_NEWSAMPDATA" TO "GATEMAXVALUE" TS_SYSCLK*2;
#TIMESPEC TS_GATE_MAXDATA = FROM "GATEMAXVALUE" TO "GATEMAXVALUE" TS_SYSCLK*2;
#INST "Gate*/RawSampleEarly*" TNM="GATE_RAWSAMPEARLY";
#INST "Gate*/RawSampleData*" TNM="GATE_RAWSAMPDATA";
#TIMESPEC TS_GATE_RAWSAMPLEDATA = FROM "GATE_RAWSAMPEARLY" TO "GATE_RAWSAMPDATA" TS_SYSCLK*2;
#
#INST "Gate*/iGateFiring" TNM="GATE_FIRE";
#INST "Gate*/GateZeroFiring" TNM="GATE_FIRE";
#INST "Gate*/Trigger" TNM="GATE_TRIGGER";
##INST "Gate*/TriggerC" TNM="GATE_TRIGGER";
#INST "ResSel/GateFireTime*" TNM="GATE_TRIGGER";
#TIMESPEC TS_GATE_TRIG = FROM "GATE_FIRE" TO "GATE_TRIGGER" TS_SYSCLK*2;
#INST "GATE*/PeakCount*" TNM="GATE_PEAKCOUNT";
#TIMESPEC TS_GATE_PEAKCOUNT = FROM "GATE_TRIGGER" TO "GATE_PEAKCOUNT" TS_SYSCLK*2;
#
#INST "Gate*/TimeCount*" TNM="GATE_TIMECOUNT";
#INST "Gate*/TimeDone" TNM="GATE_TIMEDONE";
#TIMESPEC TS_GATE_TIMECOUNT = FROM "GATE_TIMECOUNT" TO "GATE_TIMECOUNT" TS_SYSCLK*2;
#TIMESPEC TS_GATE_TIMEDONE = FROM "GATE_TIMECOUNT" TO "GATE_TIMEDONE" TS_SYSCLK*2;
#INST "ResSel/TimeCount*" TNM="RESSEL_TIMECOUNT";
#TIMESPEC TS_RESSEL_TIMECOUNT = FROM "RESSEL_TIMECOUNT" TO "RESSEL_TIMECOUNT" TS_SYSCLK*2;
#INST "Gate0/TimeCount*" TNM="GATE0_TIMECOUNT";
#INST "Gate*/GateActive" TNM="GATE0_ACTIVE";
#TIMESPEC TS_GATE_ACTIVE = FROM "GATE_TIMECOUNT" TO "GATE0_ACTIVE" TS_SYSCLK*2;

# DDS
NET "DdsFSync" LOC = "N8" | IOSTANDARD = LVCMOS33;
NET "DdsSClk" LOC = "N9" | IOSTANDARD = LVCMOS33;
NET "DdsSData" LOC = "N10" | IOSTANDARD = LVCMOS33;
NET "DdsSleep" LOC = "M10" | IOSTANDARD = LVCMOS33;
NET "DdsReset" LOC = "M1" | IOSTANDARD = LVCMOS33;
NET "DdsPSelect" LOC = "M2" | IOSTANDARD = LVCMOS33;
NET "DdsFSelect" LOC = "M3" | IOSTANDARD = LVCMOS33;
NET "nDdsOscInh" LOC = "M4" | IOSTANDARD = LVCMOS33;

# Pulser
NET "PulsePFetP" LOC = "AF1" | IOSTANDARD = "LVDS_25";
NET "PulsePFetN" LOC = "AF2" | IOSTANDARD = "LVDS_25";
NET "PulseNFetP" LOC = "AG1" | IOSTANDARD = "LVDS_25";
NET "PulseNFetN" LOC = "AG2" | IOSTANDARD = "LVDS_25";

NET "ChTxP<0>" LOC = "T1" | IOSTANDARD = "LVDS_25";
NET "ChTxN<0>" LOC = "T2" | IOSTANDARD = "LVDS_25";
NET "ChTxP<1>" LOC = "T9" | IOSTANDARD = "LVDS_25";
NET "ChTxN<1>" LOC = "T10" | IOSTANDARD = "LVDS_25";
NET "ChTxP<2>" LOC = "V1" | IOSTANDARD = "LVDS_25";
NET "ChTxN<2>" LOC = "V2" | IOSTANDARD = "LVDS_25";
NET "ChTxP<3>" LOC = "V10" | IOSTANDARD = "LVDS_25";
NET "ChTxN<3>" LOC = "W10" | IOSTANDARD = "LVDS_25";
NET "ChTxP<4>" LOC = "W6" | IOSTANDARD = "LVDS_25";
NET "ChTxN<4>" LOC = "W7" | IOSTANDARD = "LVDS_25";
NET "ChTxP<5>" LOC = "Y7" | IOSTANDARD = "LVDS_25";
NET "ChTxN<5>" LOC = "Y8" | IOSTANDARD = "LVDS_25";
NET "ChTxP<6>" LOC = "AA6" | IOSTANDARD = "LVDS_25";
NET "ChTxN<6>" LOC = "AA7" | IOSTANDARD = "LVDS_25";
NET "ChTxP<7>" LOC = "AB4" | IOSTANDARD = "LVDS_25";
NET "ChTxN<7>" LOC = "AB5" | IOSTANDARD = "LVDS_25";

NET "ChCkP<0>" LOC = "T3" | IOSTANDARD = "LVDS_25";
NET "ChCkN<0>" LOC = "T4" | IOSTANDARD = "LVDS_25";
NET "ChCkP<1>" LOC = "U6" | IOSTANDARD = "LVDS_25";
NET "ChCkN<1>" LOC = "U7" | IOSTANDARD = "LVDS_25";
NET "ChCkP<2>" LOC = "V4" | IOSTANDARD = "LVDS_25";
NET "ChCkN<2>" LOC = "V5" | IOSTANDARD = "LVDS_25";
NET "ChCkP<3>" LOC = "W1" | IOSTANDARD = "LVDS_25";
NET "ChCkN<3>" LOC = "W2" | IOSTANDARD = "LVDS_25";
NET "ChCkP<4>" LOC = "Y1" | IOSTANDARD = "LVDS_25";
NET "ChCkN<4>" LOC = "Y2" | IOSTANDARD = "LVDS_25";
NET "ChCkP<5>" LOC = "Y10" | IOSTANDARD = "LVDS_25";
NET "ChCkN<5>" LOC = "AA10" | IOSTANDARD = "LVDS_25";
NET "ChCkP<6>" LOC = "AA9" | IOSTANDARD = "LVDS_25";
NET "ChCkN<6>" LOC = "AB8" | IOSTANDARD = "LVDS_25";
NET "ChCkP<7>" LOC = "AC1" | IOSTANDARD = "LVDS_25";
NET "ChCkN<7>" LOC = "AC2" | IOSTANDARD = "LVDS_25";

NET "ChRxP<0>" LOC = "T5" | IOSTANDARD = "LVDS_25";
NET "ChRxN<0>" LOC = "T6" | IOSTANDARD = "LVDS_25";
NET "ChRxP<1>" LOC = "U9" | IOSTANDARD = "LVDS_25";
NET "ChRxN<1>" LOC = "U10" | IOSTANDARD = "LVDS_25";
NET "ChRxP<2>" LOC = "V6" | IOSTANDARD = "LVDS_25";
NET "ChRxN<2>" LOC = "W5" | IOSTANDARD = "LVDS_25";
NET "ChRxP<3>" LOC = "W3" | IOSTANDARD = "LVDS_25";
NET "ChRxN<3>" LOC = "W4" | IOSTANDARD = "LVDS_25";
NET "ChRxP<4>" LOC = "Y5" | IOSTANDARD = "LVDS_25";
NET "ChRxN<4>" LOC = "Y6" | IOSTANDARD = "LVDS_25";
NET "ChRxP<5>" LOC = "AA2" | IOSTANDARD = "LVDS_25";
NET "ChRxN<5>" LOC = "AA3" | IOSTANDARD = "LVDS_25";
NET "ChRxP<6>" LOC = "AB1" | IOSTANDARD = "LVDS_25";
NET "ChRxN<6>" LOC = "AB2" | IOSTANDARD = "LVDS_25";
NET "ChRxP<7>" LOC = "AC3" | IOSTANDARD = "LVDS_25";
NET "ChRxN<7>" LOC = "AC4" | IOSTANDARD = "LVDS_25";

NET "IoOutTxP" LOC = "AC5" | IOSTANDARD = "LVDS_25";
NET "IoOutTxN" LOC = "AC6" | IOSTANDARD = "LVDS_25";
NET "IoOutCkP" LOC = "AC7" | IOSTANDARD = "LVDS_25";
NET "IoOutCkN" LOC = "AD6" | IOSTANDARD = "LVDS_25";
NET "IoOutRxP" LOC = "AD1" | IOSTANDARD = "LVDS_25";
NET "IoOutRxN" LOC = "AD2" | IOSTANDARD = "LVDS_25";

NET "IoInTxP" LOC = "AD3" | IOSTANDARD = "LVDS_25";
NET "IoInTxN" LOC = "AD4" | IOSTANDARD = "LVDS_25";
NET "IoInCkP" LOC = "AE2" | IOSTANDARD = "LVDS_25";
NET "IoInCkN" LOC = "AE3" | IOSTANDARD = "LVDS_25";
NET "IoInRxP" LOC = "AE5" | IOSTANDARD = "LVDS_25";
NET "IoInRxN" LOC = "AF4" | IOSTANDARD = "LVDS_25";

NET "OpPha<1>" LOC = "R1" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPhb<1>" LOC = "R2" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpIndex<1>" LOC = "R3" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPha<2>" LOC = "R4" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPhb<2>" LOC = "R5" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpIndex<2>" LOC = "R6" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPha<3>" LOC = "R7" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPhb<3>" LOC = "R8" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpIndex<3>" LOC = "R9" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPha<4>" LOC = "R10" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpPhb<4>" LOC = "P2" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;
NET "OpIndex<4>" LOC = "P3" | IOBDELAY = NONE | IOSTANDARD = LVCMOS33;

NET "FSerData"	LOC = "D15" | IOSTANDARD = LVCMOS33;
NET "nFSerOE"	LOC = "C15" | IOSTANDARD = LVCMOS33;
NET "FSerClk"	LOC = "AH29" | IOSTANDARD = LVCMOS33;
NET "FSerRClk"	LOC = "AH30" | IOSTANDARD = LVCMOS33;
NET "FSel0db" LOC = "L2" | IOSTANDARD = LVCMOS33;
NET "FSelN20db" LOC = "L1" | IOSTANDARD = LVCMOS33;
NET "FSelN40db" LOC = "L4" | IOSTANDARD = LVCMOS33;
NET "FSelP20db" LOC = "L3" | IOSTANDARD = LVCMOS33;

NET "nHVEnable" LOC = "P6" | IOSTANDARD = LVCMOS33;
NET "HVFeedback" LOC = "P7" | IOSTANDARD = LVCMOS33;
NET "nHVDisChg" LOC = "P9" | IOSTANDARD = LVCMOS33;
NET "nHVSync" LOC = "P10" | IOSTANDARD = LVCMOS33;
NET "HVSClk" LOC = "N1" | IOSTANDARD = LVCMOS33;
NET "HVSDIn" LOC = "N2" | IOSTANDARD = LVCMOS33;

NET "TcgDacClk" LOC = "G10" | SLEW = FAST | IOSTANDARD = LVCMOS33;
NET "TcgDacSleep" LOC = "A11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<0>" LOC = "F10" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<1>" LOC = "C10" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<2>" LOC = "B10" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<3>" LOC = "J10" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<4>" LOC = "K11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<5>" LOC = "H11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<6>" LOC = "G11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<7>" LOC = "F11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<8>" LOC = "E11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<9>" LOC = "D11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<10>" LOC = "C11" | IOSTANDARD = LVCMOS33;
NET "TcgDacD<11>" LOC = "B11" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<0>" LOC = "F9" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<1>" LOC = "H9" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<2>" LOC = "J9" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<3>" LOC = "A8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<4>" LOC = "B8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<5>" LOC = "C8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<6>" LOC = "D8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<7>" LOC = "E8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<8>" LOC = "F8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<9>" LOC = "G8" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<10>" LOC = "C7" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<11>" LOC = "D7" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<12>" LOC = "F7" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<13>" LOC = "F6" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<14>" LOC = "B6" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<15>" LOC = "C6" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<16>" LOC = "E6" | IOSTANDARD = LVCMOS33;
NET "TcgDacA<17>" LOC = "D5" | IOSTANDARD = LVCMOS33;
NET "nTcgDacBHE" LOC = "A5" | IOSTANDARD = LVCMOS33;
NET "nTcgDacBLE" LOC = "B5" | IOSTANDARD = LVCMOS33;
NET "nTcgDacOe" LOC = "A4" | IOSTANDARD = LVCMOS33;
NET "nTcgDacCs" LOC = "B4" | IOSTANDARD = LVCMOS33;
NET "nTcgDacWr" LOC = "C4" | IOSTANDARD = LVCMOS33;
##############################################################################################################
## Area Group Constraint For TCG module.
##############################################################################################################
INST "TCG/*" AREA_GROUP = tcg_ctl;
AREA_GROUP "tcg_ctl" RANGE = SLICE_X0Y140:SLICE_X33Y159;
#AREA_GROUP "tcg_ctl" GROUP = CLOSED;
##############################################################################################################
## Area Group Constraint For Trigger Generator module.
##############################################################################################################
INST "TrigGen/*" AREA_GROUP = trig_gen;
AREA_GROUP "trig_gen" RANGE = SLICE_X33Y104:SLICE_X62Y139;
#AREA_GROUP "trig_gen" GROUP = CLOSED;

# SDRAM
NET "SR_Ck<0>"	LOC = "B23" | IOSTANDARD = SSTL18_II;
NET "nSR_Ck<0>"	LOC = "A23" | IOSTANDARD = SSTL18_II;
NET "SR_Ck<1>"	LOC = "H28" | IOSTANDARD = SSTL18_II;
NET "nSR_Ck<1>"	LOC = "H27" | IOSTANDARD = SSTL18_II;
NET "SR_Cke<0>"	LOC = "A19" | IOSTANDARD = SSTL18_II;
NET "SR_Cke<1>"	LOC = "B19" | IOSTANDARD = SSTL18_II;

##############################################################################################################
## These paths are constrained to get rid of unconstrained paths.
##############################################################################################################
NET "RamClk" TNM_NET = "clk0";
#NET "RAMIf/DataPath/DqsDelayedCol*" TNM_NET = "dqs_clk";
#TIMESPEC "TS_CLK" = FROM "clk0" TO "dqs_clk"  18 ns DATAPATHONLY;

#TIMESPEC "TS_CLK0" = FROM "dqs_clk" TO "clk0" 18 ns DATAPATHONLY;

#NET "RAMIf/DataPath/GenFifo[*].GenCol*.FifoBit*/WCLK" TNM_NET = "fifo_clk";
#TIMESPEC "TS_DQS_CLK" = FROM "dqs_clk" TO "fifo_clk"  5 ns DATAPATHONLY;

#INST "RAMIf/DataPath/GenWrEn[*].Fifo*WrEnInst/*" TNM = "fifo_we_clk";
#TIMESPEC "TS_WE_CLK" = FROM "dqs_clk" TO "fifo_we_clk"  5 ns DATAPATHONLY;

#INST "RAMIf/DataPath/GenWrAddr[*].Fifo*WrAddrInst/*" TNM = "fifo_waddr_clk";
#TIMESPEC "TS_WADDR_CLK" = FROM "dqs_clk" TO "fifo_waddr_clk"  5 ns DATAPATHONLY;

#############################################################################################################
## Calibration Circuit Constraints
#############################################################################################################
## Placement constraints for LUTS in tap delay ckt
#############################################################################################################
INST "RAMIf/CkRst/Cal/TapDel/l0" RLOC=X0Y6;
INST "RAMIf/CkRst/Cal/TapDel/l0" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l1" RLOC=X0Y6;
INST "RAMIf/CkRst/Cal/TapDel/l1" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l2" RLOC=X0Y7;
INST "RAMIf/CkRst/Cal/TapDel/l2" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l3" RLOC=X0Y7;
INST "RAMIf/CkRst/Cal/TapDel/l3" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l4" RLOC=X1Y6;
INST "RAMIf/CkRst/Cal/TapDel/l4" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l5" RLOC=X1Y6;
INST "RAMIf/CkRst/Cal/TapDel/l5" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l6" RLOC=X1Y7;
INST "RAMIf/CkRst/Cal/TapDel/l6" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l7" RLOC=X1Y7;
INST "RAMIf/CkRst/Cal/TapDel/l7" U_SET = delay_calibration_chain;
  
INST "RAMIf/CkRst/Cal/TapDel/l8" RLOC=X0Y4;
INST "RAMIf/CkRst/Cal/TapDel/l8" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l9" RLOC=X0Y4;
INST "RAMIf/CkRst/Cal/TapDel/l9" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l10" RLOC=X0Y5;
INST "RAMIf/CkRst/Cal/TapDel/l10" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l11" RLOC=X0Y5;
INST "RAMIf/CkRst/Cal/TapDel/l11" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l12" RLOC=X1Y4;
INST "RAMIf/CkRst/Cal/TapDel/l12" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l13" RLOC=X1Y4;
INST "RAMIf/CkRst/Cal/TapDel/l13" U_SET = delay_calibration_chain;
 
INST "RAMIf/CkRst/Cal/TapDel/l14" RLOC=X1Y5;
INST "RAMIf/CkRst/Cal/TapDel/l14" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l15" RLOC=X1Y5;
INST "RAMIf/CkRst/Cal/TapDel/l15" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l16" RLOC=X0Y2;
INST "RAMIf/CkRst/Cal/TapDel/l16" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l17" RLOC=X0Y2;
INST "RAMIf/CkRst/Cal/TapDel/l17" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l18" RLOC=X0Y3;
INST "RAMIf/CkRst/Cal/TapDel/l18" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l19" RLOC=X0Y3;
INST "RAMIf/CkRst/Cal/TapDel/l19" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l20" RLOC=X1Y2;
INST "RAMIf/CkRst/Cal/TapDel/l20" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l21" RLOC=X1Y2;
INST "RAMIf/CkRst/Cal/TapDel/l21" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l22" RLOC=X1Y3;
INST "RAMIf/CkRst/Cal/TapDel/l22" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l23" RLOC=X1Y3;
INST "RAMIf/CkRst/Cal/TapDel/l23" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l24" RLOC=X0Y0;
INST "RAMIf/CkRst/Cal/TapDel/l24" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l25" RLOC=X0Y0;
INST "RAMIf/CkRst/Cal/TapDel/l25" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l26" RLOC=X0Y1;
INST "RAMIf/CkRst/Cal/TapDel/l26" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l27" RLOC=X0Y1;
INST "RAMIf/CkRst/Cal/TapDel/l27" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l28" RLOC=X1Y0;
INST "RAMIf/CkRst/Cal/TapDel/l28" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l29" RLOC=X1Y0;
INST "RAMIf/CkRst/Cal/TapDel/l29" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l30" RLOC=X1Y1;
INST "RAMIf/CkRst/Cal/TapDel/l30" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/l31" RLOC=X1Y1;
INST "RAMIf/CkRst/Cal/TapDel/l31" U_SET = delay_calibration_chain;

#################################################################################################################
# Placement constraints for first stage flops in tap delay ckt
#################################################################################################################
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[0].r" RLOC=X0Y6;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[0].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[1].r" RLOC=X0Y6;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[1].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[2].r" RLOC=X0Y7;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[2].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[3].r" RLOC=X0Y7;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[3].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[4].r" RLOC=X1Y6;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[4].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[5].r" RLOC=X1Y6;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[5].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[6].r" RLOC=X1Y7;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[6].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[7].r" RLOC=X1Y7;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[7].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[8].r" RLOC=X0Y4;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[8].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[9].r" RLOC=X0Y4;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[9].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[10].r" RLOC=X0Y5;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[10].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[11].r" RLOC=X0Y5;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[11].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[12].r" RLOC=X1Y4;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[12].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[13].r" RLOC=X1Y4;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[13].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[14].r" RLOC=X1Y5;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[14].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[15].r" RLOC=X1Y5;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[15].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[16].r" RLOC=X0Y2;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[16].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[17].r" RLOC=X0Y2;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[17].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[18].r" RLOC=X0Y3;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[18].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[19].r" RLOC=X0Y3;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[19].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[20].r" RLOC=X1Y2;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[20].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[21].r" RLOC=X1Y2;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[21].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[22].r" RLOC=X1Y3;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[22].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[23].r" RLOC=X1Y3;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[23].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[24].r" RLOC=X0Y0;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[24].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[25].r" RLOC=X0Y0;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[25].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[26].r" RLOC=X0Y1;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[26].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[27].r" RLOC=X0Y1;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[27].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[28].r" RLOC=X1Y0;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[28].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[29].r" RLOC=X1Y0;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[29].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[30].r" RLOC=X1Y1;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[30].r" U_SET = delay_calibration_chain;

INST "RAMIf/CkRst/Cal/TapDel/GenTap1[31].r" RLOC=X1Y1;
INST "RAMIf/CkRst/Cal/TapDel/GenTap1[31].r" U_SET = delay_calibration_chain;

#####################################################################################################################
## BEL constraints for LUTS in tap delay ckt
#####################################################################################################################
INST "RAMIf/CkRst/Cal/TapDel/l0"  BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l1"  BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l2"  BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l3"  BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l4"  BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l5"  BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l6"  BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l7"  BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l8"  BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l9"  BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l10" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l11" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l12" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l13" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l14" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l15" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l16" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l17" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l18" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l19" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l20" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l21" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l22" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l23" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l24" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l25" BEL= F;  
INST "RAMIf/CkRst/Cal/TapDel/l26" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l27" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l28" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l29" BEL= F;
INST "RAMIf/CkRst/Cal/TapDel/l30" BEL= G;
INST "RAMIf/CkRst/Cal/TapDel/l31" BEL= F;

##############################################################################################################
## MAXDELAY constraints
##############################################################################################################

##############################################################################################################
## Constraint to have the tap delay inverter connection wire length to be the same and minimum to get
## accurate calibration of tap delays. The following constraints are independent of frequency. This delay 
## varies from device to device. The reported delay will be in the range of 300 to 600 ps
##############################################################################################################
NET "RAMIf/CkRst/Cal/TapDel/tap[7]"  MAXDELAY = 600ps;
NET "RAMIf/CkRst/Cal/TapDel/tap[15]" MAXDELAY = 600ps;
NET "RAMIf/CkRst/Cal/TapDel/tap[23]" MAXDELAY = 600ps;

##############################################################################################################
## Constraint from the dqs PAD to input of LUT delay element. The reported delay will be in the range of 
## 400 to 860 ps.
##############################################################################################################
#NET "RAMIf/DQSIn*" MAXDELAY = 860ps;

##############################################################################################################
## Constraint from rst_dqs_div_in PAD to input of LUT delay element. The reported delay will be in the range 
## of 400 to 860ps.
##############################################################################################################
NET "RAMIf/RstDqsDivIn" MAXDELAY = 860ps;


##############################################################################################################
## RLOC Origin constraint for LUT delay calibration chain.
##############################################################################################################
INST "RAMIf/CkRst/Cal/TapDel/l0" RLOC_ORIGIN = X58Y142;

##############################################################################################################
## Area Group Constraint For tap_dly and cal_ctl module.
##############################################################################################################
INST "RAMIf/CkRst/Cal/*" AREA_GROUP = cal_ctl;
AREA_GROUP "cal_ctl" RANGE = SLICE_X58Y142:SLICE_X69Y155;
AREA_GROUP "cal_ctl" GROUP = CLOSED;
##############################################################################################################

##############################################################################################################
## MAXDELAY constraints
##############################################################################################################

##############################################################################################################
## MAXDELAY constraint on inter LUT delay elements. This constraint is required to minimize the 
## wire delays between the LUTs. The reported delay will be in the range of 315 ps tp 415 ps.
##############################################################################################################
#NET "RAMIf/DataPath/GenDelay[*].DqsDelayCol*/Delay*"  MAXDELAY = 420ps;
#NET "RAMIf/DataPath/DqsDelayedCol*" MAXDELAY = 1800 ps;

##############################################################################################################
## Following are the MAXDELAY constraints on delayed rst_dqs_div net and fifo write enable signals.
## These constraints are required since these paths are not covered by timing analysis. The requirement is total
## delay on delayed rst_dqs_div and fifo_wr_en nets should not exceed the clock period.
##############################################################################################################
#NET "RAMIf/DataPath/RstDqsDiv"  MAXDELAY = 3030 ps;
#NET "RAMIf/DataPath/Fifo*WrEn*" MAXDELAY = 3030 ps;

##############################################################################################################
## The MAXDELAY value on fifo write address should be less than clock period. This constraint is 
## required since this path is not covered by timing analysis.
##############################################################################################################
#NET "RAMIf/DataPath/Fifo*WrAddr<*>" MAXDELAY = 4545 ps;

##############################################################################################################

NET "SR_Dq<0>"	LOC = "A26" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[0].GenCol0.FifoBit0" LOC = SLICE_X122Y158;
INST "RAMIf/DataPath/GenFifo[0].GenCol0.FifoBit1" LOC = SLICE_X122Y159;
NET "SR_Dq<1>"	LOC = "B26" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[1].GenCol1.FifoBit0" LOC = SLICE_X122Y156;
INST "RAMIf/DataPath/GenFifo[1].GenCol1.FifoBit1" LOC = SLICE_X122Y157;
NET "SR_Dq<2>"	LOC = "A24" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[2].GenCol0.FifoBit0" LOC = SLICE_X114Y158;
INST "RAMIf/DataPath/GenFifo[2].GenCol0.FifoBit1" LOC = SLICE_X114Y159;
NET "SR_Dq<3>"	LOC = "B24" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[3].GenCol1.FifoBit0" LOC = SLICE_X114Y156;
INST "RAMIf/DataPath/GenFifo[3].GenCol1.FifoBit1" LOC = SLICE_X114Y157;
NET "SR_Dq<4>"	LOC = "C27" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[4].GenCol0.FifoBit0" LOC = SLICE_X124Y158;
INST "RAMIf/DataPath/GenFifo[4].GenCol0.FifoBit1" LOC = SLICE_X124Y159;
NET "SR_Dq<5>"	LOC = "D26" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[5].GenCol1.FifoBit0" LOC = SLICE_X124Y156;
INST "RAMIf/DataPath/GenFifo[5].GenCol1.FifoBit1" LOC = SLICE_X124Y157;
NET "SR_Dq<6>"	LOC = "C25" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[6].GenCol0.FifoBit0" LOC = SLICE_X120Y158;
INST "RAMIf/DataPath/GenFifo[6].GenCol0.FifoBit1" LOC = SLICE_X120Y159;
NET "SR_Dq<7>"	LOC = "B25" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[7].GenCol1.FifoBit0" LOC = SLICE_X120Y156;
INST "RAMIf/DataPath/GenFifo[7].GenCol1.FifoBit1" LOC = SLICE_X120Y157;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[0].Fifo0WrAddrInst/bit0" LOC = SLICE_X123Y158;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo0WrAddrInst/bit1" LOC = SLICE_X123Y158;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo0WrAddrInst/bit2" LOC = SLICE_X123Y159;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo0WrAddrInst/bit3" LOC = SLICE_X123Y159;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo1WrAddrInst/bit0" LOC = SLICE_X123Y156;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo1WrAddrInst/bit1" LOC = SLICE_X123Y156;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo1WrAddrInst/bit2" LOC = SLICE_X123Y157;
INST "RAMIf/DataPath/GenWrAddr[0].Fifo1WrAddrInst/bit3" LOC = SLICE_X123Y157;
#INST "RAMIf/DataPath/GenWrEn[0].Fifo0WrEnInst/*" LOC = SLICE_X121Y158;
#INST "RAMIf/DataPath/GenWrEn[0].Fifo1WrEnInst/*" LOC = SLICE_X121Y156;

NET "SR_Dq<8>"	LOC = "F23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[8].GenCol0.FifoBit0" LOC = SLICE_X110Y158;
INST "RAMIf/DataPath/GenFifo[8].GenCol0.FifoBit1" LOC = SLICE_X110Y159;
NET "SR_Dq<9>"	LOC = "G23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[9].GenCol1.FifoBit0" LOC = SLICE_X110Y156;
INST "RAMIf/DataPath/GenFifo[9].GenCol1.FifoBit1" LOC = SLICE_X110Y157;
NET "SR_Dq<10>"	LOC = "D22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[10].GenCol0.FifoBit0" LOC = SLICE_X100Y158;
INST "RAMIf/DataPath/GenFifo[10].GenCol0.FifoBit1" LOC = SLICE_X100Y159;
NET "SR_Dq<11>"	LOC = "E22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[11].GenCol1.FifoBit0" LOC = SLICE_X100Y156;
INST "RAMIf/DataPath/GenFifo[11].GenCol1.FifoBit1" LOC = SLICE_X100Y157;
NET "SR_Dq<12>"	LOC = "G24" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[12].GenCol0.FifoBit0" LOC = SLICE_X112Y158;
INST "RAMIf/DataPath/GenFifo[12].GenCol0.FifoBit1" LOC = SLICE_X112Y159;
NET "SR_Dq<13>"	LOC = "H23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[13].GenCol1.FifoBit0" LOC = SLICE_X112Y156;
INST "RAMIf/DataPath/GenFifo[13].GenCol1.FifoBit1" LOC = SLICE_X112Y157;
NET "SR_Dq<14>"	LOC = "E23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[14].GenCol0.FifoBit0" LOC = SLICE_X102Y158;
INST "RAMIf/DataPath/GenFifo[14].GenCol0.FifoBit1" LOC = SLICE_X102Y159;
NET "SR_Dq<15>"	LOC = "F22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[15].GenCol1.FifoBit0" LOC = SLICE_X102Y156;
INST "RAMIf/DataPath/GenFifo[15].GenCol1.FifoBit1" LOC = SLICE_X102Y157;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[1].Fifo0WrAddrInst/bit0" LOC = SLICE_X111Y158;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo0WrAddrInst/bit1" LOC = SLICE_X111Y158;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo0WrAddrInst/bit2" LOC = SLICE_X111Y159;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo0WrAddrInst/bit3" LOC = SLICE_X111Y159;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo1WrAddrInst/bit0" LOC = SLICE_X111Y156;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo1WrAddrInst/bit1" LOC = SLICE_X111Y156;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo1WrAddrInst/bit2" LOC = SLICE_X111Y157;
INST "RAMIf/DataPath/GenWrAddr[1].Fifo1WrAddrInst/bit3" LOC = SLICE_X111Y157;
#INST "RAMIf/DataPath/GenWrEn[1].Fifo0WrEnInst/*" LOC = SLICE_X107Y158;
#INST "RAMIf/DataPath/GenWrEn[1].Fifo1WrEnInst/*" LOC = SLICE_X107Y156;

NET "SR_Dq<16>"	LOC = "F21" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[16].GenCol0.FifoBit0" LOC = SLICE_X96Y158;
INST "RAMIf/DataPath/GenFifo[16].GenCol0.FifoBit1" LOC = SLICE_X96Y159;
NET "SR_Dq<17>"	LOC = "G21" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[17].GenCol1.FifoBit0" LOC = SLICE_X96Y156;
INST "RAMIf/DataPath/GenFifo[17].GenCol1.FifoBit1" LOC = SLICE_X96Y157;
NET "SR_Dq<18>"	LOC = "C20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[18].GenCol0.FifoBit0" LOC = SLICE_X88Y158;
INST "RAMIf/DataPath/GenFifo[18].GenCol0.FifoBit1" LOC = SLICE_X88Y159;
NET "SR_Dq<19>"	LOC = "D20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[19].GenCol1.FifoBit0" LOC = SLICE_X88Y156;
INST "RAMIf/DataPath/GenFifo[19].GenCol1.FifoBit1" LOC = SLICE_X88Y157;
NET "SR_Dq<20>"	LOC = "B22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[20].GenCol0.FifoBit0" LOC = SLICE_X98Y158;
INST "RAMIf/DataPath/GenFifo[20].GenCol0.FifoBit1" LOC = SLICE_X98Y159;
NET "SR_Dq<21>"	LOC = "A22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[21].GenCol1.FifoBit0" LOC = SLICE_X98Y156;
INST "RAMIf/DataPath/GenFifo[21].GenCol1.FifoBit1" LOC = SLICE_X98Y157;
NET "SR_Dq<22>"	LOC = "F20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[22].GenCol0.FifoBit0" LOC = SLICE_X90Y158;
INST "RAMIf/DataPath/GenFifo[22].GenCol0.FifoBit1" LOC = SLICE_X90Y159;
NET "SR_Dq<23>"	LOC = "E20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[23].GenCol1.FifoBit0" LOC = SLICE_X90Y156;
INST "RAMIf/DataPath/GenFifo[23].GenCol1.FifoBit1" LOC = SLICE_X90Y157;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[2].Fifo0WrAddrInst/bit0" LOC = SLICE_X99Y158;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo0WrAddrInst/bit1" LOC = SLICE_X99Y158;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo0WrAddrInst/bit2" LOC = SLICE_X99Y159;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo0WrAddrInst/bit3" LOC = SLICE_X99Y159;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo1WrAddrInst/bit0" LOC = SLICE_X99Y156;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo1WrAddrInst/bit1" LOC = SLICE_X99Y156;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo1WrAddrInst/bit2" LOC = SLICE_X99Y157;
INST "RAMIf/DataPath/GenWrAddr[2].Fifo1WrAddrInst/bit3" LOC = SLICE_X99Y157;
#INST "RAMIf/DataPath/GenWrEn[2].Fifo0WrEnInst/*" LOC = SLICE_X97Y158;
#INST "RAMIf/DataPath/GenWrEn[2].Fifo1WrEnInst/*" LOC = SLICE_X97Y156;

NET "SR_Dq<24>"	LOC = "J19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[24].GenCol0.FifoBit0" LOC = SLICE_X84Y158;
INST "RAMIf/DataPath/GenFifo[24].GenCol0.FifoBit1" LOC = SLICE_X84Y159;
NET "SR_Dq<25>"	LOC = "K19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[25].GenCol1.FifoBit0" LOC = SLICE_X84Y156;
INST "RAMIf/DataPath/GenFifo[25].GenCol1.FifoBit1" LOC = SLICE_X84Y157;
NET "SR_Dq<26>"	LOC = "C19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[26].GenCol0.FifoBit0" LOC = SLICE_X78Y158;
INST "RAMIf/DataPath/GenFifo[26].GenCol0.FifoBit1" LOC = SLICE_X78Y159;
NET "SR_Dq<27>"	LOC = "D19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[27].GenCol1.FifoBit0" LOC = SLICE_X78Y156;
INST "RAMIf/DataPath/GenFifo[27].GenCol1.FifoBit1" LOC = SLICE_X78Y157;
NET "SR_Dq<28>"	LOC = "A20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[28].GenCol0.FifoBit0" LOC = SLICE_X86Y158;
INST "RAMIf/DataPath/GenFifo[28].GenCol0.FifoBit1" LOC = SLICE_X86Y159;
NET "SR_Dq<29>"	LOC = "B20" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[29].GenCol1.FifoBit0" LOC = SLICE_X86Y156;
INST "RAMIf/DataPath/GenFifo[29].GenCol1.FifoBit1" LOC = SLICE_X86Y157;
NET "SR_Dq<30>"	LOC = "E19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[30].GenCol0.FifoBit0" LOC = SLICE_X80Y158;
INST "RAMIf/DataPath/GenFifo[30].GenCol0.FifoBit1" LOC = SLICE_X80Y159;
NET "SR_Dq<31>"	LOC = "F19" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[31].GenCol1.FifoBit0" LOC = SLICE_X80Y156;
INST "RAMIf/DataPath/GenFifo[31].GenCol1.FifoBit1" LOC = SLICE_X80Y157;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[3].Fifo0WrAddrInst/bit0" LOC = SLICE_X87Y158;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo0WrAddrInst/bit1" LOC = SLICE_X87Y158;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo0WrAddrInst/bit2" LOC = SLICE_X87Y159;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo0WrAddrInst/bit3" LOC = SLICE_X87Y159;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo1WrAddrInst/bit0" LOC = SLICE_X87Y156;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo1WrAddrInst/bit1" LOC = SLICE_X87Y156;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo1WrAddrInst/bit2" LOC = SLICE_X87Y157;
INST "RAMIf/DataPath/GenWrAddr[3].Fifo1WrAddrInst/bit3" LOC = SLICE_X87Y157;
#INST "RAMIf/DataPath/GenWrEn[3].Fifo0WrEnInst/*" LOC = SLICE_X85Y158;
#INST "RAMIf/DataPath/GenWrEn[3].Fifo1WrEnInst/*" LOC = SLICE_X85Y156;

NET "SR_Dq<32>"	LOC = "N23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[32].GenCol0.FifoBit0" LOC = SLICE_X126Y106;
INST "RAMIf/DataPath/GenFifo[32].GenCol0.FifoBit1" LOC = SLICE_X126Y107;
NET "SR_Dq<33>"	LOC = "N22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[33].GenCol1.FifoBit0" LOC = SLICE_X124Y106;
INST "RAMIf/DataPath/GenFifo[33].GenCol1.FifoBit1" LOC = SLICE_X124Y107;
NET "SR_Dq<34>"	LOC = "M23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[34].GenCol0.FifoBit0" LOC = SLICE_X126Y116;
INST "RAMIf/DataPath/GenFifo[34].GenCol0.FifoBit1" LOC = SLICE_X126Y117;
NET "SR_Dq<35>"	LOC = "M22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[35].GenCol1.FifoBit0" LOC = SLICE_X124Y116;
INST "RAMIf/DataPath/GenFifo[35].GenCol1.FifoBit1" LOC = SLICE_X124Y117;
NET "SR_Dq<36>"	LOC = "M26" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[36].GenCol0.FifoBit0" LOC = SLICE_X126Y104;
INST "RAMIf/DataPath/GenFifo[36].GenCol0.FifoBit1" LOC = SLICE_X126Y105;
NET "SR_Dq<37>"	LOC = "N25" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[37].GenCol1.FifoBit0" LOC = SLICE_X124Y104;
INST "RAMIf/DataPath/GenFifo[37].GenCol1.FifoBit1" LOC = SLICE_X124Y105;
NET "SR_Dq<38>"	LOC = "M27" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[38].GenCol0.FifoBit0" LOC = SLICE_X126Y126;
INST "RAMIf/DataPath/GenFifo[38].GenCol0.FifoBit1" LOC = SLICE_X126Y127;
NET "SR_Dq<39>"	LOC = "M28" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[39].GenCol1.FifoBit0" LOC = SLICE_X124Y126;
INST "RAMIf/DataPath/GenFifo[39].GenCol1.FifoBit1" LOC = SLICE_X124Y127;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[4].Fifo0WrAddrInst/bit0" LOC = SLICE_X127Y126;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo0WrAddrInst/bit1" LOC = SLICE_X127Y126;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo0WrAddrInst/bit2" LOC = SLICE_X127Y127;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo0WrAddrInst/bit3" LOC = SLICE_X127Y127;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo1WrAddrInst/bit0" LOC = SLICE_X125Y126;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo1WrAddrInst/bit1" LOC = SLICE_X125Y127;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo1WrAddrInst/bit2" LOC = SLICE_X125Y126;
INST "RAMIf/DataPath/GenWrAddr[4].Fifo1WrAddrInst/bit3" LOC = SLICE_X125Y127;
#INST "RAMIf/DataPath/GenWrEn[4].Fifo0WrEnInst/*" LOC = SLICE_X127Y128;
#INST "RAMIf/DataPath/GenWrEn[4].Fifo1WrEnInst/*" LOC = SLICE_X125Y128;

NET "SR_Dq<40>"	LOC = "L28" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[40].GenCol0.FifoBit0" LOC = SLICE_X126Y120;
INST "RAMIf/DataPath/GenFifo[40].GenCol0.FifoBit1" LOC = SLICE_X126Y121;
NET "SR_Dq<41>"	LOC = "L27" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[41].GenCol1.FifoBit0" LOC = SLICE_X124Y120;
INST "RAMIf/DataPath/GenFifo[41].GenCol1.FifoBit1" LOC = SLICE_X124Y121;
NET "SR_Dq<42>"	LOC = "K22" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[42].GenCol0.FifoBit0" LOC = SLICE_X126Y130;
INST "RAMIf/DataPath/GenFifo[42].GenCol0.FifoBit1" LOC = SLICE_X126Y131;
NET "SR_Dq<43>"	LOC = "J23" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[43].GenCol1.FifoBit0" LOC = SLICE_X124Y130;
INST "RAMIf/DataPath/GenFifo[43].GenCol1.FifoBit1" LOC = SLICE_X124Y131;
NET "SR_Dq<44>"	LOC = "L29" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[44].GenCol0.FifoBit0" LOC = SLICE_X126Y118;
INST "RAMIf/DataPath/GenFifo[44].GenCol0.FifoBit1" LOC = SLICE_X126Y119;
NET "SR_Dq<45>"	LOC = "L30" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[45].GenCol1.FifoBit0" LOC = SLICE_X124Y118;
INST "RAMIf/DataPath/GenFifo[45].GenCol1.FifoBit1" LOC = SLICE_X124Y119;
NET "SR_Dq<46>"	LOC = "K25" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[46].GenCol0.FifoBit0" LOC = SLICE_X126Y128;
INST "RAMIf/DataPath/GenFifo[46].GenCol0.FifoBit1" LOC = SLICE_X126Y129;
NET "SR_Dq<47>"	LOC = "K24" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[47].GenCol1.FifoBit0" LOC = SLICE_X124Y128;
INST "RAMIf/DataPath/GenFifo[47].GenCol1.FifoBit1" LOC = SLICE_X124Y129;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[5].Fifo0WrAddrInst/bit0" LOC = SLICE_X127Y130;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo0WrAddrInst/bit1" LOC = SLICE_X127Y130;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo0WrAddrInst/bit2" LOC = SLICE_X127Y131;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo0WrAddrInst/bit3" LOC = SLICE_X127Y131;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo1WrAddrInst/bit0" LOC = SLICE_X125Y130;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo1WrAddrInst/bit1" LOC = SLICE_X125Y131;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo1WrAddrInst/bit2" LOC = SLICE_X125Y130;
INST "RAMIf/DataPath/GenWrAddr[5].Fifo1WrAddrInst/bit3" LOC = SLICE_X125Y131;
#INST "RAMIf/DataPath/GenWrEn[5].Fifo0WrEnInst/*" LOC = SLICE_X127Y132;
#INST "RAMIf/DataPath/GenWrEn[5].Fifo1WrEnInst/*" LOC = SLICE_X125Y132;

NET "SR_Dq<48>"	LOC = "H30" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[48].GenCol0.FifoBit0" LOC = SLICE_X126Y136;
INST "RAMIf/DataPath/GenFifo[48].GenCol0.FifoBit1" LOC = SLICE_X126Y137;
NET "SR_Dq<49>"	LOC = "H29" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[49].GenCol1.FifoBit0" LOC = SLICE_X124Y136;
INST "RAMIf/DataPath/GenFifo[49].GenCol1.FifoBit1" LOC = SLICE_X124Y137;
NET "SR_Dq<50>"	LOC = "G27" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[50].GenCol0.FifoBit0" LOC = SLICE_X126Y148;
INST "RAMIf/DataPath/GenFifo[50].GenCol0.FifoBit1" LOC = SLICE_X126Y149;
NET "SR_Dq<51>"	LOC = "G28" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[51].GenCol1.FifoBit0" LOC = SLICE_X124Y148;
INST "RAMIf/DataPath/GenFifo[51].GenCol1.FifoBit1" LOC = SLICE_X124Y149;
NET "SR_Dq<52>"	LOC = "J30" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[52].GenCol0.FifoBit0" LOC = SLICE_X126Y132;
INST "RAMIf/DataPath/GenFifo[52].GenCol0.FifoBit1" LOC = SLICE_X126Y133;
NET "SR_Dq<53>"	LOC = "J29" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[53].GenCol1.FifoBit0" LOC = SLICE_X124Y132;
INST "RAMIf/DataPath/GenFifo[53].GenCol1.FifoBit1" LOC = SLICE_X124Y133;
NET "SR_Dq<54>"	LOC = "G29" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[54].GenCol0.FifoBit0" LOC = SLICE_X126Y146;
INST "RAMIf/DataPath/GenFifo[54].GenCol0.FifoBit1" LOC = SLICE_X126Y147;
NET "SR_Dq<55>"	LOC = "G30" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[55].GenCol1.FifoBit0" LOC = SLICE_X124Y146;
INST "RAMIf/DataPath/GenFifo[55].GenCol1.FifoBit1" LOC = SLICE_X124Y147;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[6].Fifo0WrAddrInst/bit0" LOC = SLICE_X127Y148;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo0WrAddrInst/bit1" LOC = SLICE_X127Y148;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo0WrAddrInst/bit2" LOC = SLICE_X127Y149;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo0WrAddrInst/bit3" LOC = SLICE_X127Y149;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo1WrAddrInst/bit0" LOC = SLICE_X125Y148;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo1WrAddrInst/bit1" LOC = SLICE_X125Y149;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo1WrAddrInst/bit2" LOC = SLICE_X125Y148;
INST "RAMIf/DataPath/GenWrAddr[6].Fifo1WrAddrInst/bit3" LOC = SLICE_X125Y149;
#INST "RAMIf/DataPath/GenWrEn[6].Fifo0WrEnInst/*" LOC = SLICE_X127Y146;
#INST "RAMIf/DataPath/GenWrEn[6].Fifo1WrEnInst/*" LOC = SLICE_X125Y146;

NET "SR_Dq<56>"	LOC = "G17" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[56].GenCol0.FifoBit0" LOC = SLICE_X74Y158;
INST "RAMIf/DataPath/GenFifo[56].GenCol0.FifoBit1" LOC = SLICE_X74Y159;
NET "SR_Dq<57>"	LOC = "F17" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[57].GenCol1.FifoBit0" LOC = SLICE_X74Y156;
INST "RAMIf/DataPath/GenFifo[57].GenCol1.FifoBit1" LOC = SLICE_X74Y157;
NET "SR_Dq<58>"	LOC = "C17" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[58].GenCol0.FifoBit0" LOC = SLICE_X72Y158;
INST "RAMIf/DataPath/GenFifo[58].GenCol0.FifoBit1" LOC = SLICE_X72Y159;
NET "SR_Dq<59>"	LOC = "B17" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[59].GenCol1.FifoBit0" LOC = SLICE_X72Y156;
INST "RAMIf/DataPath/GenFifo[59].GenCol1.FifoBit1" LOC = SLICE_X72Y157;
NET "SR_Dq<60>"	LOC = "k16" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[60].GenCol0.FifoBit0" LOC = SLICE_X70Y158;
INST "RAMIf/DataPath/GenFifo[60].GenCol0.FifoBit1" LOC = SLICE_X70Y159;
NET "SR_Dq<61>"	LOC = "J16" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[61].GenCol1.FifoBit0" LOC = SLICE_X70Y156;
INST "RAMIf/DataPath/GenFifo[61].GenCol1.FifoBit1" LOC = SLICE_X70Y157;
NET "SR_Dq<62>"	LOC = "B16" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[62].GenCol0.FifoBit0" LOC = SLICE_X64Y158;
INST "RAMIf/DataPath/GenFifo[62].GenCol0.FifoBit1" LOC = SLICE_X64Y159;
NET "SR_Dq<63>"	LOC = "C16" | IOSTANDARD = SSTL18_II;
INST "RAMIf/DataPath/GenFifo[63].GenCol1.FifoBit0" LOC = SLICE_X64Y156;
INST "RAMIf/DataPath/GenFifo[63].GenCol1.FifoBit1" LOC = SLICE_X64Y157;
# Write address and enable
INST "RAMIf/DataPath/GenWrAddr[7].Fifo0WrAddrInst/bit0" LOC = SLICE_X75Y158;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo0WrAddrInst/bit1" LOC = SLICE_X75Y158;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo0WrAddrInst/bit2" LOC = SLICE_X75Y159;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo0WrAddrInst/bit3" LOC = SLICE_X75Y159;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo1WrAddrInst/bit0" LOC = SLICE_X75Y156;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo1WrAddrInst/bit1" LOC = SLICE_X75Y156;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo1WrAddrInst/bit2" LOC = SLICE_X75Y157;
INST "RAMIf/DataPath/GenWrAddr[7].Fifo1WrAddrInst/bit3" LOC = SLICE_X75Y157;
#INST "RAMIf/DataPath/GenWrEn[7].Fifo0WrEnInst/*" LOC = SLICE_X73Y158;
#INST "RAMIf/DataPath/GenWrEn[7].Fifo1WrEnInst/*" LOC = SLICE_X73Y156;


NET "SR_Dqs<0>"		LOC = "F25" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<0>"	LOC = "F24" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/One" LOC = SLICE_X118Y157;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Two" LOC = SLICE_X118Y157;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Three" LOC = SLICE_X118Y156;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Four" LOC = SLICE_X118Y156;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Five" LOC = SLICE_X119Y157;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Six" LOC = SLICE_X119Y156;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/One" LOC = SLICE_X118Y158;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/One" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Two" LOC = SLICE_X118Y159;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Two" BEL = F;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Three" LOC = SLICE_X118Y159;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Four" LOC = SLICE_X119Y158;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Five" LOC = SLICE_X119Y158;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Six" LOC = SLICE_X119Y159;
#INST "RAMIf/DataPath/GenDelay[0].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<1>"		LOC = "J22" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<1>"	LOC = "H22" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/One" LOC = SLICE_X104Y157;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Two" LOC = SLICE_X104Y157;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Three" LOC = SLICE_X104Y156;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Four" LOC = SLICE_X104Y156;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Five" LOC = SLICE_X105Y157;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Six" LOC = SLICE_X105Y156;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/One" LOC = SLICE_X104Y158;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/One" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Two" LOC = SLICE_X104Y159;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Two" BEL = F;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Three" LOC = SLICE_X104Y159;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Four" LOC = SLICE_X104Y158;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Five" LOC = SLICE_X105Y158;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Six" LOC = SLICE_X105Y159;
#INST "RAMIf/DataPath/GenDelay[1].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<2>"		LOC = "H20" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<2>"	LOC = "G20" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/One" LOC = SLICE_X92Y157;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Two" LOC = SLICE_X92Y157;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Three" LOC = SLICE_X92Y156;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Four" LOC = SLICE_X92Y156;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Five" LOC = SLICE_X93Y157;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Six" LOC = SLICE_X93Y156;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/One" LOC = SLICE_X92Y158;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/One" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Two" LOC = SLICE_X92Y159;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Two" BEL = F;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Three" LOC = SLICE_X92Y159;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Four" LOC = SLICE_X92Y158;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Five" LOC = SLICE_X93Y158;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Six" LOC = SLICE_X93Y159;
#INST "RAMIf/DataPath/GenDelay[2].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<3>"		LOC = "H19" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<3>"	LOC = "G19" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/One" LOC = SLICE_X82Y157;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Two" LOC = SLICE_X82Y157;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Three" LOC = SLICE_X82Y156;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Four" LOC = SLICE_X82Y156;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Five" LOC = SLICE_X83Y157;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Six" LOC = SLICE_X83Y156;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/One" LOC = SLICE_X82Y158;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/One" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Two" LOC = SLICE_X82Y159;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Two" BEL = F;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Three" LOC = SLICE_X82Y159;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Four" LOC = SLICE_X82Y158;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Five" LOC = SLICE_X83Y158;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Six" LOC = SLICE_X83Y159;
#INST "RAMIf/DataPath/GenDelay[3].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<4>"		LOC = "N21" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<4>"	LOC = "M21" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/One" LOC = SLICE_X124Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Two" LOC = SLICE_X124Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Three" LOC = SLICE_X124Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Four" LOC = SLICE_X124Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Five" LOC = SLICE_X125Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Six" LOC = SLICE_X125Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/One" LOC = SLICE_X126Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Two" LOC = SLICE_X126Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Three" LOC = SLICE_X126Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Four" LOC = SLICE_X126Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Five" LOC = SLICE_X127Y109;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Six" LOC = SLICE_X127Y108;
#INST "RAMIf/DataPath/GenDelay[4].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<5>"		LOC = "L26" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<5>"	LOC = "L25" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/One" LOC = SLICE_X124Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Two" LOC = SLICE_X124Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Three" LOC = SLICE_X124Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Four" LOC = SLICE_X124Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Five" LOC = SLICE_X125Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Six" LOC = SLICE_X125Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/One" LOC = SLICE_X126Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Two" LOC = SLICE_X126Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Three" LOC = SLICE_X126Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Four" LOC = SLICE_X126Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Five" LOC = SLICE_X127Y123;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Six" LOC = SLICE_X127Y122;
#INST "RAMIf/DataPath/GenDelay[5].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<6>"		LOC = "H24" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<6>"	LOC = "G25" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/One" LOC = SLICE_X124Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Two" LOC = SLICE_X124Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Three" LOC = SLICE_X124Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Four" LOC = SLICE_X124Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Five" LOC = SLICE_X125Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Six" LOC = SLICE_X125Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/One" LOC = SLICE_X126Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Two" LOC = SLICE_X126Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Three" LOC = SLICE_X126Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Four" LOC = SLICE_X126Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Five" LOC = SLICE_X127Y145;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Six" LOC = SLICE_X127Y144;
#INST "RAMIf/DataPath/GenDelay[6].DqsDelayCol1/Six" BEL = G;

NET "SR_Dqs<7>"		LOC = "H16" | IOSTANDARD = SSTL18_II;
NET "nSR_Dqs<7>"	LOC = "G16" | IOSTANDARD = SSTL18_II;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/One" LOC = SLICE_X68Y157;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/One" BEL = F;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Two" LOC = SLICE_X68Y157;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Two" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Three" LOC = SLICE_X68Y156;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Four" LOC = SLICE_X68Y156;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Five" LOC = SLICE_X69Y157;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Six" LOC = SLICE_X69Y156;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol0/Six" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/One" LOC = SLICE_X68Y158;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/One" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Two" LOC = SLICE_X68Y159;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Two" BEL = F;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Three" LOC = SLICE_X68Y159;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Three" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Four" LOC = SLICE_X68Y158;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Four" BEL = F;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Five" LOC = SLICE_X69Y158;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Five" BEL = G;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Six" LOC = SLICE_X69Y159;
#INST "RAMIf/DataPath/GenDelay[7].DqsDelayCol1/Six" BEL = G;

NET "SR_DqsDiv"	LOC = "D23" | IOSTANDARD = SSTL18_II | IOBDELAY = IBUF;
#INST "RAMIf/DataPath/RstDqsDelay/One" LOC = SLICE_X108Y159;
#INST "RAMIf/DataPath/RstDqsDelay/One" BEL = F;
#INST "RAMIf/DataPath/RstDqsDelay/Two" LOC = SLICE_X108Y158;
#INST "RAMIf/DataPath/RstDqsDelay/Two" BEL = F;
#INST "RAMIf/DataPath/RstDqsDelay/Three" LOC = SLICE_X108Y159;
#INST "RAMIf/DataPath/RstDqsDelay/Three" BEL = G;
#INST "RAMIf/DataPath/RstDqsDelay/Four" LOC = SLICE_X109Y158;
#INST "RAMIf/DataPath/RstDqsDelay/Four" BEL = F;
#INST "RAMIf/DataPath/RstDqsDelay/Five" LOC = SLICE_X109Y158;
#INST "RAMIf/DataPath/RstDqsDelay/Five" BEL = G;
#INST "RAMIf/DataPath/RstDqsDelay/Six" LOC = SLICE_X109Y159;
#INST "RAMIf/DataPath/RstDqsDelay/Six" BEL = G;

#INST "RAMIf/Io/RstIob_REG" LOC = SLICE_X108Y156;

NET "SR_DM<0>"	LOC = "E25" | IOSTANDARD = SSTL18_II;
NET "SR_DM<1>"	LOC = "D24" | IOSTANDARD = SSTL18_II;
NET "SR_DM<2>"	LOC = "J21" | IOSTANDARD = SSTL18_II;
NET "SR_DM<3>"	LOC = "C21" | IOSTANDARD = SSTL18_II;
NET "SR_DM<4>"	LOC = "M25" | IOSTANDARD = SSTL18_II;
NET "SR_DM<5>"	LOC = "J26" | IOSTANDARD = SSTL18_II;
NET "SR_DM<6>"	LOC = "H26" | IOSTANDARD = SSTL18_II;
NET "SR_DM<7>"	LOC = "F16" | IOSTANDARD = SSTL18_II;

NET "SR_A<0>"	LOC = "R28" | IOSTANDARD = SSTL18_II;
NET "SR_A<1>"	LOC = "R25" | IOSTANDARD = SSTL18_II;
NET "SR_A<2>"	LOC = "R27" | IOSTANDARD = SSTL18_II;
NET "SR_A<3>"	LOC = "R24" | IOSTANDARD = SSTL18_II;
NET "SR_A<4>"	LOC = "R26" | IOSTANDARD = SSTL18_II;
NET "SR_A<5>"	LOC = "R23" | IOSTANDARD = SSTL18_II;
NET "SR_A<6>"	LOC = "F29" | IOSTANDARD = SSTL18_II;
NET "SR_A<7>"	LOC = "F28" | IOSTANDARD = SSTL18_II;
NET "SR_A<8>"	LOC = "E30" | IOSTANDARD = SSTL18_II;
NET "SR_A<9>"	LOC = "E29" | IOSTANDARD = SSTL18_II;
NET "SR_A<10>"	LOC = "R22" | IOSTANDARD = SSTL18_II;
NET "SR_A<11>"	LOC = "D28" | IOSTANDARD = SSTL18_II;
NET "SR_A<12>"	LOC = "D27" | IOSTANDARD = SSTL18_II;
NET "SR_A<13>"	LOC = "R21" | IOSTANDARD = SSTL18_II;

NET "SR_Ba<0>"	LOC = "P24" | IOSTANDARD = SSTL18_II;
NET "SR_Ba<1>"	LOC = "P25" | IOSTANDARD = SSTL18_II;
NET "SR_Ba<2>"	LOC = "D30" | IOSTANDARD = SSTL18_II;

NET "nSR_We"	LOC = "P29" | IOSTANDARD = SSTL18_II;
NET "nSR_Ras"	LOC = "P21" | IOSTANDARD = SSTL18_II;
NET "nSR_Cas"	LOC = "P22" | IOSTANDARD = SSTL18_II;
NET "SR_ODT<0>"	LOC = "N26" | IOSTANDARD = SSTL18_II;
NET "SR_ODT<1>"	LOC = "N27" | IOSTANDARD = SSTL18_II;
NET "nSR_S<0>"	LOC = "N30" | IOSTANDARD = SSTL18_II;
NET "nSR_S<1>"	LOC = "N29" | IOSTANDARD = SSTL18_II;

NET "SR_SCL"	LOC = "E15" | IOSTANDARD = LVCMOS33;
NET "SR_SDA"	LOC = "K15" | PULLUP | IOSTANDARD = LVCMOS33;
NET "SR_SA<0>"	LOC = "D13" | IOSTANDARD = LVCMOS33;
NET "SR_SA<1>"	LOC = "K13" | IOSTANDARD = LVCMOS33;

NET "PhyClkToMac" LOC = "AJ16" | IOSTANDARD = LVCMOS33;
NET "nPhyReset"	LOC = "AG27" | IOSTANDARD = LVCMOS33;
NET "PhyRxCrs"	LOC = "AG28" | IOSTANDARD = LVCMOS33;
NET "PhyRxCol"	LOC = "AG29" | IOSTANDARD = LVCMOS33;
NET "PhyRxClk"	LOC = "B15" | IOSTANDARD = LVCMOS33;
NET "PhyRxDv"	LOC = "AG30" | IOSTANDARD = LVCMOS33;
NET "PhyRxEr"	LOC = "AF29" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<0>"	LOC = "AF30" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<1>"	LOC = "AF27" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<2>"	LOC = "AE26" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<3>"	LOC = "AE28" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<4>"	LOC = "AE29" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<5>"	LOC = "AD27" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<6>"	LOC = "AD28" | IOSTANDARD = LVCMOS33;
NET "PhyRxD<7>"	LOC = "AD29" | IOSTANDARD = LVCMOS33;
NET "PhyGTxClk"	LOC = "AD30" | IOSTANDARD = LVCMOS33;
NET "PhyTxClk"	LOC = "A15" | IOSTANDARD = LVCMOS33;
NET "PhyTxEn"	LOC = "AD25" | IOSTANDARD = LVCMOS33;
NET "PhyTxEr"	LOC = "AC24" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<0>"	LOC = "AC25" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<1>"	LOC = "AC26" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<2>"	LOC = "AC27" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<3>"	LOC = "AC28" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<4>"	LOC = "AC29" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<5>"	LOC = "AC30" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<6>"	LOC = "AB25" | IOSTANDARD = LVCMOS33;
NET "PhyTxD<7>"	LOC = "AB26" | IOSTANDARD = LVCMOS33;
NET "PhyMdc"	LOC = "AB27" | IOSTANDARD = LVCMOS33;
NET "PhyMdio"	LOC = "AB29" | IOSTANDARD = LVCMOS33;
NET "nPhyInt"	LOC = "AB30" | IOSTANDARD = LVCMOS33;
NET "PhyMdixEn"	LOC = "AB23" | IOSTANDARD = LVCMOS33;
NET "PhyMultiEn"	LOC = "AA22" | IOSTANDARD = LVCMOS33;
NET "PhyAd<0>"	LOC = "AA21" | IOSTANDARD = LVCMOS33;
NET "PhyAd<1>"	LOC = "AA29" | IOSTANDARD = LVCMOS33;
NET "PhyAd<2>"	LOC = "AA28" | IOSTANDARD = LVCMOS33;
NET "PhyAd<3>"	LOC = "AA25" | IOSTANDARD = LVCMOS33;
NET "PhyAd<4>"	LOC = "AA24" | IOSTANDARD = LVCMOS33;
NET "PhyAnEn"	LOC = "Y21" | IOSTANDARD = LVCMOS33;
NET "PhyDuplex"	LOC = "Y23" | IOSTANDARD = LVCMOS33;
NET "PhySpeed<0>"	LOC = "Y25" | IOSTANDARD = LVCMOS33;
NET "PhySpeed<1>"	LOC = "Y24" | IOSTANDARD = LVCMOS33;

NET "MRamIO<0>"	LOC = "H5" | IOSTANDARD = LVCMOS33;
NET "MRamIO<1>"	LOC = "H6" | IOSTANDARD = LVCMOS33;
NET "MRamIO<2>"	LOC = "H3" | IOSTANDARD = LVCMOS33;
NET "MRamIO<3>"	LOC = "H4" | IOSTANDARD = LVCMOS33;
NET "MRamIO<4>"	LOC = "H1" | IOSTANDARD = LVCMOS33;
NET "MRamIO<5>"	LOC = "H2" | IOSTANDARD = LVCMOS33;
NET "MRamIO<6>"	LOC = "J6" | IOSTANDARD = LVCMOS33;
NET "MRamIO<7>"	LOC = "J4" | IOSTANDARD = LVCMOS33;
NET "MRamIO<8>"	LOC = "J5" | IOSTANDARD = LVCMOS33;
NET "MRamIO<9>"	LOC = "J1" | IOSTANDARD = LVCMOS33;
NET "MRamIO<10>"	LOC = "J2" | IOSTANDARD = LVCMOS33;
NET "MRamIO<11>"	LOC = "J8" | IOSTANDARD = LVCMOS33;
NET "MRamIO<12>"	LOC = "K9" | IOSTANDARD = LVCMOS33;
NET "MRamIO<13>"	LOC = "K6" | IOSTANDARD = LVCMOS33;
NET "MRamIO<14>"	LOC = "K7" | IOSTANDARD = LVCMOS33;
NET "MRamIO<15>"	LOC = "K3" | IOSTANDARD = LVCMOS33;
NET "MRamA<0>"	LOC = "C1" | IOSTANDARD = LVCMOS33;
NET "MRamA<1>"	LOC = "C2" | IOSTANDARD = LVCMOS33;
NET "MRamA<2>"	LOC = "D3" | IOSTANDARD = LVCMOS33;
NET "MRamA<3>"	LOC = "D4" | IOSTANDARD = LVCMOS33;
NET "MRamA<4>"	LOC = "D2" | IOSTANDARD = LVCMOS33;
NET "MRamA<5>"	LOC = "D1" | IOSTANDARD = LVCMOS33;
NET "MRamA<6>"	LOC = "E1" | IOSTANDARD = LVCMOS33;
NET "MRamA<7>"	LOC = "E2" | IOSTANDARD = LVCMOS33;
NET "MRamA<8>"	LOC = "E4" | IOSTANDARD = LVCMOS33;
NET "MRamA<9>"	LOC = "F5" | IOSTANDARD = LVCMOS33;
NET "MRamA<10>"	LOC = "F2" | IOSTANDARD = LVCMOS33;
NET "MRamA<11>"	LOC = "F3" | IOSTANDARD = LVCMOS33;
NET "MRamA<12>"	LOC = "G3" | IOSTANDARD = LVCMOS33;
NET "MRamA<13>"	LOC = "G4" | IOSTANDARD = LVCMOS33;
NET "MRamA<14>"	LOC = "G1" | IOSTANDARD = LVCMOS33;
NET "MRamA<15>"	LOC = "G2" | IOSTANDARD = LVCMOS33;
NET "MRamA<16>"	LOC = "G6" | IOSTANDARD = LVCMOS33;
NET "MRamA<17>"	LOC = "H7" | IOSTANDARD = LVCMOS33;
NET "nMRamCs"	LOC = "K2" | IOSTANDARD = LVCMOS33;
NET "nMRamWe"	LOC = "K10" | IOSTANDARD = LVCMOS33;
NET "nMRamOe"	LOC = "L10" | IOSTANDARD = LVCMOS33;
NET "nMRamBle"	LOC = "L7" | IOSTANDARD = LVCMOS33;
NET "nMRamBhe"	LOC = "L8" | IOSTANDARD = LVCMOS33;

NET "FTrigger"	LOC = "H12" | IOSTANDARD = LVCMOS33;
NET "FSync"	LOC = "G12" | IOSTANDARD = LVCMOS33;
NET "Ident<0>"	LOC = "C12" | IOSTANDARD = LVCMOS33;
NET "Ident<1>"	LOC = "D12" | IOSTANDARD = LVCMOS33;
NET "Ident<2>"	LOC = "E12" | IOSTANDARD = LVCMOS33;
NET "Ident<3>"	LOC = "F12" | IOSTANDARD = LVCMOS33;
NET "nSDVterm"	LOC = "AB6" | IOSTANDARD = "LVCMOS25";
NET "Relay"	LOC = "L5" | IOSTANDARD = LVCMOS33;

NET "BuzzP<0>"		LOC = "H13" | IOSTANDARD = LVCMOS33;
NET "BuzzN<0>"		LOC = "J13" | IOSTANDARD = LVCMOS33;
NET "BuzzP<1>"		LOC = "E13" | IOSTANDARD = LVCMOS33;
NET "BuzzN<1>"		LOC = "F13" | IOSTANDARD = LVCMOS33;
NET "BuzzP<2>"		LOC = "A13" | IOSTANDARD = LVCMOS33;
NET "BuzzN<2>"		LOC = "B13" | IOSTANDARD = LVCMOS33;
NET "BuzzP<3>"		LOC = "J14" | IOSTANDARD = LVCMOS33;
NET "BuzzN<3>"		LOC = "K14" | IOSTANDARD = LVCMOS33;
NET "BuzzP<4>"		LOC = "F14" | IOSTANDARD = LVCMOS33;
NET "BuzzN<4>"		LOC = "G14" | IOSTANDARD = LVCMOS33;
NET "BuzzP<5>"		LOC = "B14" | IOSTANDARD = LVCMOS33;
NET "BuzzN<5>"		LOC = "C14" | IOSTANDARD = LVCMOS33;
NET "BuzzP<6>"		LOC = "H15" | IOSTANDARD = LVCMOS33;
NET "BuzzN<6>"		LOC = "J15" | IOSTANDARD = LVCMOS33;
NET "BuzzP<7>"		LOC = "F15" | IOSTANDARD = LVCMOS33;
NET "BuzzN<7>"		LOC = "G15" | IOSTANDARD = LVCMOS33;
NET "BuzzP<8>"		LOC = "AD10" | IOSTANDARD = "LVDS_25";
NET "BuzzN<8>"		LOC = "AD11" | IOSTANDARD = "LVDS_25";
NET "BuzzP<9>"		LOC = "AE11" | IOSTANDARD = "LVDS_25";
NET "BuzzN<9>"		LOC = "AF11" | IOSTANDARD = "LVDS_25";
NET "BuzzP<10>"		LOC = "AC11" | IOSTANDARD = "LVDS_25";
NET "BuzzN<10>"		LOC = "AB12" | IOSTANDARD = "LVDS_25";
NET "BuzzP<11>"		LOC = "AC12" | IOSTANDARD = "LVDS_25";
NET "BuzzN<11>"		LOC = "AD12" | IOSTANDARD = "LVDS_25";

NET DBugD<0>	LOC = "K12" | IOSTANDARD = LVCMOS33;
NET DBugD<1>	LOC = "J12" | IOSTANDARD = LVCMOS33;
NET DBugD<2>	LOC = "B12" | IOSTANDARD = LVCMOS33;
NET DBugD<3>	LOC = "A12" | IOSTANDARD = LVCMOS33;
#NET DBugD<4>	LOC = "D15" | IOSTANDARD = LVCMOS33;
#NET DBugD<5>	LOC = "C15" | DRIVE = 16 | SLEW = FAST;
#NET DBugD<6>	LOC = "AH29";
#NET DBugD<7>	LOC = "AH30" | DRIVE = 16 | SLEW = FAST;
