---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: DataMux.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Programmable I/O for Pulser Receiver Card (PRx) System FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity SysIo is
  generic(
    gWidth   : in     integer := 32);
  port(
    pClock   : in     std_ulogic;
    pnReset  : in     std_ulogic;
    pnWE     : in     std_ulogic;
    pnCSData : in     std_ulogic;
    pnCSDir  : in     std_ulogic;
    pDataIn  : in     std_logic_vector(31 downto 0);
    pDataOut : out    std_logic_vector(31 downto 0);
    pDirOut  : out    std_logic_vector(31 downto 0);
    pIO      : inout  std_logic_vector(gWidth-1 downto 0));
end SysIo;

architecture RTL of SysIo is

  signal PioDataOut: std_logic_vector(gWidth-1 downto 0);
  signal PioDir: std_logic_vector(gWidth-1 downto 0);

begin

  PioFF: process (pClock, pnReset)
  begin
    if pnReset = '0' then
      PioDataOut <= (others => '0');
      PioDir <= (others => '0');
    elsif rising_edge(pClock) then
      if pnCSData ='0' and pnWE = '0' then
        PioDataOut <= pDataIn(gWidth-1 downto 0);
      end if;
      if pnCSDir = '0' and pnWE = '0' then
        PioDir <= pDataIn(gWidth-1 downto 0);
      end if;
    end if;
  end process PioFF;

  PioIp: process (pIO, PioDir)
  begin
    pDataOut <= (others => '0');
    pDirOut <= (others => '0');

    pDataOut(gWidth-1 downto 0) <= pIO;
    pDirOut(gWidth-1 downto 0) <= PioDir(gWidth-1 downto 0);
  end process PioIp;

  GenpIO: for Count in 0 to gWidth-1 generate
    pIO(Count) <= PioDataOut(Count) when PioDir(Count) = '1' else 'Z';
  end generate;

end architecture RTL;
