---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: SyncPulse.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Sync functions to move pulses between clock domains
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity SyncPulseUp is
  port (InClock  : in  std_ulogic;
        OutClock : in  std_ulogic;
        nReset   : in  std_ulogic;
        DIn      : in  std_ulogic;
        DOut     : out std_ulogic);
end SyncPulseUp;

-- move up in frequency (must be atleast 2 times freq.)
architecture Rtl of SyncPulseUp is
  signal  DInSample0 : std_ulogic;
  signal  DInSample1 : std_ulogic;
begin
    Sample : process (OutClock, nReset) is
    begin
      if nReset ='0' then
        DInSample0 <= '0';
        DInSample1 <= '0';
        DOut <= '0';
      elsif OutClock'event and OutClock = '1' then
--        DInSample0 <= DIn;
        DInSample0 <= DIn or (DinSample0 and not DInSample1); -- allow lower freq.
        DInSample1 <= DInSample0;
        DOut <= DInSample0 and not DInSample1; 
      end if;
    end process Sample;
end Rtl;


library IEEE;
use IEEE.std_logic_1164.all;

entity SyncPulseDown is
  port (InClock  : in  std_ulogic;
        OutClock : in  std_ulogic;
        nReset   : in  std_ulogic;
        DIn      : in  std_ulogic;
        DOut     : out std_ulogic);
end SyncPulseDown;

-- move down in frequency (must be atleast 2 times freq.)
architecture Rtl of SyncPulseDown is
  signal  DInExtend : std_ulogic;
  signal  iDOut     : std_ulogic;
  signal  DOutExtend: std_ulogic;
begin
    Extend : process (InClock, nReset) is
    begin
      if nReset ='0' then
        DInExtend <= '0';
      elsif InClock'event and InClock = '0' then -- falling edge to guarantee overlap
--        DInExtend <= DIn or (DInExtend and not iDOut);
        DInExtend <= DIn or (DInExtend and not DOutExtend);
      end if;
    end process Extend;

    Pulse : process (OutClock, nReset) is
    begin
      if nReset ='0' then
        iDOut <= '0';
        DOutExtend <= '1';
      elsif (OutClock'event and OutClock = '1') then
        iDOut <= (DIn or DInExtend) and not iDout;
        DOutExtend <= iDout or (DOutExtend and DInExtend);
      end if;
    end process Pulse;

    DOut <= iDOut;

end Rtl;
