---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SyncPulse.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card Control FPGA
--
-- Design Description:
-- Sync functions to move pulses between clock domains
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity SyncPulseUp is
  port(
    pInClock  : in  std_ulogic;
    pOutClock : in  std_ulogic;
    pnReset   : in  std_ulogic;
    pDIn      : in  std_ulogic;
    pDOut     : out std_ulogic);
end SyncPulseUp;

-- move up in frequency (must be atleast 2 times freq.)
architecture Rtl of SyncPulseUp is
  signal  DInSample0 : std_ulogic;
  signal  DInSample1 : std_ulogic;
begin
    Sample : process (pOutClock, pnReset) is
    begin
      if (pnReset ='0') then
        DInSample0 <= '0';
        DInSample1 <= '0';
        pDOut <= '0';
      elsif (pOutClock'event and pOutClock = '1') then
        DInSample0 <= pDIn;
        DInSample1 <= DInSample0;
        pDOut <= DInSample0 and not DInSample1; 
      end if;
    end process Sample;
end Rtl;


library IEEE;
use IEEE.std_logic_1164.all;

entity SyncPulseDown is
  port(
    pInClock  : in  std_ulogic;
    pOutClock : in  std_ulogic;
    pnReset   : in  std_ulogic;
    pDIn      : in  std_ulogic;
    pDOut     : out std_ulogic);
end SyncPulseDown;

-- move down in frequency (must be atleast 2 times freq.)
architecture Rtl of SyncPulseDown is
  signal  DInExtend : std_ulogic;
  signal  DOut      : std_ulogic;
begin
    Extend : process (pInClock, pnReset) is
    begin
      if (pnReset ='0') then
        DInExtend <= '0';
      elsif (pInClock'event and pInClock = '0') then -- falling edge to guarantee overlap
        if (pDIn = '1') then
          DInExtend <= '1';
        elsif (Dout = '1') then
          DInExtend <= '0';
        end if;
      end if;
    end process Extend;

    Pulse : process (pOutClock, pnReset) is
    begin
      if (pnReset ='0') then
        DOut <= '0';
      elsif (pOutClock'event and pOutClock = '1') then
        DOut <= (pDIn or DInExtend) and not Dout;
      end if;
    end process Pulse;

    pDOut <= DOut;

end Rtl;
