---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: GrayCounter4Bit.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Gray counter with asynchronous reset
---------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
library UNISIM;
use UNISIM.Vcomponents.all;


entity GrayCounter4BitWr is
  port (Clk     : in  std_ulogic;
        Reset   : in  std_ulogic;
        CountEn : in  std_ulogic;
        GrCount : out std_logic_vector(3 downto 0));
end GrayCounter4BitWr;

architecture Rtl of GrayCounter4BitWr is

  signal DIn      : std_logic_vector(3 downto 0);
  signal iGrCount : std_logic_vector(3 downto 0);

begin
  
  process(iGrCount)
  begin
    case iGrCount is
      when "0000" => DIn <= "0001";    --0 > 1
      when "0001" => DIn <= "0011";    --1 > 3
      when "0010" => DIn <= "0110";    --2 > 6
      when "0011" => DIn <= "0010";    --3 > 2
      when "0100" => DIn <= "1100";    --4 > c
      when "0101" => DIn <= "0100";    --5 > 4
      when "0110" => DIn <= "0111";    --6 > 7
      when "0111" => DIn <= "0101";    --7 > 5
      when "1000" => DIn <= "0000";    --8 > 0
      when "1001" => DIn <= "1000";    --9 > 8
      when "1010" => DIn <= "1011";    --a > b
      when "1011" => DIn <= "1001";    --b > 9
      when "1100" => DIn <= "1101";    --c > d
      when "1101" => DIn <= "1111";    --d > f
      when "1110" => DIn <= "1010";    --e > a
      when "1111" => DIn <= "1110";    --f > e
      when others => DIn <= "0001";    --0 > 1
    end case;
  end process;

  bit0 : FDCE
    port map (Q   => iGrCount(0),
              C   => Clk,
              CE  => CountEn,
              CLR => Reset,
              D   => DIn(0));

  bit1 : FDCE
    port map (Q   => iGrCount(1),
              C   => Clk,
              CE  => CountEn,
              CLR => Reset,
              D   => DIn(1));
  
  bit2 : FDCE
    port map (Q   => iGrCount(2),
              C   => Clk,
              CE  => CountEn,
              CLR => Reset,
              D   => DIn(2));

  bit3 : FDCE
    port map (Q   => iGrCount(3),
              C   => Clk,
              CE  => CountEn,
              CLR => Reset,
              D   => DIn(3));

  GrCount <= iGrCount;

end Rtl;
