---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: HC595.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 System FPGA
--
-- Design Description:
-- SIPO shift register model
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

entity HC595 is
  port (SH_CP : in  std_ulogic; -- 20MHz Max
        ST_CP : in  std_ulogic; -- 20MHz Max
        nMR   : in  std_ulogic;
        nOE   : in  std_ulogic;
        --
        DS    : in  std_ulogic;
        Q7s   : out   std_ulogic;
        Q     : out   std_logic_vector(7 downto 0));
end entity HC595;


architecture Beh of HC595 is
  signal DShift: std_logic_vector(7 downto 0);
  signal QOut: std_logic_vector(7 downto 0);

begin

  Shift : process(nMR, SH_CP)
  begin
    if nMR = '0' then
      DShift <= (others => '0');
    elsif rising_edge(SH_CP) then
      DShift <= DShift(6 downto 0) & DS;
    end if;
  end process Shift;

  Q7s <= DShift(7) after 63 ns;

  OpLatch : process(nMR, ST_CP)
  begin
    if nMR = '0' then
      QOut <= (others => '0');
    elsif rising_edge(ST_CP) then
      QOut <= DShift;
    end if;
  end process OpLatch;

  -- output assignment
  Q <= QOut after 60 ns when nOE = '0' else (others => 'Z') after 45 ns;

end architecture Beh;
