---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: EEPROM.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Manage Read/Write access to the EEPROM.
-- This is a wrapper around original code by CG
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;

entity EEPROM is
  port (
    pnReset    : in  std_ulogic;
    pClock     : in  std_ulogic;
    pDoWrite   : in  std_ulogic;
    pDoRead    : in  std_ulogic;
    pnWE       : in  std_ulogic;
    pnCS       : in  std_ulogic;
    pAddress   : in  std_logic_vector(7 downto 0);
    pDataIn    : in  std_logic_vector(31 downto 0);
    pEEPROM_Q  : in  std_ulogic;         -- EEPROM Read Data
    pBusy      : out std_ulogic;
    pEEPROM_C  : out std_ulogic;         -- EEPROM Clock
    pEEPROM_nS : out std_ulogic;         -- EEPROM Chip Select
    pEEPROM_D  : out std_ulogic;         -- EEPROM Write Data
    pDataOut   : out std_logic_vector(31 downto 0));
end EEPROM;


architecture RTL of EEPROM is

  component EepromCtrl
    port (
      pnReset      : in  std_ulogic;
      pLCLKA       : in  std_ulogic;
      pWriteEeprom : in  std_ulogic;
      pReadEeprom  : in  std_ulogic;
      pEepromBusy  : out std_ulogic;
      pDebug       : out std_logic_vector(7 downto 0);
      pBRamWriteEn : out std_ulogic;
      pBRamAddr    : out std_logic_vector(5 downto 0);
      pBRamWrData  : out std_logic_vector(31 downto 0);
      pBRamRdData  : in  std_logic_vector(31 downto 0);
      pEeprom_C    : out std_ulogic;
      pEeprom_nS   : out std_ulogic;
      pEeprom_D    : out std_ulogic;
      pEeprom_Q    : in  std_ulogic);
  end component;
  
  component DPBRAM32x256
    port (
      pnReset  : in  std_ulogic;
      pClock   : in  std_ulogic;
      AddressA : in  std_logic_vector(7 downto 0);
      AddressB : in  std_logic_vector(7 downto 0);
      DataInA  : in  std_logic_vector(31 downto 0);
      DataInB  : in  std_logic_vector(31 downto 0);
      WriteEnA : in  std_ulogic;
      WriteEnB : in  std_ulogic;
      DataOutA : out std_logic_vector(31 downto 0);
      DataOutB : out std_logic_vector(31 downto 0));
  end component;
  
  signal B_Address   : std_logic_vector(7 downto 0);
  signal B_DataRead  : std_logic_vector(31 downto 0);
  signal B_DataWrite : std_logic_vector(31 downto 0);
  signal B_WE        : std_ulogic;
  signal A_WE        : std_ulogic;

begin

  B_Address(7 downto 6) <= "00";
  A_WE <= '1' when (pnCS = '0' and pnWE = '0') else '0';

  EepromCtrl_1 : EepromCtrl
    port map (
      pnReset      => pnReset,
      pLCLKA       => pClock,
      pWriteEeprom => pDoWrite,
      pReadEeprom  => pDoRead,
      pEepromBusy  => pBusy,
      pDebug       => open,
      pBRamWriteEn => B_WE,
      pBRamAddr    => B_Address(5 downto 0),
      pBRamWrData  => B_DataWrite,
      pBRamRdData  => B_DataRead,
      pEeprom_C    => pEeprom_C,
      pEeprom_nS   => pEeprom_nS,
      pEeprom_D    => pEeprom_D,
      pEeprom_Q    => pEeprom_Q);

  DPBRAM32x256_1 : DPBRAM32x256
    port map (
      pnReset  => pnReset,
      pClock   => pClock,
      AddressA => pAddress,
      AddressB => B_Address,
      DataInA  => pDataIn,
      DataInB  => B_DataWrite,
      WriteEnA => A_WE,
      WriteEnB => B_WE,
      DataOutA => pDataOut,
      DataOutB => B_DataRead);

end architecture RTL;

