---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: SimCtrl003.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Simulation Control file to for General DSP testing
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


architecture Test of SimCtrl is

  -- DSP Sequence Table registers
  constant cInputSelReg           : integer := 16#00301000#;
  constant cFilterCtrlReg         : integer := 16#00301004#;
  constant cRectifierModeReg      : integer := 16#00301008#;
  constant cDropSamplesReg        : integer := 16#0030100C#;
  constant cAScanRepRateReg       : integer := 16#00301010#;
  constant cPulseWidthReg         : integer := 16#00301014#;
  constant cPulseTrainReg         : integer := 16#00301018#;
  constant cAScanRangeReg         : integer := 16#0030101C#;
  constant cTriggerDelayReg       : integer := 16#0030102C#;
  constant cSeqStepCtrlReg        : integer := 16#00301030#;
  -- Other DSP Registers
  constant cDSPCheckReg           : integer := 16#00305000#;
  constant cADCSerialCtrlReg      : integer := 16#00305004#;
  constant cRawADCDataReg         : integer := 16#00305008#;
  constant cHVDACDataReg          : integer := 16#00305010#;
  constant cHVDACCtrlReg          : integer := 16#00305014#;
  constant cHVCtrlReg             : integer := 16#00305018#;
  constant cRAMBankSizeReg        : integer := 16#0030501C#;
  constant cSeqRepRateReg         : integer := 16#00305020#;
  constant cSeqPerBankReg         : integer := 16#00305024#;
  constant cRAMControlReg         : integer := 16#00305028#;
  constant cSeqTriggerModeReg     : integer := 16#00305038#;
  constant cSeqTriggerForceReg    : integer := 16#0030503C#;
  constant cSeqInRamReg           : integer := 16#00305040#;
  constant cSampleCtrlReg         : integer := 16#00305044#;
  constant cSeqCtrlReg            : integer := 16#003050A4#;

  constant cTCGRAMOffset          : integer := 16#00000000#;

begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15.152 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing DSP Check Register"));
    writeline (OUTPUT, vLine);

    LBusRead(cDspCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FFFFFFFF# then
      write (vLine, string'("Testbench: Error - Expected 0xFFFFFFFF from DSP Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cDspCheckReg, 16#5555AAAA#, ToBusModel, FromBusModel);
    LBusRead(cDspCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AAAA5555# then
      write (vLine, string'("Testbench: Error - Expected 0xAAAA5555 from DSP Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cDspCheckReg, 16#00000001#, ToBusModel, FromBusModel);
    LBusRead(cDspCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FFFFFFFE# then
      write (vLine, string'("Testbench: Error - Expected 0xFFFFFFFE from DSP Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    write (vLine, string'("Testbench: DSP Check Register tests complete"));
    writeline (OUTPUT, vLine);

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing Shift register controls"));
    writeline (OUTPUT, vLine);

    LBusWrite(cInputSelReg, 16#FFFFFFFF#, ToBusModel, FromBusModel);
    LBusWrite(cFilterCtrlReg, 16#0000FFFF#, ToBusModel, FromBusModel);

    wait for 100 us;
    if DspShiftData /= x"FFFF7F7FFF" then
      write (vLine, string'("Testbench: Error - Expected 0xFFFF7F7FFF from DSP Shift register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    if FSel /= x"F" then
      write (vLine, string'("Testbench: Error - Expected 0xF from Attenuator control"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cInputSelReg, 16#0A0A55AA#, ToBusModel, FromBusModel);
    LBusWrite(cFilterCtrlReg, 16#00000102#, ToBusModel, FromBusModel);

    wait for 100 us;
    if DspShiftData /= x"01020A55AA" then
      write (vLine, string'("Testbench: Error - Expected 0x01020A55AA from DSP Shift register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    if FSel /= x"A" then
      write (vLine, string'("Testbench: Error - Expected 0xA from Attenuator control"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cInputSelReg, 16#05102030#, ToBusModel, FromBusModel);
    LBusWrite(cFilterCtrlReg, 16#0000AA55#, ToBusModel, FromBusModel);

    wait for 100 us;
    if DspShiftData /= x"AA55102030" then
      write (vLine, string'("Testbench: Error - Expected 0xAA55102030 from DSP Shift register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;
    if FSel /= x"5" then
      write (vLine, string'("Testbench: Error - Expected 0x5 from Attenuator control"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    write (vLine, string'("Testbench: Shift register test complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing HV DAC & Control"));
    writeline (OUTPUT, vLine);

    LBusWrite(cHVDACDataReg, 16#2AA8#, ToBusModel, FromBusModel);
    LBusWrite(cHVDACCtrlReg, 16#00000001#, ToBusModel, FromBusModel);

    LBusRead(cHVDACCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cHVDACCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;

    if HvAdj /= 16#AAA# then
      write (vLine, string'("Testbench: Error - Expected 0xAAA from HV DAC"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    wait for 100 ns;

    LBusWrite(cHVDACDataReg, 16#1554#, ToBusModel, FromBusModel);
    LBusWrite(cHVDACCtrlReg, 16#00000001#, ToBusModel, FromBusModel);

    LBusRead(cHVDACCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cHVDACCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;

    if HvAdj /= 16#555# then
      write (vLine, string'("Testbench: Error - Expected 0x555 from HV DAC"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cHVCtrlReg, 16#00000002#, ToBusModel, FromBusModel);
    if HvEn /= '1' or HVDischarge /= '0' then
      write (vLine, string'("Testbench: Error - Expected HvEn = 1 and HVDischarge = 0"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    HVFeedback <= '1';
    LBusRead(cHVCtrlReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#80000002# then
      write (vLine, string'("Testbench: Error - Expected 0x80000002 from HV control register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cHVCtrlReg, 16#00000001#, ToBusModel, FromBusModel);
    if HvEn /= '0' or HVDischarge /= '1' then
      write (vLine, string'("Testbench: Error - Expected HvEn = 0 and HVDischarge = 1"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    HVFeedback <= '0';
    LBusRead(cHVCtrlReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#00000001# then
      write (vLine, string'("Testbench: Error - Expected 0x00000001 from HV control register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    write (vLine, string'("Testbench: HV DAC & control test complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing main ADC Serial interface"));
    writeline (OUTPUT, vLine);

    LBusWrite(cADCSerialCtrlReg, 16#01800100#, ToBusModel, FromBusModel);

    LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;
    if vRData /= 16#0080010C# then
      write (vLine, string'("Testbench: Error - Expected 0x0080010C from ADC Chip ID register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cADCSerialCtrlReg, 16#01800000#, ToBusModel, FromBusModel);

    LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;
    if vRData /= 16#00800018# then
      write (vLine, string'("Testbench: Error - Expected 0x00800018 from ADC Chip port config register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cADCSerialCtrlReg, 16#0100005A#, ToBusModel, FromBusModel);
    LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;

    LBusWrite(cADCSerialCtrlReg, 16#01800000#, ToBusModel, FromBusModel);

    LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    while (vRData and 16#80000000#) /= 0 loop
      LBusRead(cADCSerialCtrlReg, vRData, ToBusModel, FromBusModel);
    end loop;
    if vRData /= 16#0080005A# then
      write (vLine, string'("Testbench: Error - Expected 0x0080005A from ADC Chip port config register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    write (vLine, string'("Testbench: ADC Serial interface test complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing Processor TCG RAM access"));
    writeline (OUTPUT, vLine);

    -- write some data
    for i in 0 to 256 loop
      LBusWrite(cTCGRAMOffset+(i*4), i+1, ToBusModel, FromBusModel);
    end loop;

    -- Read some data
    for i in 0 to 256 loop
      LBusRead(cTCGRAMOffset+(i*4), vRData, ToBusModel, FromBusModel);
      if vRData /= i+1 then
        write (vLine, string'("Testbench: Error - Processor TCG RAM read error"));
        writeline (OUTPUT, vLine);
        vTestFail := true;
      end if;
    end loop;

    write (vLine, string'("Testbench: Processor TCG RAM access tests complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation 003 completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation 003 completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;