---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: ClockReset.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Clock and Reset generators
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity ClockReset is
  port(
    pClockIn   : in  std_ulogic;
    pClockOut  : out std_ulogic;
    pnResetIn  : in  std_ulogic;
    pnResetOut : out std_ulogic);
end ClockReset;

architecture RTL of ClockReset is

  signal Clock       : std_ulogic;
  signal ClockInBuff : std_ulogic;
  signal ClockDLL    : std_ulogic;
  signal Reset       : std_ulogic;

begin

  pClockOut <= Clock;
  Reset     <= not pnResetIn;

  IBUFG0 : IBUFG
    port map(
      I => pClockIn,
      O => ClockInBuff);

  CLKDLL0 : CLKDLL
    port map(
      CLKIN  => ClockInBuff,
      CLKFB  => Clock,
      RST    => Reset,
      CLK0   => ClockDLL,
      CLK90  => open,
      CLK180 => open,
      CLK270 => open,
      CLK2X  => open,
      CLKDV  => open,
      LOCKED => pnResetOut);

  BUFG0 : BUFG
    port map(
      I => ClockDLL,
      O => Clock);

end architecture RTL;

