---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: ControlFPGATop.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card Control FPGA
--
-- Design Description:
-- Top level of Pulser Receiver Card (PRx) Control FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;

library UNISIM;
use UNISIM.vcomponents.all;
use work.ControlFpga_pkg.all;

entity ControlFPGATop is
  port( -- clock input
    pClock          : in  std_ulogic;
    -- System FPGA signals
    pnReset         : in  std_ulogic;
    pSTxD           : out std_ulogic;
    pSRxD           : in  std_ulogic;
    pHVStatus       : out std_ulogic;
    -- trigger and delay i/o
    pTrigger        : in  std_ulogic;
    pTriggerOut     : out std_ulogic;
    pTriggerDel     : in  std_ulogic;
    pFineDelay      : out std_logic_vector(7 downto 0);
    pAck            : out std_ulogic;
    -- control i/o
    pTestPort       : out std_logic_vector(7 downto 0);
    pSap            : out std_ulogic;
    pScreen0        : out std_ulogic;
    pPRxChk         : out std_ulogic;
    pScreen1        : out std_ulogic;
    pTSynch         : out std_ulogic;
    pExternalGainEn : out std_ulogic;
    pInternalGainEn : out std_ulogic;
    pBeHighPass     : out std_logic_vector(2 downto 0);
    pBeLowPass      : out std_logic_vector(2 downto 0);
    pHighPass       : out std_logic_vector(2 downto 0);
    pLowPass        : out std_logic_vector(2 downto 0);
    pFrontPlus20dB  : out std_ulogic;
    pFrontMinus40dB : out std_ulogic;
    pFront0dB       : out std_ulogic;
    pFrontMinus20dB : out std_ulogic;
    pMpx0dB         : out std_ulogic;
    pMpx20dB        : out std_ulogic;
    pRin47          : out std_ulogic;
    pRin100         : out std_ulogic;
    pRin270         : out std_ulogic;
    pRin470         : out std_ulogic;
    pPEChSel        : out std_logic_vector(8 downto 1);
    pRxChSel        : out std_logic_vector(8 downto 1);
    pPulse          : out std_logic_vector(8 downto 1);
    pHighVoltageEn  : out std_ulogic;
    pHighVoltageOK  : in  std_ulogic;
    pnPowerOn       : out std_ulogic;
    pnPowerOOT      : in  std_ulogic;
    pHTVOOT         : in  std_ulogic;
    pHTIOOT         : in  std_ulogic;
    pHTIsEn         : in  std_ulogic;
    pDAC_nCS        : out std_ulogic;
    pDAC_SDI        : out std_ulogic;
    pDAC_Clk        : out std_ulogic);
end ControlFPGATop;

architecture RTL of ControlFPGATop is

  component CtrlControl
    port (
      pnReset  : in  std_ulogic;
      pClock   : in  std_ulogic;
      pDataIn  : in  std_logic_vector(7 downto 0);
      pDataOut : out std_logic_vector(7 downto 0);
      pAddress : out std_logic_vector(31 downto 0);
      pPAD     : out std_logic_vector(7 downto 0);
      pOE      : out std_ulogic;
      pWE      : out std_ulogic;
      pSRxD    : in  std_ulogic;
      pSTxD    : out std_ulogic);
  end component;

  component CtrlBitIO
    port(
      pClock   : in  std_ulogic;
      pnReset  : in  std_logic;
      pPAD     : in  std_logic_vector(7 downto 0);
      pWE      : in  std_ulogic;
      pDataIn  : in  std_ulogic;
      pPortIn  : in  std_logic_vector(7 downto 0);
      pDataOut : out std_ulogic;
      pPortOut : out std_logic_vector(7 downto 0));
  end component;

  component OutPort32
    generic(
      gRstVal  : in  std_logic_vector(31 downto 0));
    port(
      pClock   : in  std_ulogic;
      pnReset  : in  std_ulogic;
      pWE      : in  std_ulogic;
      pDataIn  : in  std_logic_vector(7 downto 0);
      pPAD     : in  std_logic_vector(7 downto 0);
      pDataOut : out std_logic_vector(31 downto 0);
      pSyncSet : in  std_logic_vector(31 downto 0));
  end component;

  component InPort32
    generic(
	  gBase    : std_logic_vector(7 downto 0) := x"20");
    port(
      pClock   : in  std_ulogic;
      pnReset  : in  std_ulogic;
      pnWE     : in  std_ulogic;
      pPAD     : in  std_logic_vector(7 downto 0);
      pDataIn  : in  std_logic_vector(31 downto 0);
      pDataOut : out std_logic_vector(31 downto 0);
      pDOut8   : out std_logic_vector(7 downto 0);
      pSyncClr : in  std_logic_vector(31 downto 0));
  end component;

  component SyncPulseUp
    port(
      pInClock  : in  std_ulogic;
      pOutClock : in  std_ulogic;
      pnReset   : in  std_ulogic;
      pDIn      : in  std_ulogic;
      pDOut     : out std_ulogic);
  end component;

  component SyncPulseDown
    port(
      pInClock  : in  std_ulogic;
      pOutClock : in  std_ulogic;
      pnReset   : in  std_ulogic;
      pDIn      : in  std_ulogic;
      pDOut     : out std_ulogic);
  end component;

  component PulseGen
    port(
      pClock        : in  std_ulogic;
      pClockx2      : in  std_ulogic;
      pnReset       : in  std_ulogic;
      pTrigger      : in  std_ulogic;
      pTriggerOut   : out std_ulogic;
      pTriggerDel   : in  std_ulogic;
      pPulse        : out std_logic_vector(8 downto 1);
      pPulseDisable : in  std_logic_vector(8 downto 1);
      pIntTrigDis   : in  std_ulogic;
      pExtTrigEn    : in  std_ulogic;
      pTxEn         : in  std_logic_vector(7 downto 0);
      pPulseWidth   : in  std_logic_vector(15 downto 0);
      pPulseCount   : in  std_logic_vector(3 downto 0);
      pRepRate      : in  std_logic_vector(31 downto 0);
      pNewSeqTable  : in  std_ulogic;
      pUpdatePulse  : out std_ulogic;
      pAckStart     : in  std_ulogic;
      pAckEn        : in  std_ulogic;
      pAck          : out std_ulogic);
  end component;

  component OverloadDetect
    port(
      pClock        : in  std_ulogic;
      pnReset       : in  std_ulogic;
      pPulse        : in  std_logic_vector(8 downto 1);
      pHVControl    : in  std_logic_vector(2 downto 0);
      pnAutoReset   : in  std_ulogic;
      pPulseDisable : out std_logic_vector(8 downto 1);
      pOverload     : out std_ulogic;
      pOverloadClear: in  std_ulogic);
  end component;

  component CtrlSequenceTable
    port (
      pnReset       : in  std_ulogic;
      pClock        : in  std_ulogic;
      pWE           : in  std_ulogic;
      pPAD          : in  std_logic_vector(7 downto 0);
      pAddress      : in  std_logic_vector(9 downto 0);
      pDataIn       : in  std_logic_vector(7 downto 0);
	    pNewTable     : in  std_ulogic;
      pUpdateTable  : in  std_ulogic;
      pStepSkip     : in  std_logic_vector(4 downto 0);
      pOverSample   : in  std_logic_vector(7 downto 0);
      pFineDelInc   : in  std_logic_vector(7 downto 0);
      pFineDelay    : out std_logic_vector(7 downto 0);
      pAckStart     : out std_ulogic;
      pAckEn        : out std_ulogic;
      pSeqTableEn   : out std_logic_vector(7 downto 0);
      pSeqTable0    : out std_logic_vector(31 downto 0);
      pSeqTable1    : out std_logic_vector(31 downto 0);
      pSeqTable2    : out std_logic_vector(31 downto 0);
      pSeqTable3    : out std_logic_vector(31 downto 0);
      pSeqTable4    : out std_logic_vector(31 downto 0);
      pSeqTable5    : out std_logic_vector(31 downto 0);
      pSeqTable6    : out std_logic_vector(31 downto 0);
      pSeqTable7    : out std_logic_vector(31 downto 0));
  end component;

  component DeMux3_8
    port(
      pDIn  : in  std_logic_vector(2 downto 0);
      pDOut : out std_logic_vector(7 downto 0));
  end component;

  component DacSerial
    port(
      pClock   : in  std_ulogic;   -- 33MHz Clock
      pnReset  : in  std_ulogic;
      pDInA    : in  std_logic_vector(11 downto 0);
      pDInAEn  : in  std_ulogic;
      pDinB    : in  std_logic_vector(11 downto 0);
      pDInBEn  : in  std_ulogic;
      pBusy    : out std_ulogic;
      -- DAC signals
      pDAC_nCS : out std_ulogic;
      pDAC_SDI : out std_ulogic;
      pDAC_Clk : out std_ulogic);
  end component;

  component StrobeExtender is
    generic(gLfsrBits: integer range 3 to 32 := 3);
    port(pnReset    : in  std_ulogic;
         pClk       : in  std_ulogic;
         pStrobeIn  : in  std_ulogic;
         pStrobeOut : out std_ulogic);
  end component StrobeExtender;

  component UltranPowerSm
	  port (
		  Clock: in STD_LOGIC;						  --State machine clock no need for speed
		  nHT_I_OOT: in STD_LOGIC;					  --Input from amplifier to indicate HT current overload
		  nHT_IS_EN: in STD_LOGIC;					  --Input from amplifier to indicate HT is enabled
		  nHT_V_OOT: in STD_LOGIC;					  --Input from amplifier to indicate HT voltage OOT
		  nPowerOOT: in STD_LOGIC;					  --Input from amplifier to indicate internal supplier OOT
		  Req_HT_ON: in STD_LOGIC;					  --Connect to register bit to turn on HT
		  Req_P_ON: in STD_LOGIC;						  --Connect to register bit to turn on amplifier supplies
		  nReset: in STD_LOGIC;						  --Reset for state machine
		  Fault: out STD_LOGIC_VECTOR (3 downto 0);	  --Indication of fault code - connect to register
		  Interrupt: out STD_LOGIC;					  --Interrupt request during serious fault codes
		  nHT_ON: out STD_LOGIC;						  --Logic output to amplifier that turns on HT
		  nPowerON: out STD_LOGIC);					  --Logic output to amplifier that turns on supplies
  end component;

  -- attributes give divde by 3 for DLL CLKDV output
  attribute CLKDV_DIVIDE : real; 
  attribute CLKDV_DIVIDE of CLKDLL1 : label is 3.0;

  signal nReset       : std_ulogic;  -- Local reset, from the LOCKED signal of DLL
  signal Clock        : std_ulogic;  -- Local clock - output of DLL
  signal ClockInBuff  : std_ulogic;
  signal ClockDLL0    : std_ulogic;
  signal ClockDLL1    : std_ulogic;
  signal ClockFB      : std_ulogic;
  signal Clock33      : std_ulogic;
  signal CtrlClock    : std_ulogic;  -- 33MHz clock for control circuitry
  signal Clock200     : std_ulogic;
  signal Clockx2      : std_ulogic;  -- 200MHz clock

  signal Reset        : std_ulogic;
  -- picoBlaze signals
  signal Address      : std_logic_vector(31 downto 0);
  signal DataIn       : std_logic_vector(7 downto 0);
  signal DataOut      : std_logic_vector(7 downto 0);
  signal PAD          : std_logic_vector(7 downto 0);
  signal OE           : std_ulogic;
  signal WE           : std_ulogic;
  signal BitPortIn    : std_logic_vector(7 downto 0) := (others => '0');
  signal BitPortOut   : std_logic_vector(7 downto 0);
  signal BitDataIn    : std_ulogic;
  signal StatusDataIn : std_logic_vector(7 downto 0);

  signal NewSeqTable100: std_ulogic;
  signal UpdateTable  : std_ulogic;
  signal UpdatePulse  : std_ulogic;
  signal AckStart33   : std_ulogic;
  signal AckStart100  : std_ulogic;
  signal AckEn        : std_ulogic;

  signal GlobalConfig : std_logic_vector(31 downto 0);
  signal SeqTable0    : std_logic_vector(31 downto 0);
  signal SeqTable1    : std_logic_vector(31 downto 0);
  signal SeqTable2    : std_logic_vector(31 downto 0);
  signal SeqTable3    : std_logic_vector(31 downto 0);
  signal SeqTable4    : std_logic_vector(31 downto 0);
  signal SeqTable5    : std_logic_vector(31 downto 0);
  signal SeqTable6    : std_logic_vector(31 downto 0);
  signal SeqTable7    : std_logic_vector(31 downto 0);
  signal SeqTableEn   : std_logic_vector(7 downto 0);
  signal SeqValid     : std_ulogic;
  signal IntTrigDis   : std_ulogic;
  signal Status       : std_logic_vector(31 downto 0);

  signal FineGainControl : std_logic_vector(11 downto 0);
  signal HVControl       : std_logic_vector(11 downto 0);
  signal PulseDisable    : std_logic_vector(8 downto 1);
  signal HighVoltageEn   : std_logic;

  signal Pulse        : std_logic_vector(8 downto 1);
  signal TestCount    : std_logic_vector(7 downto 0);
  signal SapPulse     : std_ulogic;
  signal TSynchPulse  : std_ulogic;

begin

  Reset <= not pnReset;

  IBUFG1 : IBUFG
    port map(
      I => pClock,
      O => ClockInBuff);

  CLKDLL0 : CLKDLL
    port map(
      CLKIN  => ClockInBuff,
      CLKFB  => Clockx2,
      RST    => Reset,
      CLK0   => ClockDLL0,
      CLK90  => open,
      CLK180 => open,
      CLK270 => open,
      CLK2X  => Clock200,
      CLKDV  => open,
      LOCKED => open);

  BUFG0 : BUFG
    port map(
      I => Clock200,
      O => Clockx2);

  BUFG1 : BUFG
    port map(
      I => ClockDLL0,
      O => Clock);

  CLKDLL1 : CLKDLL
    -- synthesis translate_off
    generic map(
      SIM_CLKIN_CYCLE_JITTER => 50 ns,
      SIM_CLKIN_PERIOD_JITTER => 50 ns,
      CLKDV_DIVIDE => 3.0)
    -- synthesis translate_on
    port map(
      CLKIN  => Clock,
      CLKFB  => ClockFB,
      RST    => Reset,
      CLK0   => ClockDLL1,
      CLK90  => open,
      CLK180 => open,
      CLK270 => open,
      CLK2X  => open,
      CLKDV  => Clock33,
      LOCKED => nReset);

  BUFG2 : BUFG
    port map(
      I => Clock33,
      O => CtrlClock);

  BUFG3 : BUFG
    port map(
      I => ClockDLL1,
      O => ClockFB);

  Control_1 : CtrlControl
    port map(
      pnReset  => nReset,
      pClock   => CtrlClock,
      pDataIn  => DataIn,
      pDataOut => DataOut,
      pAddress => Address,
      pPAD     => PAD,
      pOE      => OE,
      pWE      => WE,
      pSRxD    => pSRxD,
      pSTxD    => pSTxD);

  Status_1: InPort32
    generic map(
      gBase    => x"20")
    port map(
      pClock   => CtrlClock,
      pnReset  => nReset,
      pnWE     => WE,
      pPAD     => PAD,
      pDataIn  => Status,
      pDataOut => open,
      pDOut8   => StatusDataIn,
      pSyncClr => (others => '0'));

  Status(2 downto 0) <= (others => '0');
  Status(7 downto 5) <= (others => '0');
  Status(31 downto 12) <= (others => '0');

  BitIO_1: CtrlBitIO
    port map(
      pClock   => CtrlClock,
      pnReset  => nReset,
      pPAD     => PAD,
      pWE      => WE,
      pDataIn  => DataOut(0),
      pPortIn  => (others => '0'),
      pDataOut => BitDataIn,
      pPortOut => BitPortOut);

  DataIn <= StatusDataIn or ("0000000" & BitDatain);

  GlbConf_1: OutPort32
    generic map(
      gRstVal  => x"00010000")
    port map(
      pClock   => CtrlClock,
      pnReset  => nReset,
      pWE      => WE,
      pDataIn  => DataOut,
      pPAD     => PAD,
      pDataOut => GlobalConfig,
      pSyncSet => (others => '0'));


  Test : process (CtrlClock) is
  begin
    if rising_edge(CtrlClock) then
      TestCount <= unsigned(TestCount) + '1';
    end if;
  end process Test;

  -- bring out Global config pins [6:0] to LEDs for testing
  pTestPort(6 downto 0) <= GlobalConfig(6 downto 0);
  pTestPort(7) <= updatePulse;

  SeqTab_1: CtrlSequenceTable
    port map(
      pnReset       => nReset,
      pClock        => CtrlClock,
      pWE           => WE,
      pPAD          => PAD,
      pAddress      => Address(9 downto 0),
      pDataIn       => DataOut,
	    pNewTable     => BitPortOut(1),
      pUpdateTable  => UpdateTable,
      pStepSkip     => SeqTable0(28 downto 24),
      pOverSample   => SeqTable4(23 downto 16),
      pFineDelInc   => SeqTable4(7 downto 0),
      pFineDelay    => pFineDelay,
      pAckStart     => AckStart33,
      pAckEn        => AckEn,
      pSeqTableEn   => SeqTableEn,
      pSeqTable0    => SeqTable0,
      pSeqTable1    => SeqTable1,
      pSeqTable2    => SeqTable2,
      pSeqTable3    => SeqTable3,
      pSeqTable4    => SeqTable4,
      pSeqTable5    => SeqTable5,
      pSeqTable6    => SeqTable6,
      pSeqTable7    => SeqTable7);

  -- move pulses between clock domains
  AckSync: SyncPulseUp
    port map(
      pInClock  => CtrlClock,
      pOutClock => Clock,
      pnReset   => nReset,
      pDIn      => AckStart33,
      pDOut     => AckStart100);

  UpdateSync: SyncPulseDown
    port map(
      pInClock  => Clock,
      pOutClock => CtrlClock,
      pnReset   => nReset,
      pDIn      => updatePulse,
      pDOut     => UpdateTable);

  NewSeqTableSync: SyncPulseUp
    port map(
      pInClock  => CtrlClock,
      pOutClock => Clock,
      pnReset   => nReset,
      pDIn      => BitPortOut(1),
      pDOut     => NewSeqTable100);

  IntTrigDisSync: SyncPulseUp
    port map(
      pInClock  => CtrlClock,
      pOutClock => Clock,
      pnReset   => nReset,
      pDIn      => BitPortOut(2),
      pDOut     => IntTrigDis);

  -- Pulse generation
  Pulse_1: PulseGen
    port map(
      pClock        => Clock,
      pClockx2      => Clockx2,
      pnReset       => nReset,
      pTrigger      => pTrigger,
      pTriggerOut   => pTriggerOut,
      pTriggerDel   => pTriggerDel,
      pPulse        => Pulse,
      pPulseDisable => PulseDisable,
      pIntTrigDis   => IntTrigDis,
      pExtTrigEn    => GlobalConfig(16),
      pTxEn         => SeqTable0(7 downto 0), 
      pPulseWidth   => SeqTable5(15 downto 0),
      pPulseCount   => SeqTable5(27 downto 24),
      pRepRate      => SeqTable7,
      pNewSeqTable  => NewSeqTable100,
      pUpdatePulse  => UpdatePulse,
      pAckStart     => AckStart100,
      pAckEn        => AckEn,
      pAck          => pAck);

  Overload_1: OverloadDetect
    port map(
      pClock         => Clock,
      pnReset        => nReset,
      pPulse         => Pulse,
      pHVControl     => GlobalConfig(11 downto 9),
      pnAutoReset    => GlobalConfig(14),
      pPulseDisable  => PulseDisable,
      pOverload      => Status(4),
      pOverloadClear => BitPortOut(3));

  -- Sample Trigger signals with 100MHz clock
  Sample : process (Clock, nReset) is
    variable vSapSample: std_logic_vector(2 downto 0);
    variable vTSynchSample: std_logic_vector(2 downto 0);
  begin
      if (nReset ='0') then
        vSapSample := (others => '0');
        vTSynchSample := (others => '0');
        SapPulse <= '0';
        TSynchPulse <= '0';
      elsif (Clock'event and Clock = '1') then
        if vSapSample(2) = '0' and vSapSample(1) = '1' then
          SapPulse <= '1';
        else
          SapPulse <= '0';
        end if;
        if vTSynchSample(2) = '0' and vTSynchSample(1) = '1' then
          TSynchPulse <= '1';
        else
          TSynchPulse <= '0';
        end if;
        vSapSample := vSapSample(1 downto 0) & Pulse(1);
        vTSynchSample := vTSynchSample(1 downto 0) & pTriggerDel;
    end if;
  end process Sample;

  -- Extend SAP and TSYNC pulses to 5us
  StrobeExtender0: StrobeExtender
    generic map(gLfsrBits => 9) -- 9 = 5.12us
    port map(pnReset    => nReset,
             pClk       => Clock,
             pStrobeIn  => SapPulse,
             pStrobeOut => pSap);

  StrobeExtender1: StrobeExtender
    generic map(gLfsrBits => 9) -- 9 = 5.12us
    port map(pnReset    => nReset,
             pClk       => Clock,
             pStrobeIn  => TSynchPulse,
             pStrobeOut => pTSynch);
           
  -- assign pulse outputs
  pPulse <= Pulse;
--  pSap <= Pulse(1);
--  pTSynch <= pTriggerDel;
  pPRxChk <= '1';
  pScreen0 <= '0';
  pScreen1 <= '0';

  -- High voltage control
  pHVStatus <= pHighVoltageOK;
  Status(3) <= pHighVoltageOK;
  HighVoltageEn  <= GlobalConfig(15);
  -- convert to 2's compliment
  -- limit gain range to half scale
  FineGainControl <= '1' & SeqTable1(11 downto 1);

  HVControl <= unsigned(GlobalConfig(11 downto 0)) + 2048;

UltranGen: if cUltran = true generate
  Ultran: UltranPowerSm
    port map (
  	  Clock     => CtrlClock,
  	  nHT_I_OOT => pHTIOOT,
  	  nHT_IS_EN => pHTIsEn,
  	  nHT_V_OOT => pHTVOOT,
  	  nPowerOOT => pnPowerOOT,
  	  Req_HT_ON => HighVoltageEn,
  	  Req_P_ON  => GlobalConfig(12),
  	  nReset => nReset,
  	  Fault => Status(11 downto 8),
  	  Interrupt => open,
  	  nHT_ON => pHighVoltageEn,
  	  nPowerON => pnPowerOn);     
end generate;

nUltranGen: if cUltran = false generate
  pHighVoltageEn <= HighVoltageEn;
  Status(11 downto 8) <= (others => '0');
end generate;

  DACIf: DacSerial
    port map(
      pClock   => CtrlClock,
      pnReset  => nReset,
      pDInA    => FineGainControl,
      pDInAEn  => SeqTableEn(1),
      pDinB    => HVControl,
      pDInBEn  => BitPortOut(0),
      pBusy    => open,
      pDAC_nCS => pDAC_nCS,
      pDAC_SDI => pDAC_SDI,
      pDAC_Clk => pDAC_Clk);

  -- Gain controls
  pExternalGainEn <= SeqTable1(31);
  pInternalGainEn <= not SeqTable1(31);

  -- Connect up gains as 2 bit 2's compliment number
  pFrontMinus40dB <= '1' when (SeqTable3(9 downto 8) = "10") else '0';
  pFrontMinus20dB <= '1' when (SeqTable3(9 downto 8) = "11") else '0';
  pFront0dB       <= '1' when (SeqTable3(9) = '0') else '0';
  pFrontPlus20dB  <= '1' when (SeqTable3(9 downto 8) = "01") else '0';

  -- +20db due to schematic error (really main path control)
  -- schematic error now fixed but leave in to support old boards
  pMpx0dB <= '1' when (SeqTable3(9 downto 8) = "01") else '0';
  pMpx20dB <= '0' when (SeqTable3(9 downto 8) = "01") else '1';

  -- Filter control
  pHighPass <= SeqTable2(26 downto 24);
  pLowPass <= SeqTable2(18 downto 16);

  pBeHighPass <= SeqTable2(10 downto 8);
  pBeLowPass <= SeqTable2(2 downto 0);

  -- Channel control
  pRin47  <= SeqTable3(3);
  pRin100 <= SeqTable3(2);
  pRin270 <= SeqTable3(1);
  pRin470 <= SeqTable3(0);

  pPEChSel <= GlobalConfig(31 downto 24);

  RxChan: DeMux3_8
    port map(
      pDIn  => SeqTable0(18 downto 16),
      pDOut => pRxChSel);

end architecture RTL;
