---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004-2007
--
-- Filename: AdcModelPkg.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Package for ADC Models
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;


package AdcModelPkg is

  -- Type holding signals to ADC Model
  type tToAdcModel is
    record
      TestPattern: integer;
      RepeatTimes: integer;
      Start:       std_ulogic;
      IntTrigger:  std_ulogic;
    end record;

  type tFromAdcModel is
    record
      Done:        std_ulogic;
    end record;

  -- System Monitor ADC control types
  type tSysMon is array (0 to 23) of integer range 0 to 4095;

  -- Procedure to send data from ADC to DSP FPGA
  procedure AdcSendPattern(TestPattern:         in  integer;
                           RepeatTimes:         in  integer;
                           signal ToAdcModel:   out tToAdcModel;
                           signal FromAdcModel: in  tFromAdcModel);

end package AdcModelPkg;



package body AdcModelPkg is


  -- Procedure to do a 32-bit read
  procedure AdcSendPattern (TestPattern:         in  integer;
                            RepeatTimes:         in  integer;
                            signal ToAdcModel:   out tToAdcModel;
                            signal FromAdcModel: in  tFromAdcModel) is
  begin
    ToAdcModel.TestPattern  <= TestPattern;
    ToAdcModel.RepeatTimes  <= RepeatTimes;
    ToAdcModel.Start <= '1';
    wait for 1 ps;
    ToAdcModel.Start <= '0';
  end procedure AdcSendPattern;


end package body AdcModelPkg;