---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: TcgCtrl.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card DSP FPGA
--
-- Design Description:
-- Module to control TCG
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

library work;
use work.DspFpgaPkg.all;


entity TcgCtrl is
  port (-- Local bus signals
        pnReset       : in  std_ulogic;
        pADC_2xClk    : in  std_ulogic;
        pTcgEnable    : in  std_ulogic;
        pNumOfSamples : in  std_logic_vector(13 downto 0);
        pTriggersIn   : in  std_logic_vector(15 downto 0);
        pTriggerNum   : in  std_ulogic;
        pElemSelBits  : in  std_logic_vector(1 downto 0);
        pAScanNum     : in  std_logic_vector(6 downto 0);
        pTcgApplyTime : in  std_logic_vector(3 downto 0);
        pCaptureDone  : in  std_ulogic;
        -- DAC SRAM Signals
        pDACA         : out std_logic_vector(17 downto 0);
        -- Actual DAC Signals
        DACWRT        : out std_ulogic;
        DACCLK        : out std_ulogic;
        Test          : out std_ulogic);
end entity TcgCtrl;


architecture Rtl of TcgCtrl is

  signal Trigger:    std_ulogic;
  signal AddrCount:  std_logic_vector(15 downto 0);
  signal AddrReset:  std_ulogic;
  signal AddrEn:     std_ulogic;

begin

  Test <= AddrReset;
  
  -- Send clock out YUCK!!!
  DACWRT <= pADC_2xClk;
  DACCLK <= pADC_2xClk;

  GenTrigger: process(pnReset, pADC_2xClk)
  begin
    if pnReset = '0' then
      Trigger   <= '0';
    elsif rising_edge(pADC_2xClk) then
      if pTcgEnable = '1' then
        case pTriggerNum is
          when '0' => Trigger      <= pTriggersIn(0);
          when others => Trigger   <= pTriggersIn(15);
        end case;
      else
        -- TCG Operation is disabled
        Trigger <= '0';
      end if;
    end if;
  end process GenTrigger;


  GenAddrEn:  process(pnReset, pADC_2xClk)
    variable vAddrEnCnt: integer range 0 to 15;
  begin
    if pnReset = '0' then
      vAddrEnCnt := 15;
    elsif rising_edge(pADC_2xClk) then
      if vAddrEnCnt = 0 and AddrReset /= '1' then
        AddrEn <= '1';
      else
        AddrEn <= '0';
      end if;

      if Trigger = '1' then
        vAddrEnCnt := conv_integer(unsigned(pTcgApplyTime));
      else  --if AddrReset /= '1' then
        if vAddrEnCnt /= 0 then
          vAddrEnCnt := (vAddrEnCnt - 1) mod 16;
        else
          vAddrEnCnt := conv_integer(unsigned(pTcgApplyTime));
        end if;
      end if;
    end if;
  end process GenAddrEn;



  GenAddrCount: process(pnReset, pADC_2xClk)
  begin
    if pnReset = '0' then
      AddrCount <= (others => '0');
      AddrReset <= '1';
    elsif rising_edge(pADC_2xClk) then
      if Trigger = '1' then
        AddrReset <= '0';
      elsif pCaptureDone = '1' then
        AddrReset <= '1';
      end if;

      -- Increment address on each 'AddrEn' when 'AddrReset' is not set
      if AddrReset /= '1' then
        if AddrEn = '1' then
          AddrCount <= (unsigned(AddrCount) + 1) and "1111111111111111";
        end if;
      else  -- AddrReset = '1'
        AddrCount <= "0000000000000000";
      end if;
    end if;
  end process GenAddrCount;


  GenpDACA: process(pnReset, pADC_2xClk)  --process(pElemSelBits, AddrCount, pAScanNum)
  begin
    if pnReset = '0' then
      pDACA <= (others => '0');
    elsif rising_edge(pADC_2xClk) then
      case pElemSelBits is
        when "00" => -- 1 TCG curve in TCG SRAM
          pDACA <= "00" & AddrCount(15 downto 0);
        when "01" => -- 32 TCG curves in TCG SRAM
          pDACA <= pAScanNum(4 downto 0) & AddrCount(12 downto 0);
        when "10" => -- 64 TCG curves in TCG SRAM
          pDACA <= pAScanNum(5 downto 0) & AddrCount(11 downto 0);
        when others => -- 128 TCG curves in TCG SRAM
          pDACA <= pAScanNum(6 downto 0) & AddrCount(10 downto 0);
      end case;
    end if;
  end process GenpDACA;


end Rtl;

