---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: SystemFpgaTop.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 System FPGA
--
-- Design Description:
-- Top Level for NDTS System FPGA
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

library UNISIM;
use UNISIM.vcomponents.all;

entity SystemFpgaTop is
  port (-- Local bus
        nLRESET    : in    std_ulogic;
        LCLKA      : in    std_ulogic;
        LCLKB      : in    std_ulogic;
        LWnR       : inout std_logic;
        LD         : inout std_logic_vector(31 downto 0);
        DP         : inout std_logic_vector(3 downto 0);
        LA         : inout std_logic_vector(31 downto 2);
        nADS       : inout std_logic;
        nBLAST     : inout std_logic;
        nREADY     : inout std_logic;
        nWAIT      : inout std_logic;
        nBTERM     : inout std_logic;
        nLBE       : inout std_logic_vector(3 downto 0);
        BREQi      : inout std_ulogic; -- was out
        BREQo      : in    std_ulogic;
        nDREQ0     : out   std_ulogic;
        nDREQ1     : out   std_ulogic;
        nDACK0     : in    std_ulogic;
        nDACK1     : in    std_ulogic;
        nLINTi     : out   std_ulogic;
        nLINTo     : in    std_ulogic;
        nLSERR     : in    std_ulogic;
        nBIGEND    : out   std_ulogic;
        LHOLD      : in    std_ulogic;
        LHOLDA     : inout std_ulogic; -- was out
        USERi      : out   std_ulogic;
        USERo      : in    std_ulogic;
        nEOT       : in    std_ulogic;
        nCCS       : out   std_ulogic;
        nPMEIN     : out   std_ulogic;
        GPIO       : inout std_logic_vector(3 downto 0);
        -- DSP FPGA connections
        DspCClk    : out   std_ulogic;
        DspDone    : in    std_ulogic;
        nDspProg   : out   std_ulogic;
        DspDIn     : out   std_ulogic;
        nDspInit   : in    std_ulogic;
        -- EEPROM connections
        EEClk      : out   std_ulogic;
        EEOut      : in    std_ulogic;
        EEIn       : out   std_ulogic;
        nEECs      : out   std_ulogic;
        -- System Monitor
        nSysMonCs  : out   std_logic_vector(2 downto 0);
        SysMonSClk : out   std_ulogic;
        SysMonDIn  : out   std_ulogic;
        SysMonDOut : in    std_logic;
        TempSnsCe  : out   std_ulogic;
        TempSnsSClk: out   std_ulogic;
        TempSnsSDo : in    std_ulogic;
        SysMonD    : out   std_logic_vector(4 downto 0);
        SysMonOK   : out   std_ulogic;
        -- Misc IO
        SysLED     : out   std_ulogic;
        DbugD      : inout std_logic_vector(15 downto 8);
        BuzzP      : out   std_logic_vector(11 downto 0);
        BuzzN      : out   std_logic_vector(11 downto 0));
end entity SystemFpgaTop;


architecture Str of SystemFpgaTop is

  component SysLBusInterface
    port (-- Local bus
          nReset            : in  std_ulogic;
          LClk              : in  std_ulogic;
          LWnR              : in  std_ulogic;
          LDIn              : in  std_logic_vector(31 downto 0);
          LDOut             : out std_logic_vector(31 downto 0);
          nLDOe             : out std_ulogic;
          LAin              : in  std_logic_vector(31 downto 2);
          nAds              : in  std_ulogic;
          nBLast            : in  std_ulogic;
          nReady            : out std_ulogic;
          nBTerm            : out std_ulogic;
          LHold             : in  std_ulogic;
          LHoldA            : out std_ulogic;
          BReqi             : out std_ulogic;
          Test			        : out std_ulogic; 
          -- DSP FPGA configuration
          DspConfigData     : out std_logic_vector(31 downto 0);
          DspConfigWr       : out std_ulogic;
          DspConfigStart    : out std_ulogic;
          DspConfigDone     : in  std_ulogic;
          DspConfigBusy     : in  std_ulogic;
          -- System Monitor
          SysMonitorEn      : out std_ulogic;
          SysMonitorSel     : in  std_logic_vector(4 downto 0);
          SysMonitorVal     : in  std_logic_vector(11 downto 0);
          SysMonitorValWr   : in  std_ulogic;
          SysMonitorMin     : out std_logic_vector(11 downto 0);
          SysMonitorMax     : out std_logic_vector(11 downto 0);
          SysMonitorTempVal : in  std_logic_vector(9 downto 0);
          SysMonitorTempMin : out std_logic_vector(9 downto 0);
          SysMonitorTempMax : out std_logic_vector(9 downto 0);
          UnderRangeFlags   : in  std_logic_vector(24 downto 0);
          OverRangeFlags    : in  std_logic_vector(24 downto 0);
          LedEnSel          : in  std_logic_vector(2 downto 0);
          UnderRangeEn      : out std_logic_vector(24 downto 0);
          OverRangeEn       : out std_logic_vector(24 downto 0));
  end component;

  component FPGAConfig
    port (-- Local bus
          nReset      : in  std_ulogic;
          LClk        : in  std_ulogic;
          -- Register interface signals
          ConfigData  : in  std_logic_vector(31 downto 0);
          ConfigWr    : in  std_ulogic;
          ConfigStart : in  std_ulogic;
          ConfigDone  : out std_ulogic;
          ConfigBusy  : out std_ulogic;
          -- FPGA signals
          CClk        : out std_ulogic;
          Done        : in  std_ulogic;
          nProg       : out std_ulogic;
          DIn         : out std_ulogic;
          nInit       : in  std_ulogic);
  end component;

  component SystemMonitor
    port (-- Local bus
          nReset             : in  std_ulogic;
          LClk               : in  std_ulogic;
          -- Register interface signals
          SysMonitorEn       : in  std_ulogic;
          SysMonitorSel      : out std_logic_vector(4 downto 0);
          SysMonitorVal      : out std_logic_vector(11 downto 0);
          SysMonitorValWr    : out std_ulogic;
          SysMonitorMin      : in  std_logic_vector(11 downto 0);
          SysMonitorMax      : in  std_logic_vector(11 downto 0);
          SysMonitorTempVal  : out std_logic_vector(9 downto 0);
          SysMonitorTempMin  : in  std_logic_vector(9 downto 0);
          SysMonitorTempMax  : in  std_logic_vector(9 downto 0);
          UnderRangeFlags    : out std_logic_vector(24 downto 0);
          OverRangeFlags     : out std_logic_vector(24 downto 0);
          LedEnSel           : out std_logic_vector(2 downto 0);
          UnderRangeEn       : in  std_logic_vector(24 downto 0);
          OverRangeEn        : in  std_logic_vector(24 downto 0);
          -- System Monitor ADC signals
          nSysMonCs          : out   std_logic_vector(2 downto 0);
          SysMonSClk         : out   std_ulogic;
          SysMonDIn          : out   std_ulogic;
          SysMonDOut         : in    std_ulogic;
          TempSnsCe          : out   std_ulogic;
          TempSnsSClk        : out   std_ulogic;
          TempSnsSDo         : in    std_ulogic;
          SysMonD            : out   std_logic_vector(4 downto 0);
          SysMonOK           : out   std_ulogic);
  end component;

  signal nReset : std_ulogic;
  signal LClk   : std_ulogic;
  signal LDOut  : std_logic_vector(31 downto 0);
  signal nLDOe  : std_ulogic;

  -- Register interface signals
  signal DspConfigData      : std_logic_vector(31 downto 0);
  signal DspConfigWr        : std_ulogic;
  signal DspConfigStart     : std_ulogic;
  signal DspConfigDone      : std_ulogic;
  signal DspConfigBusy      : std_ulogic;

  signal SysMonitorEn       : std_ulogic;
  signal SysMonitorSel      : std_logic_vector(4 downto 0);
  signal SysMonitorVal      : std_logic_vector(11 downto 0);
  signal SysMonitorValWr    : std_ulogic;
  signal SysMonitorMin      : std_logic_vector(11 downto 0);
  signal SysMonitorMax      : std_logic_vector(11 downto 0);
  signal SysMonitorTempVal  : std_logic_vector(9 downto 0);
  signal SysMonitorTempMin  : std_logic_vector(9 downto 0);
  signal SysMonitorTempMax  : std_logic_vector(9 downto 0);
  signal UnderRangeFlags    : std_logic_vector(24 downto 0);
  signal OverRangeFlags     : std_logic_vector(24 downto 0);
  signal LedEnSel           : std_logic_vector(2 downto 0);
  signal UnderRangeEn       : std_logic_vector(24 downto 0);
  signal OverRangeEn        : std_logic_vector(24 downto 0);

  signal Test : std_ulogic;

begin

  nReset <= nLRESET;

  IBUFG0: IBUFG
    port map(I   => LCLKA,
             O   => LClk);

  -- Tristate data i/o
  LD <= LDOut when nLDOe = '0' else (others => 'Z');

  -- Tie off unused LBUS outputs
  LWnR <= 'Z';
  DP <= (others => 'Z');
  LA <= (others => 'Z');
  nADS <= 'Z';
  nBLAST <= 'Z';
  nWAIT <= 'Z';
  nLBE  <= (others => 'Z');

  nBIGEND <= 'Z';
  nCCS <= '1'; -- 'Z';
  USERi <= 'Z';
  nPMEIN <= 'Z';
  nDREQ0 <= 'Z';
  nDREQ1 <= 'Z';
  nLINTi <= 'Z';

  -- LBus interface
  LBus: SysLBusInterface
    port map (-- Local bus
              nReset            => nReset,
              LClk              => LClk,
              LWnR              => LWnR,
              LDIn              => LD,
              LDOut             => LDOut,
              nLDOe             => nLDOe,
              LAin              => LA,
              nAds              => nADS,
              nBLast            => nBLAST,
              nReady            => nREADY,
              nBTerm            => nBTERM,
              LHold             => LHOLD,
              LHoldA            => LHOLDA,
              BReqi             => BREQi,
              Test			        => Test,
              -- DSP FPGA configuration
              DspConfigData     => DspConfigData,
              DspConfigWr       => DspConfigWr,
              DspConfigStart    => DspConfigStart,
              DspConfigDone     => DspConfigDone,
              DspConfigBusy     => DspConfigBusy,
              -- System Monitor
              SysMonitorEn      => SysMonitorEn,
              SysMonitorSel     => SysMonitorSel,
              SysMonitorVal     => SysMonitorVal,
              SysMonitorValWr   => SysMonitorValWr,
              SysMonitorMin     => SysMonitorMin,
              SysMonitorMax     => SysMonitorMax,
              SysMonitorTempVal => SysMonitorTempVal,
              SysMonitorTempMin => SysMonitorTempMin,
              SysMonitorTempMax => SysMonitorTempMax,
              UnderRangeFlags   => UnderRangeFlags,
              OverRangeFlags    => OverRangeFlags,
              LedEnSel          => LedEnSel,
              UnderRangeEn      => UnderRangeEn,
              OverRangeEn       => OverRangeEn);

  -- DSP FPGA configuration
  DSPConfig: FPGAConfig
    port map (-- Local bus
              nReset      => nReset,
              LClk        => LClk,
              -- Register interface signals
              ConfigData  => DspConfigData,
              ConfigWr    => DspConfigWr,
              ConfigStart => DspConfigStart,
              ConfigDone  => DspConfigDone,
              ConfigBusy  => DspConfigBusy,
              -- FPGA signals
              CClk        => DspCClk,
              Done        => DspDone,
              nProg       => nDspProg,
              DIn         => DspDIn,
              nInit       => nDspInit);

  -- System Monitor
  SysMon: SystemMonitor
    port map (-- Local bus
              nReset             => nReset,
              LClk               => LClk,
              -- Register interface signals
              SysMonitorEn       => SysMonitorEn,
              SysMonitorSel      => SysMonitorSel,
              SysMonitorVal      => SysMonitorVal,
              SysMonitorValWr    => SysMonitorValWr,
              SysMonitorMin      => SysMonitorMin,
              SysMonitorMax      => SysMonitorMax,
              SysMonitorTempVal  => SysMonitorTempVal,
              SysMonitorTempMin  => SysMonitorTempMin,
              SysMonitorTempMax  => SysMonitorTempMax,
              UnderRangeFlags    => UnderRangeFlags,
              OverRangeFlags     => OverRangeFlags,
              LedEnSel           => LedEnSel,
              UnderRangeEn       => UnderRangeEn,
              OverRangeEn        => OverRangeEn,
              -- System Monitor ADC signals
              nSysMonCs          => nSysMonCs,
              SysMonSClk         => SysMonSClk,
              SysMonDIn          => SysMonDIn,
              SysMonDOut         => SysMonDOut,
              TempSnsCe          => TempSnsCe,
              TempSnsSClk        => TempSnsSClk,
              TempSnsSDo         => TempSnsSDo,
              SysMonD            => SysMonD,
              SysMonOK           => SysMonOK);

  -- EEPROM interface
  EEClk <= '0';
  EEIn <= '0';
  nEECs <= '1';

  -- Turn on Sys LED when we come out of reset
  SysLED <= not nLRESET;

  -- Misc
  DBugD <= (8 => nADS,
            9 => nREADY,
            10 => nWAIT,
            11 => nLBE(0),
            12 => Test,
            13 => nBLAST,
            14 => BREQi,
            15 => LHOLDA,
            others => '0');

  BuzzP(7 downto 0) <= (others => 'Z');
  BuzzN(7 downto 0) <= (others => 'Z');

  Buzz: for i in 8 to 11 generate
    OBUFDS_inst : OBUFDS
      generic map ( IOSTANDARD => "LVDS_25")
      port map (O => BuzzP(i),
                OB => BuzzN(i),
                I => '0');
  end generate;

end architecture Str;
