---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2004
--
-- Filename: SimCtrl010.vhd
-- Language: VHDL '93
-- Project:  Digitiser Card FPGAs
--
-- Design Description:
--Simulation Control file (010) for Digitiser card testbench
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
use work.AdcModelPkg.all;


entity SimCtrl is
  port(ToBusModel   : out tToBusModel;
       FromBusModel : in tFromBusModel;
       ToAdcModel   : out tToAdcModel;
       FromAdcModel : in tFromAdcModel);
end entity SimCtrl;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00500000#;
  constant cSysCommandReg: integer := 16#00500014#;
  constant cSysStatusReg:  integer := 16#00500014#;

  constant cPerCheckReg:   integer := 16#00500400#;

  constant cGateStartStop:  integer := 16#00500438#;
  constant cGateAttributes: integer := 16#0050043C#;
  constant cGateSetup:      integer := 16#00500440#;

  -- Define the base of the system SRAM
  constant cSysSramBase:   integer := 16#00400000#;

  -- Define the base of the sample SRAM
  constant cSampleSramBase:   integer := 16#00000000#;


begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Doing shortened FPGA configuration to reduce simulation time"));
    writeline (OUTPUT, vLine);

    -- Program the FPGAs - actually skip full configuration simulation
    LBusWrite(cSysSramBase, 16#DEADBEEF#, ToBusModel, FromBusModel);
    LBusWrite(cSysCommandReg, 16#00000011#, ToBusModel, FromBusModel);

    -- Try to access the check register, should be delayed until FPGAs have been configured
    LBusWrite(cSysCheckReg, 16#01234567#, ToBusModel, FromBusModel);
    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FEDCBA98# then
      write (vLine, string'("Testbench: Error - Expected 0xFEDCBA98 from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    else
      write (vLine, string'("Testbench: Shortened FPGA configuration complete"));
      writeline (OUTPUT, vLine);
    end if;

    -- Setup values for the number of samples
    LBusWrite(16#00500258#, 16#0000019F#, ToBusModel, FromBusModel);

    -- Set A-Scan reprate
    LBusWrite(16#00500410#, 16#00000064#, ToBusModel, FromBusModel);

    -- Set A-Scans per B-Scan = 5
    LBusWrite(16#00500414#, 16#00000004#, ToBusModel, FromBusModel);

    -- Set pulse width
    LBusWrite(16#00500408#, 16#00000010#, ToBusModel, FromBusModel);

    -- Select internal trigger
    LBusWrite(16#00500404#, 16#00010000#, ToBusModel, FromBusModel);


    wait for 2 us;

    -- Manually trigger B-Scan
    LBusWrite(16#0050041C#, 16#80000000#, ToBusModel, FromBusModel);

    wait for 50 us;

    -- Manually trigger B-Scan
    LBusWrite(16#0050041C#, 16#80000000#, ToBusModel, FromBusModel);

    wait for 50 us;

    -- Enable free running mode
    LBusWrite(16#0050041C#, 16#20000226#, ToBusModel, FromBusModel);

    wait for 100 us;

    -- Disable free running mode
    LBusWrite(16#0050041C#, 16#00000000#, ToBusModel, FromBusModel);

    wait for 50 us;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;