---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2008
--
-- Filename: SDRAMIf.vhd
-- Language: VHDL '93
-- Project:  NDTS2100 DSP FPGA
--
-- Design Description:
-- Top Level for NDTS2100 DDR2 SDRAM interface
---------------------------------------------------------------------------
library IEEE;
use IEEE.Std_Logic_1164.all;
library UNISIM;
use UNISIM.vcomponents.all;

entity SDRAMIfTb is
end SDRAMIfTb;

architecture TestBench of SDRAMIfTb is

  component SDRAMIf
      port (ClkIn     : in    std_ulogic;
          nReset    : in    std_ulogic;
          MemClkOut : out   std_ulogic;
          -- User i/o
          uDIn      : in    std_logic_vector(127 downto 0);
          uDMask    : in    std_logic_vector(15 downto 0);
          uDOut     : out   std_logic_vector(127 downto 0);
          uAddr     : in    std_logic_vector(30 downto 5);
          uWr       : in    std_ulogic;
          uWrPop    : out   std_ulogic;
          uRd       : in    std_ulogic;
          uRdPush   : out   std_ulogic;
          uAck      : out   std_ulogic;
          -- SDRAM
          SR_Ck     : out   std_logic_vector(1 downto 0);
          nSR_Ck    : out   std_logic_vector(1 downto 0);
          SR_Cke    : out   std_logic_vector(1 downto 0);
          SR_Dq     : inout std_logic_vector(63 downto 0);
          SR_Dqs    : inout std_logic_vector(7 downto 0);
          nSR_Dqs   : inout std_logic_vector(7 downto 0);
          SR_DM     : out   std_logic_vector(7 downto 0);
          SR_A      : out   std_logic_vector(13 downto 0);
          SR_Ba     : out   std_logic_vector(2 downto 0);
          nSR_We    : out   std_ulogic;
          nSR_Ras   : out   std_ulogic;
          nSR_Cas   : out   std_ulogic;
          SR_ODT    : out   std_logic_vector(1 downto 0);
          nSR_S     : out   std_logic_vector(1 downto 0);
          SR_SCL    : out   std_ulogic;
          SR_SDA    : in    std_ulogic;
          SR_SA     : out   std_logic_vector(1 downto 0);
          RstDqsDiv : inout std_ulogic);
  end component;

  component ddr2_sodimm
    port (reset_n : in    std_ulogic;
          ck      : in    std_logic_vector(1 downto 0);
          ck_n    : in    std_logic_vector(1 downto 0);
          cke     : in    std_logic_vector(1 downto 0);
          s_n     : in    std_logic_vector(1 downto 0);
          ras_n   : in    std_ulogic;
          cas_n   : in    std_ulogic;
          we_n    : in    std_ulogic;
          ba      : in    std_logic_vector(2 downto 0);
          addr    : in    std_logic_vector(13 downto 0);
          odt     : in    std_logic_vector(1 downto 0);
          dm      : in    std_logic_vector(7 downto 0);
          dqs     : inout std_logic_vector(7 downto 0);
          dqs_n   : inout std_logic_vector(7 downto 0);
          dq      : inout std_logic_vector(63 downto 0);
          scl     : in    std_ulogic;
          sa      : in    std_logic_vector(2 downto 0);
          sda     : inout std_ulogic);
  end component;

  signal ClkIn     : std_ulogic := '0';
  signal nReset    : std_ulogic;
  signal MemClkOut : std_ulogic;
  -- User i/o
  signal D1        : std_logic_vector(127 downto 0);
  signal D2        : std_logic_vector(127 downto 0);
  signal uDIn      : std_logic_vector(127 downto 0);
  signal uDMask    : std_logic_vector(15 downto 0);
  signal uDOut     : std_logic_vector(127 downto 0);
  signal uAddr     : std_logic_vector(30 downto 5);
  signal uWr       : std_ulogic;
  signal uWrPop    : std_ulogic;
  signal uRd       : std_ulogic;
  signal uRdPush   : std_ulogic;
  signal uAck      : std_ulogic;
  -- SDRAM
  signal SR_Ck     : std_logic_vector(1 downto 0);
  signal nSR_Ck    : std_logic_vector(1 downto 0);
  signal SR_Cke    : std_logic_vector(1 downto 0);
  signal SR_Dq     : std_logic_vector(63 downto 0);
  signal SR_Dqs    : std_logic_vector(7 downto 0);
  signal nSR_Dqs   : std_logic_vector(7 downto 0);
  signal SR_DM     : std_logic_vector(7 downto 0);
  signal SR_A      : std_logic_vector(13 downto 0);
  signal SR_Ba     : std_logic_vector(2 downto 0);
  signal nSR_We    : std_ulogic;
  signal nSR_Ras   : std_ulogic;
  signal nSR_Cas   : std_ulogic;
  signal SR_ODT    : std_logic_vector(1 downto 0);
  signal nSR_S     : std_logic_vector(1 downto 0);
  signal SR_SCL    : std_ulogic;
  signal SR_SDA    : std_ulogic;
  signal SR_SA     : std_logic_vector(2 downto 0);
  signal RstDqsDiv : std_ulogic;

begin
  ClkIn <= not ClkIn after 7.576 ns;

  process
  begin
    D1 <= (others => '0');
    uDMask <= (others => '0');
    uAddr <= (others => '0');
    uWr <= '0';
    uRd <= '0';

    nReset <= '0';
    wait for 50 ns;
    nReset <= '1';
    wait for 250 us;
    wait until rising_edge(MemClkOut);
    uWr <= '1';
    D1(31 downto 0) <= x"AA55AA55";
    uDMask(3 downto 0) <= "1111";
    
    while uWrPop'delayed = '0' loop
      wait until rising_edge(MemClkOut);
    end loop;
    D1 <= (others => '1');
    uDMask <= "1111000000000000";

    while uAck'delayed = '0' loop
      wait until rising_edge(MemClkOut);
    end loop;
    uWr <= '0';
      
    wait;
  end process;     

  DFF : process (MemClkOut) is
  begin
    if rising_edge(MemClkOut) then
      D2 <= D1;
      uDIn <= D2;
    end if;
  end process DFF;    

  U1 : SDRAMIf
	port map (ClkIn => ClkIn,
		        nReset => nReset,
		        MemClkOut => MemClkOut,
		        uDIn => uDIn,
		        uDMask => uDMask,
		        uDOut => uDOut,
		        uAddr => uAddr,
		        uWr => uWr,
		        uWrPop => uWrPop,
		        uRd => uRd,
		        uRdPush => uRdPush,
		        uAck => uAck,
		        SR_Ck => SR_Ck,
		        nSR_Ck => nSR_Ck,
		        SR_Cke => SR_Cke,
		        SR_Dq => SR_Dq,
		        SR_Dqs => SR_Dqs,
		        nSR_Dqs => nSR_Dqs,
		        SR_DM => SR_DM,
		        SR_A => SR_A,
		        SR_Ba => SR_Ba,
		        nSR_We => nSR_We,
		        nSR_Ras => nSR_Ras,
		        nSR_Cas => nSR_Cas,
		        SR_ODT => SR_ODT,
		        nSR_S => nSR_S,
		        SR_SCL => SR_SCL,
		        SR_SDA => SR_SDA,
		        SR_SA => SR_SA(1 downto 0),
		        RstDqsDiv => RstDqsDiv);

	-- DDR2 RAM
	U2: ddr2_sodimm
		port map (reset_n => nReset,
		          ck      => SR_Ck,
		          ck_n    => nSR_Ck,
		          cke     => SR_Cke,
		          s_n     => nSR_S,
		          ras_n   => nSR_Ras,
		          cas_n   => nSR_Cas,
		          we_n    => nSR_We,
		          ba      => SR_Ba,
		          addr    => SR_A,
		          odt     => SR_ODT,
		          dm      => SR_Dm,
		          dqs     => SR_Dqs,
		          dqs_n   => nSR_Dqs,
		          dq      => SR_Dq,
		          scl     => SR_SCL,
		          sa      => SR_SA,
		          sda     => SR_SDA);
		      

end TestBench;
