---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2007
--
-- Filename: SimCtrl001.vhd
-- Language: VHDL '93
-- Project:  NDTS2100
--
-- Design Description:
-- Simulation Control file to test basic System FPGA bus access and DSP FPGA configuration
---------------------------------------------------------------------------


library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;
use std.textio.all;

library work;
use work.LocalBusModelPkg.all;
--use work.AdcModelPkg.all;


architecture Test of SimCtrl is

  -- Define some system register addresses
  constant cSysCheckReg:   integer := 16#00300000#;
  constant cSysControlReg: integer := 16#00300004#;
  constant cSysFPGACfgReg: integer := 16#00300008#;
  constant cSysMonCtrlReg: integer := 16#00300010#;

  constant cXC3S2000ConfigSize  : integer := (7673024 / 32); -- (bits / 32) = DWORDS

begin

  -- Main Simulation Control process
  Main: process
    variable vRData: integer;
    variable vWData: integer;
    variable vTestFail: boolean;
    variable vLine: Line;
    variable vDone: boolean;
    variable vBurstData: tBurstData;
    variable vReadBurstData: tBurstData;

  begin

    -- Initialise the test fail flag
    vTestFail := false;

    -- Initialise the Bus Model (bus clock = 66 MHz)
    BusInit(15.152 ns, ToBusModel, FromBusModel);

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing System Check Register"));
    writeline (OUTPUT, vLine);

    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FFFFFFFF# then
      write (vLine, string'("Testbench: Error - Expected 0xFFFFFFFF from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cSysCheckReg, 16#5555AAAA#, ToBusModel, FromBusModel);
    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#AAAA5555# then
      write (vLine, string'("Testbench: Error - Expected 0xAAAA5555 from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    LBusWrite(cSysCheckReg, 16#00000001#, ToBusModel, FromBusModel);
    LBusRead(cSysCheckReg, vRData, ToBusModel, FromBusModel);
    if vRData /= 16#FFFFFFFE# then
      write (vLine, string'("Testbench: Error - Expected 0xFFFFFFFE from System Check register"));
      writeline (OUTPUT, vLine);
      vTestFail := true;
    end if;

    write (vLine, string'("Testbench: System Check Register tests complete"));
    writeline (OUTPUT, vLine);

    -- Write description of test to output
    write (vLine, string'("Testbench: Testing Accesses to System SRAM"));
    writeline (OUTPUT, vLine);

    -- Program the FPGAs (or at least write the correct number of bytes
    write (vLine, string'("Testbench: DSP FPGA configuration test (this will take over 500 ms)"));
    writeline (OUTPUT, vLine);

    -- Start the FPGA programming sequence
    LBusWrite(cSysControlReg, 16#00000001#, ToBusModel, FromBusModel);
    -- loop while busy bit set
    LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
    while vRData = 16#80000000# loop
      LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
    end loop;

    -- Write dummy config data to System SRAM (checked by testbench)
    for Count in 0 to 9 loop  -- First 10 config values for DSP FPGA
      vWData := Count;
      LBusWrite(cSysFPGACfgReg, vWData, ToBusModel, FromBusModel);
      -- loop while busy bit set
      LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      while vRData = 16#80000000# loop
        LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      end loop;
    end loop;

    for Count in 10 to cXC3S2000ConfigSize-11 loop
      vWData := 16#AA55BB66#;
      LBusWrite(cSysFPGACfgReg, vWData, ToBusModel, FromBusModel);
      -- loop while busy bit set
      LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      while vRData = 16#80000000# loop
        LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      end loop;
    end loop;

    for Count in cXC3S2000ConfigSize-10 to cXC3S2000ConfigSize-1 loop  -- Last 10 config values for DSP FPGA
      vWData := Count - (cXC3S2000ConfigSize-80);
      LBusWrite(cSysFPGACfgReg, vWData, ToBusModel, FromBusModel);
      -- loop while busy bit set
      LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      while vRData = 16#80000000# loop
        LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
      end loop;
    end loop;

    -- Wait for Done Bit
    LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
    while vRData /= 16#40000000# loop
      LBusRead(cSysControlReg, vRData, ToBusModel, FromBusModel);
    end loop;

    write (vLine, string'("Testbench: DSP FPGA configuration test complete"));
    writeline (OUTPUT, vLine);

    wait for 100 ns;

    -- Stop the simulation and report pass/fail
    if vTestFail then
      report "Testbench: Simulation 001 completed - FAIL"
      severity failure;
    else
      report "Testbench: Simulation 001 completed - PASS"
      severity failure;
    end if;

    wait;

  end process main;


end architecture Test;