---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: BusArbiter.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Local Bus Arbiter for Pulser Receiver Card (PRx) System FPGA
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity BusArbiter is
  port(
    pnReset  : in  std_ulogic;
    pClock   : in  std_ulogic;  -- same Local Bus Clock as sent to PLX chip
    pHOLD_1  : in  std_ulogic;
    pHOLD_2  : in  std_ulogic;
    pHOLDA_1 : out std_ulogic;
    pHOLDA_2 : out std_ulogic);
end BusArbiter;

architecture RTL of BusArbiter is

  type   tControlState is (sIdle, sHold1, sHold2);
  signal CState : tControlState;

begin

  ControlFSM : process(pnReset, pClock)
  begin
    if pnReset = '0' then
      CState   <= sIdle;
      pHOLDA_1 <= '0';
      pHOLDA_2 <= '0';
    elsif rising_edge(pClock) then
      pHOLDA_1 <= '0';
      pHOLDA_2 <= '0';
      case CState is

        when sIdle =>
          if pHOLD_1 = '1' then
            pHOLDA_1 <= '1';
            CState   <= sHold1;
          elsif pHOLD_2 = '1' then
            pHOLDA_2 <= '1';
            CState   <= sHold2;
          else
            CState <= sIdle;
          end if;

        when sHold1 =>
          if pHOLD_1 = '1' then
            pHOLDA_1 <= '1';
            CState   <= sHold1;
          elsif pHOLD_2 = '1' then
            pHOLDA_2 <= '1';
            CState   <= sHold2;
          else
            CState <= sIdle;
          end if;

        when sHold2 =>
          if pHOLD_2 = '1' then
            pHOLDA_2 <= '1';
            CState   <= sHold2;
          elsif pHOLD_1 = '1' then
            pHOLDA_1 <= '1';
            CState   <= sHold1;
          else
            CState <= sIdle;
          end if;
          
        when others =>
          CState <= sIdle;

      end case;
    end if;
  end process ControlFSM;

end architecture RTL;

