---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: CheckReg.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- check register - just inverts data
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.std_logic_1164.all;

entity CheckReg is
  port(
    pClock   : in  std_ulogic;
    pnReset  : in  std_ulogic;
    pnWE     : in  std_ulogic;
    pnCS     : in  std_ulogic;
    pDataIn  : in  std_logic_vector(31 downto 0);
    pDataOut : out std_logic_vector(31 downto 0));
end CheckReg;

architecture RTL of CheckReg is

  signal DataBuffer : std_logic_vector(31 downto 0);

begin

  process (pClock, pnReset)
  begin
    if pnReset = '0' then
      DataBuffer <= (others => '0');
    elsif rising_edge(pClock) then
      if pnCS = '0' and pnWE = '0' then
        DataBuffer <= pDataIn;
      end if;
    end if;
  end process;

  pDataOut <= not DataBuffer;

end architecture RTL;

