JDF G
// Created by Project Navigator ver 1.0
PROJECT PRx Control FPGA
DESIGN controlfpga
DEVFAM spartan2
DEVFAMTIME 0
DEVICE xc2s200
DEVICETIME 0
DEVPKG fg456
DEVPKGTIME 0
DEVSPEED -5
DEVSPEEDTIME 0
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE ..\source\ControlROM\CTRL_ROM.VHD
SOURCE ..\source\CtrlSequenceTable.vhd
SOURCE ..\source\ControlFpgaTop.vhd
SOURCE ..\source\CtrlControl.vhd
SOURCE ..\source\CtrlKCPSM.vhd
SOURCE ..\source\ControlFpga_pkg.vhd
SOURCE ..\..\common\source\UAT.vhd
SOURCE ..\..\common\source\bbfifo_16x8.vhd
SOURCE ..\..\common\source\DPBRAM32x256.vhd
SOURCE ..\..\common\source\kcpsm.vhd
SOURCE ..\..\common\source\kcuart_rx.vhd
SOURCE ..\..\common\source\kcuart_tx.vhd
SOURCE ..\..\common\source\OutPort32.vhd
SOURCE ..\..\common\source\UAR.vhd
SOURCE ..\..\common\source\uart_rx.vhd
SOURCE ..\..\common\source\uart_tx.vhd
SOURCE ..\..\common\source\AddressCounter.vhd
SOURCE ..\source\DacSerial.vhd
SOURCE ..\source\DeMux3_8.vhd
SOURCE ..\source\PulseGen.vhd
SOURCE ..\source\SyncPulse.vhd
SOURCE ..\source\CtrlBitIO.vhd
SOURCE ..\..\common\source\StrobeExtender.vhd
SOURCE ..\source\OverloadDetect.vhd
SOURCE ..\..\common\source\InPort32.vhd
DEPASSOC controlfpgatop ..\constraints\ControlFPGA.ucf
[Normal]
xilxNgdbld_AUL=xstvhd, spartan2, Implementation.t_ngdbuild, 1164060590, True
xilxPAReffortLevel=xstvhd, spartan2, Implementation.t_par, 1118914478, High
xilxPreTrceRpt=xstvhd, spartan2, Implementation.t_preRouteTrce, 1122407747, Error Report
xilxPreTrceRptLimit=xstvhd, spartan2, Implementation.t_preRouteTrce, 1122405321, 50
xilxPreTrceRptTiming=xstvhd, spartan2, Implementation.t_preRouteTrce, 1122405407, 50
[STATUS-ALL]
controlfpgatop.bitgenGroup=OK,1166108065
[STRATEGY-LIST]
Normal=True
