---------------------------------------------------------------------------
-- NDT Solutions Ltd. Proprietary Information
-- Company Confidential
-- Copyright 2005
--
-- Filename: SysSequenceTable.vhd
-- Language: VHDL '93
-- Project:  Pulse Receive Card System FPGA
--
-- Design Description:
-- Implement dual port RAM for sequence table.
-- LBus on one side pico-blaze on the other
--
---------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.Std_Logic_Arith.all;

use work.SystemFPGA_pkg.all;

entity SysSequenceTable is
  port (
    pnReset       : in  std_ulogic;
    pClock        : in  std_ulogic;
    pnWE          : in  std_ulogic;
    pnCS          : in  std_ulogic;
    pAddress      : in  std_logic_vector(7 downto 0);
    pDataIn       : in  std_logic_vector(31 downto 0);
    pDataOut      : out std_logic_vector(31 downto 0);
	  pSeqTableAddr : in  std_logic_vector(7 downto 0);
    pSeqTableOut  : out std_logic_vector(31 downto 0));
end SysSequenceTable;


architecture RTL of SysSequenceTable is

  component DPBRAM32x256
    port (
      pnReset  : in  std_ulogic;
      pClock   : in  std_ulogic;
      AddressA : in  std_logic_vector(7 downto 0);
      AddressB : in  std_logic_vector(7 downto 0);
      DataInA  : in  std_logic_vector(31 downto 0);
      DataInB  : in  std_logic_vector(31 downto 0);
      WriteEnA : in  std_ulogic;
      WriteEnB : in  std_ulogic;
      DataOutA : out std_logic_vector(31 downto 0);
      DataOutB : out std_logic_vector(31 downto 0));
  end component;
  
  signal B_DataWrite : std_logic_vector(31 downto 0);
  signal B_WE        : std_ulogic;
  signal A_WE        : std_ulogic;

begin

  A_WE <= '1' when (pnCS = '0' and pnWE = '0') else '0';

  B_DataWrite <= (others => '0');
  B_WE <= '0';

  DPBRAM32x256_1 : DPBRAM32x256
    port map (
      pnReset  => pnReset,
      pClock   => pClock,
      AddressA => pAddress,
      AddressB => pSeqTableAddr,
      DataInA  => pDataIn,
      DataInB  => B_DataWrite,
      WriteEnA => A_WE,
      WriteEnB => B_WE,
      DataOutA => pDataOut,
      DataOutB => pSeqTableOut);

end architecture RTL;
